WO1993019419A1

WO1993019419A1 - Solid state disk emulator apparatus and method

Info

Publication number: WO1993019419A1
Application number: PCT/US1993/002533
Authority: WO
Inventors: Keith R. Fritze
Original assignee: Curtis, Inc.
Priority date: 1992-03-16
Filing date: 1993-03-16
Publication date: 1993-09-30
Also published as: AU3814093A

Abstract

A solid state disk emulator (100). The solid state disk emulator (100) of the invention comprises a microcontroller (20) interfaced to a custom logic device (30) that interfaces the microcontroller (100) to a memory decode device (40) and memory buffer (50). The memory buffer (50) can be constructed from flash memory devices. The solid state disk emulator (100) interfaces to an external host system through an I/O decode logic device (70). The microcontroller (100) provides a 'non-interleaved mode' of operation, an 'interleaved mode' of operation, a method of finding the first free entry in the disk, a method of writing a single byte to the disk, a method of checking if the programming voltage is active, a method of writing the disk to zero, and a method of erasing the disk. The solid state disk architecture is intelligent which allows less overhead by the central host microprocessor. Many of the operations can be performed independent of the host system, erasure and programming of the devices are done via a DMA channel or are done autonomously with no intervention by a host microprocessor or host system processor.

Description

SOLID STATE DISK EMULATOR APPARATUS AND METHOD

This invention relates to a solid state disk emulator apparatus and method and more particularly to a computer controlled solid state non-volatile memory apparatus and method that emulates a magnetic or optical disk drive.

BACKGROUND OF THE INVENTION Solid state disk emulators constructed from non-volatile memory are known in the art. Market demands call for disks of increasing storage capacity. Solid state disks constructed of Flash Memory from Intel Corporation, Santa Clara, CA provide one method of increasing storage capacity. However these disks suffer from a number of difficulties that prohibit their integration into conventional computer architectures. Therefore it is the motivation of the invention to provide a computer architecture that allows the use of Flash memory devices in a solid state disk. One of the important advantages of the invention is that it provides a method and apparatus for programming and erasing many flash devices simultaneously at very high speeds as compared to conventional software oriented algorithms. Another advantage of the present invention is that standard programming of flash devices when programming data to the flash devices is much faster than a standard microcontroller software controlled algorithm loop. SUMMARY OF THE INVENTION The solid state disk emulator of the invention comprises a microcontroller interfaced to a custom logic device that interfaces the microcontroller to a memory decode device and a memory array. The solid state disk emulator interfaces to an external host system through a I/O decode logic device. The microcontroller provides a "non-interleaved mode" of operation, an interleaved mode of operation, a method of finding the first free entry in the disk, a method of writing a single byte to the disk, a method of checking if the programming voltage is active, a method of writing the disk to zero, and a method of erasing the disk. The solid state disk architecture is intelligent which allows less overhead by the central host microprocessor. Many of the operations can be performed independent of the host system, erasure and programming of the devices are done via a DMA channel or are done within the architecture itself with no intervention by a host microprocessor or host system processor. It is one object of the invention to provide a solid state disk emulator apparatus and method that provides the programming and erasing of a number of flash memory devices simultaneously at very high speed. It is another object of the invention to provide an improved solid state disk emulator apparatus and method that allows the central host microprocessor to avoid the management overhead of the flash devices. It is yet a further object of the invention to provide the erasure and programming of flash devices via DMA channel.

It is yet a further object of the invention to provide an integrated solid state disk emulator apparatus.

It is a further object of the invention to provide an improved solid state disk emulator that uses a gate array that allows a decrease in printed circuit board and chip space as compared to prior art systems. Other objects, features and advantages of the present invention will become apparent to those skilled in the art through the description of the preferred embodiment, claims and drawings herein where like numerals refer to like elements.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows a high level schematic of the flash disk architecture.

Figures 2A and 2B show a circuit schematic of a microcontroller memory for the flash disk architecture of the apparatus of the invention.

Figures 3A - 3C are intended to be read together to show a non-interleaved mode method of the flash core architecture of the invention. Figures 4A, 4B and 4C show a gate array data path logic for the flash core architecture of the apparatus of the invention.

Figure 5 shows a timing diagram for a Vpp control algorithm of the flash core architecture of the method of the invention.

Figures 6A - 6C are intended to be read together to show a final first free entry method of the flash core architecture of the invention.

Figures 7A and 7B are intended to be read together to show a write single byte entry method of the invention.

Figures 8A - 8J are intended to be read together to show a program interleaved mode method of the invention. Figure 9 shows a check VPP active method of the invention.

Figure 10 shows an erase device method of the invention.

Figures 11A - 11D show the timing diagrams for the write devices to zeros method of the invention. Figures 12A-12F are intended to be read together to show the program device to zeros method of the invention.

Figures 13A - 13G are intended to be read together to show an erase device method of the invention.

Figure 14 shows a register block diagram for an erase queue as employed by the method of the invention. Figure 15 shows a schematic of the operational command apparatus.

Figure 16 shows the method of the invention of monitoring the programming voltage during the idle loop. Figure 17 shows the method of the invention for controlling the programming voltage.

DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 shows the solid state disk emulator apparatus has a high level schematic block diagram. The solid state disk emulator 100 is shown as comprising a flash core architecture device 10 interfaced to a memory array 60 through decode logic 40 and buffer 50. The flash core architecture device 10 is also interfaced to a system bus 72 by I/O decode logic 70. The system bus 72 may be alternately a VME bus from Motorola, the personal computer bus, PC bus which is an International Standards ISA bus, a micro-channel bus from IBM and the Standard Bus which is a bus standard in European countries. The I/O decode logic 70 is interfaced to the flash core architecture device 10 through bi¬ directional bus 68. The flash core architecture device 10 comprises a controller 20 and a gate array 30. The controller 20 is interfaced to the gate array 30 through three control lines 22, 24 and 26. The interface line 22 is an output control line from the microcontroller to the gate array 30. The input status line 24 receives or sends input status from the gate array 30 to the controller 20. The bi- directional data bus 26 sends data back and forth from the controller 20 to the gate array 30.

Figures 2A and 2B show a block diagram schematic of the microcontroller 128 of Figure 1. The controller 20 is shown as comprising three elements. The first element is an electrically erasable programmable read only memory (EEPROM) 120. The second component is a microcontroller 128 and the third component is a latched EPROM 102. The latched EPROM 102 is comprised of an EPROM with a latch that can buffer a multiplex address line 104A. The multiplexed address and data line 104A is used to reduce the pin count of the respective embodiments of the invention but those skilled in the art will recognize that a non-latched EPROM may also be used to accomplish the same function.

Now referring to the microcontroller 128 of the invention. The microcontroller that is being used in one embodiment of the invention is the 80C31 PCC which is available from INTEL Corporation. The microcontroller 128 has a number of input output and control lines that are used in one embodiment of the invention. In the solid state disk emulator apparatus the microcontroller has a multiplexed address and data line with the high level address being non-multiplexed shown in 104B. The multiplex address data line is shown as 104A. The microcontroller is interfaced through 104A and 104B to the latched EPROM 102. The microcontroller 128 has an I/O port 121 which has 8 pins. The first 4 pins pin 0, pin 1, pin 2 and pin 3 are connected to the serial EEPROM 120.

The controller 20 of the solid state disk emulator apparatus of the invention has a number of control inputs. The first one being the ALE (address latch enable line) which is used to latch valid addresses from the multiplexed address data bus 104A. It is used both for the gate array and for the latched EPROM 102. The function of the ALE is to latch valid addresses from multiplexed address data bus. The controller 20 has a control line CPURD 110. The CPURD control line is used to read data from external devices. In the preferred embodiment of the invention data is read data from the gate array 30. If the CPURD 110 read line is in a high state, it is inactive; it is active low. The microcontroller 128 also has a CPU write line, CPUWR 112 which has the same activation meaning. The CPU memory select lines, MEMSEL 114, are connected to general purpose port I/O pins and they are used for bus configuration of memory used for BIOS purposes. The I/O select pins 118 are also connected to general purpose I/O port pins for general purpose bus I/O selection. The Vpp enable line 116 is also connected to a general purpose I/O port pin and is used for the purpose of enabling the Vpp power to the flash memory array 60. The controller 20 also has two input lines INT0STAT0 124 and STAT1 122. INT0STAT0 124, is used for receiving status from the gate array 30 as is the STAT1 122 line. Now that the structure of the controller 20 of the solid state disk emulator apparatus and method of the invention has been described, the function and operational characteristics of the controller 20 will be discussed. The controller 20 is responsible for controlling the disk emulator apparatus. The controller 20 actually implements a number of commands. These commands include high performance flash programming, high performance flash erasure algorithms, first free and blank checking algorithms, general purpose commands, signature commands, diagnostic commands and VPP power sequencing and control.

Commands specifically implemented by the microcontroller 128 include: reading EEPROM bytes from the serial EEPROM 120, writing EEPROM bytes to the serial EEPROM 120, reading flash memory array device types and manufacture codes, bank checking flash devices, programming bytes through the programming algorithm, both non-interleaved and interleaved, erasing flash devices, executing diagnostic writing of single bytes out to a flash memory device, erasing the entire EEPROM device 120, erasing a single flash memory device, finding first free, checking VPP active, writing signature data and writing data patterns to flash memory devices as well as resetting flash memory devices.

08 Erase Flash Devices Beg Device no. #Dev & Dev

Siz;

09 Execute Diagnostic Subcode 1 Subcode 2; 0A Write Single Byte Data byte N/U; OB Erase Entire EEPROM N/U N/U;

0C Erase Single Device Device no. Dev Size;

0D Find First Free End Device no. #Dev & Dev

Siz;

0E Check Vpp Active Beg Device no. #Dev & Bank#;

OF Write Signature N/U N/U;

10 Write Data Pattern #Dev & Pat Type N/U;

11 Reset Flash Devices Beg Device no. #Dev &

Bank#;

Now referring to Table 1 which shows the command codes of the apparatus and method of solid state disk emulation of the invention. The command codes are transmitted on data bus 104 . The command codes are numbered in hexadecimal from 01 to 11 and are listed in Table 1.

Command code 01 commands the microcontroller 128 to read a byte of data from the EEPROM 120.

Command code 02 commands the microcontroller to write a byte to the serial EEPROM 120. Command code 03 commands the microcontroller to read a device-type code from a flash memory device.

Command code 04 commands the microcontroller 128 to read the flash memory's manufacturers code from a designated flash memory device.

Command code 05 allows the microcontroller 128 to issue a blank check command to the gate array to start the blank checking process on a particular flash memory device. Command code 06 allows the microcontroller 128 to interact with the gate array 30 to perform programming operations for the flash memory devices in non-interleaved mode.

Command code 07 allows the controller 20 to interact with the gate array 30 to perform flash programming algorithms for programming bytes in an interleaved mode.

Command code 08 allows the controller 20 to interact with the gate array 30 to erase flash memory from 1 to any number of flash memory devices. Command code 09 allows the controller 20 to execute built-in test diagnostics.

Command code 0A allows the controller 20 to interact with the gate array 30 to program a single flash memory data byte. Command code 0B allows the controller 20 to erase an entire EEPROM device 120. Command code 0C commands the controller 20 to interact with the gate array 30 to erase a single flash memory device. Command code 0D commands the controller 20 to interact with the gate array 30 to find the first free data byte on a particular set of flash memory array devices using an algorithm. Command code 0E commands the controller 20 to check to see whether VPP is still active on the flash memory array. Command code OF commands the microcontroller to write a signature into the gate array counters to be read by the I/O bus interface. Command code lOHex commands the microcontroller to write a data pattern to a number of flash memory devices to test their integrity, it is a built in test diagnostic function. Command code llHex allows the microcontroller to reset from 1 to any number of flash devices.

Now referring concurrently to Figures 4A, 4B and 4C and to Figures 3 - 3C which may be read pieced together to show a block flow diagram of the non-interleaved mode programming of the flash memories. The process flow diagram of Figure 3A begins with non-interleaved mode entry block 130. The process then flows to block 132 where the microcontroller turns on V_pp. The process then flows to block 134 where the controller 20, loads a gate array control register 223 (shown in Figures 4A, 4B and 4C) . The gate array control register is set up for non-interleaved double-buffered mode. The process then flows to block 136 where the microcontroller 128 sets the gate array 30 in single cycle mode. At decision logic block 142 the process waits to see whether or not data becomes available, if data does not become available, a DMA time out is invoked where otherwise the process then flows to block 144 where the microcontroller 128 writes DMA time-out status code to gate array 30 to the controller 20 status register 208. The DMA time-out period may advantageously be about 65 milliseconds. Otherwise, the process flows to block 146 where the controller 20 writes a command code to gate array 30 to start the logic state machine within the gate array 30 to write the program command from register 204 and data from register 218B or 216B in gate array 30.

The process then flows to block 148 where the controller 20 sets up a software counter to a value of 24. The process then flows to block 150 where the microcontroller waits for the remainder of the 10 microsecond time-out period until expires. The process then flows to block 152 where the controller 20 activates the gate array 30 logic state machine to write a program verify code from UC data register 206 in gate array 30 to the flash memory array 60 in Figure 1. The process then flows to block 154 where - li ¬

the controller 20 waits for the remainder of the 6 microsecond time-out period. The process then flows to block 156 where the controller 20 writes a read, compare, increment command to the gate array 30 that causes the logic state machine to activate and execute a read from memory array 60 and does an automatic comparison using the compare logic 242 in gate array 30 to determine whether or not the data was valid. If the data wrote correctly, the address counter 232 and chip enable counter 230 automatically increment. Next, the write data selects multiplexer 220 and gate array 30 automatically ping-pongs to the next register 218B or 216B in gate array 30, if there was not a failure. If there is a failure, the process then flows to block 160 where the type of data compare failure is determined. At this point if there is no failure, the process flows to block 162 where DMA operation complete is tested. If there are no more data bytes to write out to the flash memory array 60 (Figure 1) , then the process flows to block 168 where the memory bank enable bits are disabled in gate array 30.

The process then flows to block 170 where the controller 20 turns off V_pp. The process then flows to block 172 where the controller 20 writes a status ^••good" code to the microcontroller status register 208 and this particular routine is exited.

Now referring to the process block 158, if the read data compare was successful and new data was available, then the process flows back to block 146 and the entire process is repeated until completed. If there was a read data compare failure at block 160 then the process flows to block 174 where the software pulse counter is decremented. If the pulse count is unequal to zero, the process then flows to block 176 where the controller 20 activates an operational command in the write command/data logic state machine, shown in detail in Figure 15, within gate array 30, and the process flows back to block 148. If the pulse count was equal to zero in block 174, the process then flows to block 178 where the memory banks are disabled within gate array 30. The process then flows to block 180 where the controller 20 turns off V_pp. The process then flows to block 182 where the controller 20 writes an flash memory write failure code to gate array status register 208. The process then flows to block 184 where the process returns to the main idle loop. If the DMA operation was not completed within block 162, the process then flows to block 164 where the controller 20 waits for DMA byte to be written into gate array 30 registers either 218 or 216. If this process is successful, the process then continues at block 146, otherwise if there is a time-out, the process flows to block 166 at which time the controller 20 writes a DMA time-out status to the gate array 30 microcontroller status register 208. The process then flows to block undefined, it exits at this point back to the microcontroller main idle loop. Figures 4A, 4B and 4C show an application specific integrated circuit for flash core architecture in schematic form. Multiplexer 202 interfaces to the microcontroller through line 104A. The microcontroller is shown in schematic form in Figures 2A and 2B. Those skilled in the art will recognize that input line 104A is a bi-directional bus which is also fed to MSO MUX 222, microcontroller status register 208, flash memory command register 204 and microcontroller data register 206. Multiplexer 202 multiplexes the signal line 104A on the microcontroller data bus. Figures 4A, 4B and 4C show a block diagram of data paths. Multiplexer 202 multiplexes the microcontroller data bus 104A to four lines, the first line being an input status line 247, the second line being a signal , line 52B which provides the output data from the MAO MUX 236. The multiplexer uses signal line 250 which is input data from the memory array. The memory array is shown in Figure 1 as memory array 60 and it interfaces to the data logic of Figures 4A, 4B and 4C through line 250 shown also on Figure 1. Signal line 250 passes through a first buffer 50 before entering the memory array 60. Signal line 250 is a bi-directional bus. The MUX 202 next controls the output to a fourth line 252 which is input to a microcontroller multiplexer 214 which is the microcontroller command register. Those skilled in the art will recognize that multiplexers 214 and 202 could be combined to multiplex the lines of MUX 214. MUX 214 then controls the data bus from the output of the data bus 104A through MUX 202 through an additional status input line 215 and a microcontroller data input line 260.

Microcontroller command register 212 interfaces to MUX 214 through line 260, register 212 receives an input from the bi-directional data bus 68 from the I/O decode logic 70 shown in Figure 1. MUX 210 drives bi-directional buffer 211 which in turn drive bi-directional bus 68. MUX 210 multiplex's signal lines, the first being a miscellaneous status signal 259. The next line being line 258 from microcontroller status register 208 which receives information through line 104A from the microcontroller 128. MUX 210 also receives information from the counter MUX 224 through signal line 247. The output of the counter MUX also is connected to multiplexer 202 as the first multiplexed line signal 247. The last multiplexed line of MUX 210 is the input data line 250 from the memory array through buffer 50 shown in Figure 1. Control registers 204 and 206 receive data from the microcontroller data bus 104A for execution of the various system commands which are shown in Table 1. Register 204 has an output line 254 which drives the MAO mux 236. Register 206 has an output line 256 which also drives an alternative input signal for the MAO MUX 236. The MAO MUX 236 is also connected to the output of the data MUX 220 and also connected to the output of the MSO MUX 222. Input data from the I/O decode logic 70 bi-directional bus 68 is also connected to a set of data registers 218A, 218B, 216A and 216B, and the MSO MUX 222. The data registers 218A and 218B function as a ping pong buffer.

The general purpose DMA interface writes alternatively to each one of the registers 218A, B and 216A, B in parallel to write data out to the memory array 60. Dual ping pong buffers run fast in interleave mode. The invention writes two bytes instead of just one and ping pongs between those two bytes. The registers are going to hold data for those two devices, as data is written out to the memory array not simultaneously but sequentially. Another set of registers buffer incoming data. A ping pong memory is needed is because for writing in interleave mode. The system must to be able to toggle between two sets of data when writing data bytes out to the flash memory array, at the same time. For example, two flash devices use the command register architecture to write data from both registers 216B and 218B. These flash devices use buffers to be able to write to registers 218B and 216B.

MSO MUX 222 drives the MSO line 262 which drives five devices, the first being the last input of the MAO mux 236, chip enable register 234, the address counter 232, the chip enable counter 230, and the chip enable upper bounds register 228. The function of the chip enable upper bounds register 228 is to drive line 264 which is connected to a comparator 238 which compares the output of the chip enable upper bounds register 228 to the chip enable counter 230 output on line 266. The output of the comparator 238 is sent to the logic state machine and input to the control logic for the flash core memory architecture of the method and apparatus of the invention. The output of the chip enable counter 42A, B is also sent to the input of the decode logic for the memory array 60 on bus 42.

The output of the comparator 238 allows programming and erasure of multiple devices. With an array of flash memory devices programmed to zero a logic state machine handles the necessary commands to write to all of these devices sequentially to 32 flash memory devices. The invention exploits the command register architecture of the flash memory devices used in the memory array 60. Commands can be sent to multiple devices rather than just one device to speed up the programming operation.

The output of the address counter 232 is connected to signal line 52A which drives the address line directly. The address counter 232 provides the full address for the flash memory devices. Part of the chip enable register 234, seen on signal line 268, is connected to enable control masking buffer 240, which masks off two banks select bits for the control line 42B. The control line 42B interfaces to the memory array 60 through I/O decode logic 40. The output of the MAO MUX 236 goes to the signal line 52B which is buffered by bidirectional buffer 251 which drives the memory array through buffer 50. The signal line 250 also is an input to a comparator 242. The output of MAO MUX 236 also appears as an input to the transition compare logic 244 which enables the writing of flash memory devices from ones to zeros, but not zeros to ones. The invention reads from the memory array in comparing a block of data which could be an MSDOS file, to see whether or not there were any zero to one transitions. If there were zero to one transitions the data buffer can not be overwritten. Once a one to a zero has been written the whole device must be erased. The flash file system of the invention handles the high level file system operations, but the zero to one detection process occurs much faster. Transition compare error signal 245 indicates whether or not a zero to one transition has occurred in the transition comparison logic 244. Bi¬ directional bus 68 is also fed to the control register 223 which is connected to the input data bus 104A from the controller 20. The MUX selects between the four principle addressing and enabling buses of the memory system. Counter MUX 224 drives line 247 which as described above is the first input to MUX 202 and the second input to mux 210. Figure 5 shows the Vpp control algorithm diagram for the solid state disk emulator of the invention. There are five sequences to go through to on the Vpp starting sequence. First, Vpp is turned on in step 501. A write operation requires Vpp to be 12 volts plus or minus 5%. There is a turn on period associated with Vpp. Second, while Vpp is turning on, write operations are done in step 502. Third, Vpp is left on for a delay period, step 503. The devices can be programmed when Vpp is on, when it is off the devices cannot be programmed. There is a transition point during the delay period where it is not stable. The system must wait until Vpp is stable before programming.

The predetermined wait period is also dependent upon the capacitance in the inputs and how many devices have been attached to the Vpp line. The capacitance is quite high because decoupling capacitors are attached to that line. The device input capacitance is low. Decoupling is associated with this line when programming, all those capacitors need to be charged.

When step 503 is completed, a delay period of two seconds is begun. This delay period allows the performance of another write function. This prevents the delay associated with turning Vpp off and incurs this Vpp off delay plus the Vpp on delay again. It saves a lot of time over prior art devices. This may be a nominal delay of about two hundred milliseconds.

A read function may occur between step 503 and step 504. If a read function occurs between steps 503 and 504 the particular flash device or devices that are read from must be set into a read state. As step 503 is completed and it is a program erasure operation the flash devices are not necessarily in a read state. They are usually in a idle state. The command that allows writing the read command codes out to all the flash devices must be executed. If a read or write request occures then the delay period is re-enabled for another two seconds. Events happen within a flash file system that make this advantageous because whenever the system writes pointers they will be written all over the memory arrays in order to link and unlink files.

If Vpp is on a read can be processed but in order to do a read, the system has to write a read command function out to the flash memory array device. The system can read while writing, but cannot read and write simultaneously. The system does not have to change Vpp to read, but the system has to write a command code out to the devices to tell it that it is in a read mode and not in an idle mode. At this point in time there is another delay period at which the capacitors that are attached to this Vpp line are discharging, step 504. During this discharge period the system cannot perform any functions. It has to wait until discharge is complete, step 505.

Part of the algorithm will allow the determination of whether or not the system is in this transition period.

Figure 16 shows the process flow diagram for Vpp in the idle loop. The process starts at process block 185 at system start. The process then flows to process block 186 where the power on initialization occurs and Vpp CNT is set to zero and Vpp CNTD is set to zero. Those skilled in the art will recognize that the two second wait period can be varied depending upon the time of the Vpp to Vcc discharge and the performance of the system in general. Other waiting times may also be appropriate and the two hundred milliseconds is just given as an example and not by way of limitation.

The process then flows to process block 188 where the Vpp timer overflow flag is set to see whether the Vpp timer has expired. If the timer has not expired the process flows to process block 207 where the microcontroller checks for a new command to process. If there is not a new command the process then flows back to checking for the Vpp timer for overflow at process block 188, if the microcontroller has a new command then the new command is executed in process block 209 and the process returns to wait for the Vpp timer overflow to set at 188. If the Vpp timer overflow flag indicates that the two second delay has occurred the process flows to process block 190 where the Vpp on counter will be set when anyone of the following commands which are listed in Table 1 are executed 3, 4, 6, 7, 8, 9, A and C. Process block 190 checks to see whether the Vpp on delay counter has expired and if it has not the process flows to process block 198 where the Vpp on delay counter is decremented. The process then flows to step 200 where the Vpp on delay counter is checked for expiration and if it has not expired, the process flows to reinitialize the delay timer at process block 205.

The system has a counter timer that is running as well as a software delay counter in order to extend the delay time to a desired amount, the counter timer expires after 50 milliseconds so the system needs a multiple of 50 milliseconds. This software delay counter functions as an overflow flag so that the system knows that 50 milliseconds has expired delay counter needs decrements N number of times. N being what is needed to extend the delay at process block 198. If the delay count has expired at process block 200 then turn off Vpp. If it has not, at process block 203, expired then reenable the counter timer for another 50 milliseconds at process block 205. Take the other path here, process block 190; if the count delay has expired then drop down and decrement the Vpp turn off delay counter Vpp CNTD at process block 192. Then check to see whether or not the turnoff delay time has expired in process block 194. If it has expired then clear the counter timer function 196. If it has not expired the count timer in process block 205 is re-enabled.

Now referring to Figures 6A - 6C which are intended to be pieced together to show the schematic diagram to find the first free entry in the flash memory. Process block 602 shows the entry point for the routine. The process then flows to block 604 where the microcontroller 128 scratch pad registers are set up and initialized. The microcontroller register bank has the following designations: R7 is the number of pages to search, R6 is the number of the device to check, R5 is the last device number, R4 is the current device number, R3 is current page number being checked. The process then flows to step 606 where the buffer registers 216 and 218 are set to FFH. The process then flows to step 608 where the counter is set to reverse linear search mode and the control register is cleared. The control register is shown on Figure 4C as control register 223. The counter set in process block 608 is part of Figure 4C counter 232. The process flows to process block 610 where the address counter 232 and the chip enable counter 230 are initialized. The process then flows to 612 where the R3 register is initialized with the total number of pages in the device, which in one embodiment of the invention is 32 pages for a 128 K device. The process then flows to process block 614 where the microcontroller issues a "read page with compare" command to the- gate array logic state machine. The process then flows to 616 where the wait search routine is called which is shown in Figure 6C. The process then flows to 618 where the condition is checked for whether the search failed for this page, if it has failed the process flows to process block 630 where a "write blank check failure" status code is written to the gate array status register 208 in Figure 4A. If the search did not fail then the process flows to 620 where the page count is decremented. The process then flows to 622 where a test for the last page in this device is made. If this is the last page in this device then the device count is decremented at process block 624. If this is the last device to be tested in this block of devices in process block 626 then the process flows to process block 628 and write an "all blank" status code to the gate array status register 208 on Figure 4A. The process ends at 633 where the process returns to the idle loop shown in Figure 16. In either of case at process 622 or 626 if the device being checked is not the last device the process flows to process block 610 to begin the blank block checking process.

Now referring to Figure 17 which shows the method of the invention used to turn the programming voltage on. The method of Figure 17 first enables the Vpp power switch in step 1440. Next the method waits for the programming voltage to reach a predetermined value for a specified period of time in step 1442. In one preferred embodiment of the invention the process waits for 20 milliseconds. THe process then initializes the Vpp on Counter in step 1444, shown in Figure 16. The process then initializes the Vpp turn off delay counter in step 1448, also described in Figure 16. Now referring particularly to Figure 6C which shows the method of the invention used to wait for a search to complete. The process begins at process block 632 and then flows to 634 where the microcontroller time out counter is set to a value representing the latency associated with testing one page. The process then flows to block 636 to test whether or not the particular operation timed out, if the operation timed out the process flows to process block 644 and the carry flag is set indicating an error occurred. If the process block did not time out, it flows to process block 638 where a test is made to determine whether or not the particular page operation has completed. If the page operation has not completed then the process returns to block 636 until it has completed where in which case it flows to block 640. If there is a page compare failure the carriage flag is set indicating that there was a non FF byte that was within this particular page, and the process exits. Next, turn to the first free routine process block 646, if there was not a page compare failure in process block 640 the process flows to process block 642 where the carriage flag is cleared indicating that the particular page that was tested did not have all FF bytes. In any other case of setting the carry flag at step 640, a clear carry flag at step 642, or the set to carry flag at step 644, the process returns to the idle loop in Figure 16.

Figures 7A and 7B may be read together to show a process and method of the invention for the flash core architecture to write a single byte in a flash device. The process starts at step 650 where the microcontroller has issued a write single byte command, the process then flows to 652 where Vpp is turned on to the correct state as shown in Figure 5. The process then flows to 654 where the control register is set up. The process then flows to block 656 where a flash program command code is written to the gate array flash memory command register 204 in Figure 4A. The process then flows to 658 where the "flash program verify" command code is written to register 206 in Figure 4A. The process then flows to 660 where the pulse counter register is set to 25 in scratch pad ram in the microcontroller. The process then flows to process block 662 where a "write command/data" command code is written to the flash gate array in Figures 4A, 4B and 4C.

The logic state machine will use the flash memory register 204 and the one of the write data registers 216 or 218 to write data command codes and data out to the flash memory array. The process then flows to step 664 where the process waits for ten microseconds. Those skilled in the art will recognize that the ten microsecond wait is by way of illustration and not limitation and that other devices and systems may wait other predetermined times. The process then flows to step 668 where the "program verify" command is sent to the flash gate array of the invention 30. The process then flows to step 670 where the process waits six microseconds. The process then flows to step 672 where the "send read compare with increment" command is sent to the flash gate array in Figures 4A, 4B and 4C. The process then flows to step 674 where the data is compared and checked if it is the data that is actually written to the flash memory device. If it is the correct data the process flows to process block 676, if it is not the correct data the process then flows to block 682 where the pulse counter is decremented. The process then flows to step 684 where the pulse counter is checked for whether or not its state is zero. If it is zero, the process then flows to step 686 where the memory bank enable bits CENO and CEN1 are disabled. The process then flows to step 688 where the Vpp is turned off. The process advances to step 690 where the EPROM write failure is checked.

The process then exits to return to the idle loop of Figure 16 at step 692. If the data compared is correct then the process flows to step 676 where the disabled memory bank enable bits are set. The process then flows to step 678 where Vpp is turned off to indicate that the write cycle is over. The process then flows to step 680 where the "send status good" command is written to the gate array status register 208 in Figure 4A. The process then ends at 692 by returning to the idle loop of Figure 16. The "Set up logic state machine" process can accomplish two writes depending upon what the user decides to select.

Figures 8A - 8J may be read together to show the interleaved mode of the method and apparatus of the invention. In the provided method devices are programmed substantially simultaneously. The system uses the capabilities of the gate array hardware elements 216A, B and 218A, B as ping pong buffer registers so a single byte from each one of those registers can be written to the two flash memory devices. The first part of the algorithm has a standard set up and an inner loop is entered, this inner loop allows data to be written very quickly. The process continues until the data is completely written.

The interleaved mode routine of the method of the invention starts at process block 802 where the system issues a program interleave mode command. The process then flows to step 804 where Vpp is turned on for a write cycle. The process then flows to step 806 where the gate array control register is set for a double buffered, interleave mode of operation. The process then flows to step 808 where the gate array is set to "single cycle logic state machine" mode. The process then flows to step 810 where the write flash program code to gate array is sent to register 204 in Figure 4A. The process then flows to step 812 where the microcontroller data register 206 in Figure 4A is set to "flash program verify" command. The process then flows to step 814 where the device number is set from the chip enable counter 230, shown in Figure 4C. The process then flows to check whether the device number is even at process block 816. If it is even, the process then flows to Figure 8B at balloon A. If the device number is odd then the process flows to 818 where the DMA BP register and the DMA register are set. The process then flows to 820 where the "DMA wait" routine is called which is shown in Figure 8F. The process then flows to check whether the carry flag is set, if it is, the process flows to balloon B, the DMA time out routine shown in Figure 81. If the carry flag is not set the process flows to Figure 8B process block 824 where the call "write single byte" routine is executed. The process then flows to block 826 which determines whether or not there was a write error. If there was a write error then the process flows to balloon C. If there was not a write error the process flows to process block 828 where the condition is checked for whether or not the DMA operation is complete. If it is the process flows to Balloon D. If it is not the process flows to block 830 where the DMA wait routine is called. The DMA wait routine is shown in Figure 8F. The process then flows to 831 to check for DMA timeout. If there is a DMA timeout the process flows to balloon B, if there is not the process flows to process block 830 where a "write command/data" command is issued by the microcontroller to the gate array 30, shown in Figures 4A, 4B and 4C, to start the first writing of the first byte.

The process then flows to step 834 where the condition is checked for whether the data buffer 2 is empty. If data buffer 2 is empty, then process flows to balloon E. Data buffer 2 is shown on Figures 4A, 4B and 4C as either register 218 or register 216. The process then flows to 836 where the "write data" command is written to the second device. The two buffered registers are 218A, B and 216A, B. The process then flows to step 838 where the pulse counter is initialized to 24. The write process can be attempted 25 times. Flash memory can only be written 25 times before it indicates a failure. Those skilled in the art will realize that the flash memories used in the flash core architecture can only be written at a maximum of 25 times according to one flash memory architecture description. Other flash memories may vary. The process then flows to 840 where the ten microsecond delay is executed. The process then flows to 842 where the "program verify command" is sent from the microcontroller to the gate array to the first device data byte. The process then flows to 844 where the microcontroller issues a "program verify" command to the second device. The process then flows to step 846 where the microcontroller issues the "read compare increment" command to the first device. The process then flows to step 848 where the condition is checked for whether the data compare has failed. If it has, then the process flows to balloon F, if it has not, the process flows to 850 where the microcontroller issues a read compare increment command to the second device data byte.

The process then flows to 852 where a condition is checked as to whether the read compare was successful, if it has been, the process flows to balloon G, if it has not, the microcontroller gets a program DMA status from the gate array which is shown on Figure 430, this is occurring in process flow block 854. The process then flows to step 856 where the condition is checked for whether or not the second byte program is functioning properly, if it is the process flows to process flow block 858, if it is not, the process flows to process flow block 864.

If the second byte programmed successfully, the process flows to block 858 where the DMA operation is checked for completeness. If it is complete the process flows to balloon D, if it is not the process flows 860 where the DMA wait routine is called which is shown in Figure 8F. The process then flows to 862 where the DMA timeout is checked, if it has timed out the process flows to balloon B, if it has not timed out the process flows to Figure 8D where the microcontroller executes a write single byte routine 872 which is shown in Figure 8J. The process then flows to step 874 where the condition is checked for a write error, if there is a write error then the process flows to balloon C, if there is not a write error the process flows to balloon G. If the second byte program is not functioning properly, at process block 856 the process flows to 864 where the microcontroller 128 calls the write single byte routine which is shown in Figure 8J. The process then flows to step 866 where the condition is checked for whether the write was error- free, if the write was error-free the process flows to balloon C. If the write fails the process flows to step 868 where the DMA operation is checked for completeness, if it is complete the process flows to balloon D, if it is not the process flows to process block 870 where the DMA is checked for time out. If the DMA is timed out the process flows to balloon B, if the DMA has not timed out the process flows to balloon G.

Now referring particularly to Figure 8E which shows the method of the flash core architecture of the invention's process for handling the condition where the data buffer number 2 is empty. The process begins at balloon E and process block 876 where the reset mask is applied to the second data byte. The process then flows to step 878 where the controller 20 issues a "program verify" command to data byte 1 and the process then flows to process block 880 where the controller 20 issues the "recompare increment" command to the first data byte. The process then flows to step 882 where the condition is checked for whether the data byte from the flash memory array of the first device compares correctly with the data byte that is in either register 218 or register 216.

The process then flows to block 884 where the microcontroller obtains the program DMA status from the gate array. The process then flows to step 886 where the condition is checked for whether the DMA data buffer is full and for the second data byte. If it is not the process flows to balloon H, if it is the process flows to process flow block 888 where the controller 20 calls the "write single byte" routine shown in Figure 8J. The process then checks for a write error in 890 and if there is a write error the process flows to balloon C, if it is not the process flows to balloon H.

Referring now to Figure 8F which shows a schematic block diagram of the DMA wait routine of the method of the flash core architecture of the invention. The DMA wait routine is called in step 891 and begins by setting up a 65 millisecond deadman timeout counter at 892. The process then flows to step 894 where the controller 20 obtains the program DMA status from the gate array. The process then flows to step 896 to determine whether the buffer data is available, if it is not the process flows to step 898 where the deadman timer is checked for a timeout. If the deadman timer is not timed out the process again returns to process flow block 894. If the deadman timer has timed out the process flows to step 890 where the carry flag is set and the process then exits to the caller at step 894. If the data buffer is available in step 896 the process flows to clear the carry flag in step 892 and then exits to the caller at 894.

Figure 8G shows a schematic block diagram routine to execute a "flash write error" status code if a write error has occurred. The method of Figure 8G is implemented in a number of places, one being in Figure 8B process block 826, the next being in Figure 8C if a write error occurs in process block 866, in Figure 8D where a write error occurs in process block 874, and in Figure 8E where a write error occurs in process block 890. The "flash write error" routine begins by disabling the memory bank chip enable register 234 shown in Figure 4B. The process then flows to step 898 where the Vpp is turned off. The process then flows to process block 900 where the controller 20 writes a flash programming error code to the microcontroller status register 208 in Figure 4A. The process then exits to the idle loop 901 shown in Figure 16. Now referring particularly to Figure 8H which shows the method and apparatus of the flash core architecture of the invention to execute a "DMA operation complete and successful" indication. "DMA operation complete and successful" routine is called by the process of Figure 8B in process block 828, the routine of Figure 8H is called in Figure 8C in process block 868. The DMA operation complete routine is called in process block 858 of Figure 8C. DMA operation complete and successful routine begins by disabling memory bank enables. Memory bank enables are found in register 234 in Figure 4B. The process then flows to step 904 where Vpp is turned off, the process then flows to step 906 where the microcontroller writes an "operation complete" status code to the gate array. The process then exits to the idle loop 907 shown in Figure 16.

Now referring to Figure 81 which shows the DMA time out routine of the method of the invention. The DMA time out routine is used by the process of Figure 8C in process block 862 and in process block 870 where DMA time out is handled by a DMA time out routine. The process first disables the memory bank enables 908 as shown in Figure 4B as register 234. The process then flows to 910 where Vpp is turned off and the process flows to 912 where the DMA time out failure status is written to the gate array status register. The process then flows to step 914 which exits to the idle loop described in Figure 5.

Figure 8J shows a method and apparatus of writing a single byte routine. The routine starts at process block 915 where a write single byte call is made from a system caller. The process begins by having the controller 20 issue a "write command/data" command to the gate array 30 shown in Figures 4A, 4B and 4C. The process then flows to step 918 where the process waits 10 microseconds. The process then flows to 920 where the controller 20 issues a "program verify" command to the gate array. The process then waits six microseconds in process block 922. The process then flows to step 924 where the controller 20 issues a recompare increment command to the gate array at step 924. The process then flows to compare the data in data buffer register 216 or 218 in Figure 4B to the flash memory data that is written. If the data compares without errors the process then flows to step 928 where the carry flag is cleared and the process flows to step 930 which returns to the caller of the write single byte routine. If the data does not compare in step 926 the process flows to step 932 where the pulse counter is decremented at step 932. The process then flows to step 934 where the pulse counter is checked if it is zero, if it is not zero the process then returns to beginning of the routine at step 916. If the pulse counter is zero the process then flows to step 936 where the carry flag is set and then the process returns to the caller at step 930. There are basically four different commands of the logic state machine that the gate array can execute. The first command is a "write command/data" command that will actually write two bytes out to a particular flash memory device. The second command is a "write data only" command where the system writes a single byte out to the memory, it can either be a command byte or a data byte. The third command is a "read compare with auto increment" command that compares data from the flash memory array. The command compares data in a particular device within the flash memory array to a data byte within one of the two buffer registers 218A, B or 216A, B. The fourth command is a comparison command that is used within the "find first free" routine that does a comparison of data within the memory array to a particular byte either in register 218A, B or 216A, B, also it automatically decrements counters. There are other conditions, too, that the logic state machine can execute after it completes a command. The system can increment the chip enable counters, increment the interleaved counters, or operate in a linear mode where the address counters are linearly incremented or decremented as in the "find first free" routine.

Now referring to Figure 9 which shows the method of the solid state disk emulator apparatus of the invention to check for the programming voltage Vpp's state. The process starts at step 1000 where the check Vpp active routine is entered.

The process then flows to step 1002 where the Vpp on delay counter is checked for zero. The Vpp on delay counter counts the amount of time that the Vpp signal makes a transition from the previous write or erasure state to the time when Vpp is turned off. The Vpp counter can be referenced in Figure 16. If the Vpp on delay counter is zero the process flows to step 1006, if the VPP on delay counter is not zero then the process flows to 1004. Microcontroller scratch pad register R2 stores the beginning device number. R3 represents the number of devices that the system has to write the read command code to. The registers are being loaded in step 1004. There are a predetermined number of devices on the flash file system disk and it is not known which one of those devices are the subject of a read operation from the "read command" code has to be written to the whole memory array. For example, if there are 25 devices, the system writes the read command code to all 25 devices.

The process then flows to step 1008 where the gate array control register is enabled for a "flow through write" operation mode. A "flow through write" operation allows the controller 20 to write directly to the memory array devices without using the internal logic state machine in the gate array.

The process then flows to process step 1012 where the chip enable counter 230 is loaded with a device number to be written. The process then flows to 1016 where the "flash read" command is written to the command register of the device. The process then flows to 1018 where the device number is incremented in R2. The process then flows to 1020 to decrement the number of devices in R3.

The process then flows to 1022 where the number of devices that are left are checked to see if there are any, if there are devices left the process flows to return to process step 1012 to load the chip enable counter 230 with the number of devices to be written. If there are not any devices left the process flows to 1024 where the gate array status register is written with the Vpp on status. The process then returns to the idle loop in process step 1028.

Returning now to the process step 1002 where the delay counter is checked to be zero. If the delay counter is checked to be zero the process as stated before proceeds to process step 1006 where the Vpp off delay counter is checked. If the Vpp off delay counter is zero the process jumps to process step 1026 to load the gate array status register with the "Vpp on or inactive" status.

The process then flows to 1030 to return to the idle loop. Returning now to the check for the Vpp off delay counter in process step 1006. The process flows to process step 1010 if the Vpp off delay counter is not zero to load the gate array status register with the "Vpp off delay" state. The "Vpp off delay" state indicates that we are transcending from the VPP write or erasure state to Vpp equals Vcc or read state. The process then flows to 1014. The gate array status register is loaded with the "Vpp on or inactive" status state meaning that Vpp is either on or in the erase or write state or Vpp equals Vcc is off or inactive.

If the gate array status register is written with a Vpp on status that indicates that the Vpp is in the write or erasure state, Vpp equals 12 volts in one preferred embodiment of the invention. Now that the structure of the Vpp active method has been described the theory of operation will be described.

The "Check Vpp active" method is valuable in cases where writes and reads are being interleaved. Reads cannot be performed when all the flash devices are in the Vpp state. The read command code must be written to the flash devices in order to read. Thus, writes and reads may be interleaved. The systems need a method keeps track of what states the devices are all in.

Now referring to Figure 10 which shows the method of the solid state disk emulator apparatus of the invention used to erase the flash memory devices. The method begins with an erase device command in process step 1030. The process then flows to step 1032 to turn on Vpp. The process then flows to process step 1034 where the "program devices to zero" routine is called. The process then flows to step 1036 where if one or more of the devices were not able to be programmed to zero the system assumes there was a device program error. If there was a device programming error process flow diagram 1046 which loads the gate array status register with a "flash memory write" failure status code. The next step is 1048 which returns to the idle loop. If there was no device programming error the process flows to 1038 which calls the "erase devices" routine. The process then flows to process step 1040 to check for an erasure error. If there was an erasure error the process flows to step 1042 to load the "erase failure" status in the gate array status register. If there was not any erasure error in process step 1040 the process flows to 1044 where the "operation completed OK" status is loaded into the gate array status register. In all cases of process step 1042, 1044, and 1046 the process returns to the idle loop in 1048.

Now referring to Figures 11A, 11B, 11C and 11D which show the state machine processing through memory control commands. There are four separate commands that the logic state machine can execute within the gate array. There is a "write command/data" command as referenced to Figure 11A, there is a "write data only" command as referenced in Figure 11B, there is a "read compare increment" command as referenced in 11C, and finally there is a "compare increment" command that does a linear address increment.

Referring now to the "write command/data" command as referenced in Figure 11A. This command allows the state machine to write a command word and a data word from registers within the gate array for N devices. The command starts with the first device as specified in the chip enable counter 230 during initialization, device N is specified in the upper bounds register. The state machine will start to do writes to the first device. The state machine will continue to increment the chip enable counters for devices at a particular address until it reaches device N at which point in time it completes its operation.

The "write data only" command operates as referenced to Figure 11B. The first device is specified initially in the chip enable counter register and writes a command or data word from internal gate array registers for the first device, second device, until writing device N which is specified in the upper bounds register within the gate array. The "read compare increment" command allows the comparison of one of the internal gate array data registers with memory array data. It starts at the lower bounds as specified in the chip enable counter and continues to do a comparison until device N detects a failure. If N device detects a failure, it stops at the particular device number in which it has failed. A status is returned to the microcontroller indicating whether or not the operation completed successfully or did not complete successfully. The J'read compare increment" command also has one other unique characteristic. If all the devices compared correctly with the memory array data then for each device compared correctly the linear address that is written to the memory array or that is available at each one of the memory array's address inputs will increment by one at the end of the operation. These particular commands are of great importance for the erasure algorithm where devices are programmed to zero. The method allows the programming of 32 devices simultaneously. Now referring to Figure 12A which shows the method of the invention used to program. All the devices of the flash core architecture to zero. The process starts at process step 1100. The process first sets up scratch pad registers according to process step 1102 to register 7 to be the number of memory pages to write. Register 6 will be the upper device bounds register. Register 5 will be the lower device bounds temporary register. Register 4 will be the lower device bounds absolute register. R2 is the pulse counter. Rl is the read compare increment command code address register. R0 is the general external address write register. The B register is the upper or lower memory bank enable byte. The process then flows to clear the gate array control registers in 1104A.

The process then flows to step 1104B where the 64K byte page counter is initialized. The process then flows to 1106 where the "write flash program" command is written to the gate array EECMD register 204. The process then flows to 1108 where the "flash program verify" command is written to the gate array microcontroller data register 206. The process then flows to 1110 where the gate array address counters are initialized to zero. The process then flows to 1112 where the gate array data registers 216 and 218 are written to zero.

The process then flows to 1114 where the upper bounds register 228 on the gate array is loaded from the R6 scratch pad register. The process then flows to 1116 where the gate array chip enable counter 230 is written with the R4 scratch pad register. The process then flows to the beginning of Figure 12B where process step 1118 is executed to write the "write command/data" command to the gate array. The process then flows to 1120 where the device page counter is decremented.

The process then flows to 1122 where the 64K byte page counter is checked for zero. If it is zero the process flows to decrement the page counter in R7 in step 1124, if it is not zero the process skips step 1124 and proceeds to process step 1126 where the remainder of the 10 microsecond timeout period is executed. The process then flows to step 1128 where the "write data" command is sent to the gate array. The process then flows to 1130 where the 6 microsecond wait period is begun and completed.

The process then flows to 1132 where the "read compare increment" command is sent to the gate array. The process then flows to 1134 where the page counter in R7 is checked to see whether it is zero. If it is zero the process flows to A at 1135 which can be found in Figure 12E.

The process then flows to process step 1136 where all the devices are checked to make sure that the comparison was successful, a "read compare" command for each device in step 1132. If it was successful the process returns to process step 1118. If the read compare operation were not successful in process step 1136 the process flows to Figure 12C process step 1138 where the pulse counter R2 is initialized 24.

The process then flows to 1140 where the chip enable counter is read from the gate array and stored in the scratch pad register R5. The process then flows to 1142 where the "write command/data" command is written to the gate array. The process then flows to step 1144 where the microcontroller waits 10 microseconds for the write operation to complete. The process then flows to 1146 where the "program verify" command is sent to the gate array.

The process then flows to 1148 where the R2 pulse counter is decremented. The process then flows to 1150 where the R2 count value is checked to be zero. If it is the process flows to process step 1152 which is found in Figure 12F. If the R2 count value is not zero the process flows to 1154 to complete the six microsecond timeout wait. The process then flows to 1156 where the "read compare increment" command is sent to the gate array. The process then flows to 1158 where the data compare status is checked. If the data compare has failed the process returns to process step 1142 to the "write command/data" command to the gate array. If the process has not failed the process flows to Figure 12D process step 1162. The process flow from 1142-1158 is an outer loop or attempting to program a single device to zero. The process has failed the first time around in the inner loop, which can be found at process steps 1118 through 1136, while programming N devices to zero. The process started at the chip enable counter 230 as a beginning device number, the upper bounds device number is stored at register R6. This process is successful for programming N devices using a logic state machine that which is also much faster than doing single device programming.

The process then advances to Figure 12D where the logic state machine is cleared from single cycle mode. The process then flows to 1164 where the chip enable counter 230 is checked to see whether it is equal to the upper bounds register. If it is the process flows to process step 1119 which would be found in Figure 12B. If it is not the process flows to 1166 to increment the lower bounds register R5 and reload the chip enable counter 230 with R5. The process then flows to 1168 where the "write command/data" command is sent to the gate array. The process then flows to 1170 where the system waits 10 microseconds for the write to complete. The process then flows to 1172 to write the "program verify" command to the gate array. The process then flows to step 1174 to wait six microseconds for the write to complete. The process then flows to 1176 to send a read compare increment command to the gate array. The process then flows to 1178 where the process is checked for whether or not any of the devices have failed. If they have not the process flows to Figure 12E process step 1180. If they have failed the process returns to point D which is referenced in Figure 12C which then reexecutes the send write data to send the "write data command" to the gate array at 1142.

Now referring to Figures 12E and 12F which show the remaining part of the method of the invention to write zeros to the devices. The process flows from 1180 where the process checks whether or not it is the last byte to program. If it is not the last byte to program the process flows to process step 1190 which is found in Figure 12B. If it is the last byte to program the process flows to process step 1182 where the carry flag is cleared. The process flows to 1184 which returns to the caller. The reset command steps in the method are entered through process step 1152 which sends a reset command to all the devices in step 1186. The carry flag is set at step 1188 and then returns to the caller at process step 1190. Process step 1152 is entered through reference to Figure 12C process step 1150 where the R2 count value is checked to see if it is zero.

Now referring to Figures 13A - 13G which shows the method of erasing the flash devices. This particular method will erase from one to N flash devices. In one preferred embodiment of the invention one to sixteen flash devices are erased. The method consists of an initialization portion and an initial erasure operation and then an erase verify portion which is the inner loop. If all the devices were erased during the first ten millisecond pulse, the outer loop would never have to be entered. The inner loop of this particular operation will check from 1-N devices.

The outer loop of this particular operation queues up the devices that have failed in an erasure queue. The method continues to give those devices pulse counts until the pulse counts exceed the manufacturer's recommended number, which in one preferred embodiment of the invention is 3,000 pulses. From one to N devices will be queued up depending upon whether they failed in the original erase verification loop. This operation will continue until all those devices have indicated that they have passed erasure. After this condition the method jumps back into the erase verify loop to verify the remaining number of locations within the N devices that we are testing.

Now referring to Figure 13A which shows a schematic process diagram of the method of erasing the flash devices. The "erase devices" routine enters at step 1200 and proceeds to process step 1202 where a set of registers are set up. R7 is the erase page count register. R6 is the upper device number register. R5 is a general purpose register. R4 is lower device number register. R3 is the device count register. R2 is the interval state time register. Rl is a general purpose address register. RO is another general purpose address register. The B register is the bank enable byte in this embodiment of the invention. The process after setting up the scratch pad register proceeds to process step 1204 where the gate array control registers are cleared.

The process flows to 1206 where the erase command code is sent to the gate array flash memory command register. The process then flows to 1208 where the "erase verify" command code is sent to the gate array microcontroller data register. The process then flows to process step 1210 to initialize the device pulse counts to decimal value 2999. The process then flows to process step 1212 where the gate array data registers are loaded with all ones. The process then flows to step 1214 to initialize the gate array address counters to zero.

The process then flows to 1216 where the chip enable counter 230 is loaded with the lower device bounds. The process then flows to Figure 13B process step 1218 where the upper bounds register is loaded with the upper bounds device number to erase. The process then flows to 1220 where the device location counter is initialized. The process then flows to 1222 where the "write command/data" command is sent to the gate array to start erasure. The process then flows to 1224 where the process waits 10 milliseconds for the erasure to time out.

This command starts the erase verification process. The erasure starts in step 1222 and times out in process step 1224. The process then flows to 1226 where the "write data" command is sent to the gate array. The process then flows to step 1228 to decrement the location of the counter. The process then flows to step 1230 to send the "read compare increment" command to the gate array. The process then flows to step 1232 where the location counter is checked to be zero. If the location counter is zero the process proceeds to process step 1324. If it is not zero the process proceeds to check whether all devices are verified in process step 1234.

If all devices are verified the process returns to process step 1226. If they are not the process proceeds to Figure 13C process step 1236 to initialize the erase queue pointer Rl. The process then flows to 1238 where lower bounds temporary register is set to be the first failed address in R5. The process then flows to 1240 where the microcontroller gets the failed device number from the chip enable counter stored as the first and second entries in the erase queue. The process then flows to process step 1330 which can be found in the bottom of Figure 13C. The process then flows to process step 1254 to check whether the chip enable counter device number is equal to the last device to be tested. If it is the last device to be tested the process flows to step 1334 which is found in Figure 13F. If it is not the last device to be tested the process flows to Figure 13D process step 1256. Now referring to process step 1332 which primarily gets the failed device number from the chip enable counter in process step 1244. The process then flows to 1246 where the condition is checked for whether or not the present failed address is equal to the last failed address. If it is not the process goes to step 1334 which can be found on Figure 13E process step 1268. If the present failed address is equal to the last failed address the erase queue pointer in Rl is decremented in step 1248. The process flows to 1250 where the "present failed device" address is placed in the erase queue. The addresses are device number addresses. The device numbers range from zero to 127 in one preferred embodiment of the invention. Those skilled in the art will recognize that the number of devices could vary.

Referring now to Figure 13D where the process continues by incrementing the present failed chip enable address in 1256. The process then flows to store a new chip enable address as the new lower temporary bound found in R5. The process then flows to step 1260 where the new chip enable failed device address is written to the gate array chip enable counter. The process then flows to step 1262 where the microcontroller issues a "read compare increment" command to the gate array. The process then flows to step 1260 to check whether all the devices compare. If they do not compare the process returns to step 1332 which is found in Figure 13C. If all devices check out OK the process flows to process step 1334 which can be found in Figure 13F.

The process continues in Figure 13E at process step 1334 where the device number is stored in the erasure queue in process step 1268. The process then flows to process step 1270 where the erase queue pointer is incremented in Rl. The process then flows to step 1272 where the device number is stored in the erase queue again for the new upper bounds. The process then flows to step 1274 to set the ERAQPTR pointer to equal the ERAQ pointer plus two which points to the next lower or upper bound pair in the erasure queue. The process then flows to step 1276 where the present chip enable address is checked for equivalence to the upper device number address. If it is the process flows to step D which is found in 13F. If it is not the process flows to step 1278 where the new lower bounds is set to the present device failure address plus one. The process then flows to 1280 to increment the erase queue pointer Rl. The process then flows step 1336 which is found in Figure 13D.

Now referring to Figure 13F which shows the method of the invention used to erase devices that need to be erased. The process flows to process step 1282 where the pulse count is decremented for each failed device. The process then flows to process step 1284 where the pulse counter is checked to be zero. If it is zero the process flows to step 1338 which is found on Figure 13G. If the pulse counter is not zero the pointer is loaded with the initial address 1286. The process then flows to process step 1288 where the first chip enable address is fetched from the erase queue. The process then flows to write the value in the erase queue to the gate array chip enable counter in process step 1290. The process then flows to step 1292 where the second device address is received from the erase queue. The process then flows to process step 1294 where the address from the erasure is written to the upper bounds counter. The process then flows to step 1296 where the microcontroller issues a "write command/data" command to the gate array to start erasure. The process then flows to step 1298 where the erase queue pointer is incremented to point to the next address pair and the queue to be erased. The process then flows to step 1302 where a test is made for end of queue. If there is no end of queue the process returns to step 1288 to erase the next element in the queue. If the queue is empty the process flows to process step 1304 to wait for a ten millisecond time out to make sure that all the last device was erased. The process then flows to process step 1306A where a "write data only" command is sent to the gate array to put the devices in the "erase verify" state. The microcontroller then puts the devices in an "erase verify" state following the process step outlined in process group 1305. The process then flows to Figure 13G.

Referring now to Figure 13G where the process loads a "lower bounds device" number to the R4 register in step 1308 to test whether all devices pass. This process block test for failed devices in the queue. The process then flows to step 1310 to load the "upper device" number to the upper bounds register in the gate array. The process then flows to step 1312 to issue a "read compare increment" command to the gate array. The process then flows to step 1314 where the "read compare increment" command is checked for failure. If the command has failed the process flows to process flow step 1328 which is found in Figure 13C. If the "read compare increment" command has not failed the process flows to step 1316 to check whether or not all locations in the flash memory have been checked. If they have not the process flows to step 1326 which is found in the inner loop found in process step 1236, in Figure 13B. If it is the last location to test the process flows to process step 1318 where the carry flag is cleared and the process flows to the caller in Figure 16. Continuing now with the process step 1338 which sets the carry flag on 1322 and exits to the caller also in Figure 16. The process step 1338 is called from process step 1284 found in Figure 13F.

Now referring to Figure 14 which shows a register block diagram of the lower and upper bounds register in the erase queue. When there are one or more devices that fail within the erasure algorithm pairs of chip enable device numbers are stored in a queue. These numbers represent the starting device number at which an erasure failure has occurred and the next device number in which it failed. This is the case in Figure 14 where these are four devices and devices 1, 3 and 4 have failed. Device 2 did not fail erasure in this case so device 2 should not show up within the erasure queue. The queue is set up such that we have lower and upper bound pairs and since device 2 did not fail, the first lower bound, upper bound pair will both represent device one as shown in step 1350 and step 1352. Since both devices 3 and 4 failed the logic state machine is set to erase and erase verify two devices within one cycle. Step 1354 represents the lower bounds number that will be loaded into the chip enable counter 230 in this case and step 1356 represents the upper bounds number that would be loaded into the upper bounds register for the logic state machine.

The logic state machine is restarted after the device erase failure is determined. The erasure queue is then loaded. The logic state machine will erase only device 1, then device pointers will be incremented and chip enable numbers and upper bound registers will be reloaded with devices 3 and 4 as lower and upper bounds and the logic state machine will be restarted. Now referring to Figure 15 which shows the logic state machine being used as a operational command apparatus for the solid state disk emulator apparatus of the invention. The command decode logic 1401 decodes commands that have been latched by the command register 1432. The command register latches commands from the microcontroller data bus 104A. The decoded commands are send on line 1414 to output decode logic 1406 and to control logic block 1402. Control logic block 1402 controls the starting and stopping of the memory cycle counter 1404.

The control logic block 1402 receives control from four sources. The device comparison logic line 1408 determines whether the present device number is equal to the last device to be written or read from. The second input status line 243 detects whether or not their is a read data memory comparison failure. The start/stop line 1410 starts command operations synchronized to the system clock 106. Input control line 1412 is a single cycle control line that when active causes the memory cycle counter 1404 to execute one memory cycle.

The memory cycle counter 1404 generates memory states that are used by the output decode logic 1406 to generate 4 control lines. The output decode logic decodes the memory states and the command types. The memory states include five different states. The four command types include: program from one to N devices by writing a single byte data value to each device with a selection of memory address autoincrement or no autoincrement at the end of the command operation cycle; program from one to N devices by writing two byte data values to each device with a selection of either memory address autoincrement or no autoincrement at the end of the command operation cycle; read data from one to N devices at a fixed memory address, compare the read data with the fixed data value and optionally autoincrement or no increment the linear portion of the memory address at the end of the command operation cycle; read data from the device and compare the data with the fixed value, if the compared value is different from the data value read, then stop at the failure address, otherwise complete the comparison for the device or the device page. The output decode logic 1406 then generates a chip enable signal 1416 which controls the chip enables on the memory devices within the memory array 60. The output decode logic 1406 also generates a output enable signal 1418 which controls the memory devices during read operations within the memory array 60. The output decode logic 1406 also generates a write strobe 1420 which controls the memory devices during write operations within the memory array 60. The output decode logic 1406 also generates a counter increment control signal 1422 which enables the incrementing of the address counter 232 and chip enable counter 230, both shown on Figure 4C.

The invention has been described herein in considerable detail in order to comply with the Patent Statutes and to provide those skilled in the art with the information needed to apply the novel principles and to construct and use such specialized components as are required. However, it is to be understood that the invention can be carried out by specifically different equipment and devices, and that various modifications, both as to the equipment details and operating procedures, can be accomplished without departing from the scope of the invention itself. What is claimed is:

Claims

1. A data storage apparatus for use in a system providing data storage command inputs, the data storage apparatus comprising: (a) logic means for performing data storage functions in response to the command inputs having a memory address output, a memory data bus, and a command input;

(b) means for memory address decoding connected to the address output having a decoded address output;

(c) buffer means for buffering data connected to the memory data bus having a buffered data bus; (d) memory means connected to the decoded address output and the buffered data bus; and

(e) control means for generating the data storage commands in response to the command inputs, wherein the control means is connected to the logic means and wherein the control means generates a command condition code indicating the status of the data storage commands.

2. The data storage apparatus of claim 1 wherein the memory means further comprises a non volatile memory.

3. The data storage apparatus of claim 1 wherein the memory means further comprises a solid state memory.

4. The data storage apparatus of claim 1 wherein the memory means further comprises a non volatile solid state memory.

5. The data storage apparatus of claim 1 wherein the memory means further comprises a plurality of flash memory devices.

6. The data storage apparatus of claim 1 wherein the logic means further comprises: (a) command register means disposed to receive the command inputs having a registered command output connected to the control means;

(b) decoding means for determining the function of the data storage command connected to receive data storage commands from the control means having an decoded data storage command output;

(c) device register means for storing device control commands in response to the decode data storage command output, wherein the register means has a device command output and a device data output; and (d) status register means for storing the condition code connected to the control means having a storage status output.

7. The data storage apparatus of claim 6 wherein the control means also generates address mapping data and wherein the logic means further comprises means for address mapping connected to receive address mapping data from the control means wherein the means for address mapping is connected to the memory address output.

8. The data storage apparatus of claim 7 wherein the memory means further comprises a plurality of memory devices and wherein the means for address mapping further comprises: (a) chip enable counting means for determining which device of the plurality of memory device means is being written to or read from;

(b) interleave counting means for determining which device of the plurality of memory devices is being written to or read from; and

(c) linear device address counting means for determining a device address for the plurality of memory device means.

9. The data storage apparatus of claim 1 wherein the logic means further comprises a direct memory access control means.

10. The data storage apparatus of claim 9 wherein the logic means further comprises a DMA request output and an external bus and wherein the direct memory access control means further comprises:

(a) means for input output decoding connected to the DMA request output having a DMA acknowledge output; and

(b) ping-pong data storage buffer means connected to receive data from the external bus and send the data to the memory data bus.

11. The data storage apparatus of claim 1 wherein the logic means further comprises an interrupt control means to signal operation completion of the data storage functions.

12. The data storage apparatus of claim 11 wherein the logic means generates a DMA interrupt and the control means generates a status interrupt, and wherein the interrupt control means further comprises: (a) interrupt storage means for capturing any number of interrupt sources from either the logic means or control means having an interrupt source output; and

(b) interrupt selection means for selecting the source of the interrupt connected to the interrupt source output having a masked interrupt source output.

13. The data storage apparatus of claim 1 wherein the logic means further comprises a means for memory data comparison.

14. The data storage apparatus of claim 13 wherein the means for memory data comparison comprises:

(a) tri-state buffer means connected to buffer the memory data bus to a tri- state memory data bus; and

(b) logical compare means having a first compare input connected to the memory data bus and a second compare input connected to the tri-state memory data bus having data comparison output.

15. The data storage apparatus of claim 1 wherein the logic means further comprises data selection multiplexer means having a first input connected to the control means data bus, a second input connected to the ping-pong buffer output, a third input connected to the registered command data output and wherein the multiplexer drives the memory data bus in response to control from the control means or the external system.

16. The data storage apparatus of claim 1 wherein the memory data bus further comprises a plurality of memory data bits and the external bus further comprises a plurality of external bits wherein there is a one to one correspondence between the memory data bit and the external bits and the logic means further comprises a transition logic means for determining whether any one bit of plurality of memory data bits is zero and the corresponding external bit is one.

17. The data storage apparatus of claim 1 wherein the logic means further comprises a buffer type selection means for selecting between double buffer mode and single buffer mode.

18. An operational command apparatus for a solid state disk emulator having a system controller that issues data storage commands including read data, write data and erase data commands, to one or more than one memory devices, linear address counters and chip enable counters, the operation command apparatus comprising:

(a) means for command decoding for decoding data storage commands having a operation data storage command output;

(b) means for controlling a counter having a first input status line, a second input status line, a start/stop line and an input control line wherein the means for controlling generates a counter control signal in response to the first input status line, a second input status line, a start/stop line and an input control line;

(c) means for counting connected to the operation data storage command output and counter control line wherein the means for counting generates a memory state control line output; and

(d) means for memory state and storage command decoding connected to the memory state control line and operational data storage command output wherein the means for memory state and storage command decoding generates a chip enable control signal, output enable control signal, write strobe signal and a counter increment signal, wherein the chip enable enables the memory devices, the output enable enables the reading of the memory devices, the write strobe signal enable the writing of the memory devices and the counter increment signal causes the incrementing of the linear address counters or chip enable counters.

19. The operational command apparatus for a solid state disk emulator of claim 18 wherein the operational data storage commands operate within a command cycle and the commands further comprise commands that: (a) program from one to N devices by writing a single byte data value to each device with a selection of memory address autoincrement or no autoincrement at the end of the command operation cycle;

(b) program from one to N devices by writing two byte data values to each device with a selection of either memory address autoincrement or no autoincrement at the end of the command operation cycle;

(c) read data from one to N devices at a fixed memory address, compare the read data with the fixed data value and optionally autoincrement or no increment the linear portion of the memory address at the end of the command operation cycle; and

(d) read data from the device and compare the data with the fixed value, if the compared value is different from the data value read, then stop at the failure address, otherwise complete the comparison for the device or the device page.

20. A method for writing data to a plurality of memory devices having a command register architecture comprising the steps of:

(a) writing a program command to the first device;

(b) writing data to the first device;

(c) writing a program command to the next device;

(d) writing data to the next device; (e) repeating steps (c) and (d) until all of the plurality of devices have been written to; (f) writing standby command to the first device; (g) repeating step (f) until all of the plurality of devices have been written to; (h) reading data from all the devices device;

(i) comparing the written data to the read data in all devices and determining if they are different and if they are different repeating steps (a) through

(e) a predetermined number of times or until the they are the same; and (j) determining that a device has failed if the data read is never the same as the data written.

21. The method of claim 20 wherein the data written is a single byte.

22. A method for writing data to a plurality of memory devices having a command register architecture controlled by the apparatus of claim 1 comprising the steps of:

(a) writing a program command to the devices;

(b) writing data to the devices; (c) writing standby command to the devices;

(d) reading data from the devices; and

(e) comparing the written data to the read data and determining if they are different and if they are different repeating steps (a) through (e) a predetermined number of times or until they are the same, and

(f) determining that a device has failed if the data read is never the same as the data written.

23. The method of claim 23 wherein the data written is a single byte.

24. A method of determining the address of the first byte in a memory that is not all ones comprising the steps of:

(a) setting the current memory address to be the highest memory address;

(b) accessing the data in the current memory address location;

(c) checking whether or not each data bit is equal to one; (d) decrementing the current memory address if all data bits are equal to one and repeating steps (b) through (d) until all memory locations have been checked or a non one value is found; (e) determining the first non free memory location to be the current memory location if all memory locations have not been checked; and (f) determining that all memory locations are free if all memory locations have been checked.

25. A method for writing a plurality of memory devices having a command register architecture controlled by the apparatus of claim 1 to all zeros comprising the steps of:

(a) storing the value 0 to the current address;

(b) writing a program command to the devices simultaneously; (c) writing the value 0 to all devices simultaneously at the current address; (d) writing standby command to the devices simultaneously; (e) reading data from the devices simultaneously at the current address; and

(f) comparing the read data to the value 0 and determining if they are different and if they are different repeating steps (a) through (e) a predetermined number of times or until they are the same; (g) determining that a device has failed if the data read is never the same as the data written; (h) incrementing the current address; and (i) repeating steps (b) through (h) until all addresses are zero.

26. A method for erasing a plurality of memory devices having a command register architecture controlled by the apparatus of claim 1 comprising the steps of: (a) storing the value 0 to the current address;

(b) writing an erasure command to the devices simultaneously;

(c) writing an erasure standby command to the devices simultaneously;

(d) reading data from the devices simultaneously at the current address;

(e) checking each device to determine if all bits are equal to one and if they are not repeating step (d) a predetermined number of times;

(f) checking each device to determine if all bits are equal to the value one and repeating steps (b) through (d) for these devices; (g) repeating step (f) a predetermined number of times or until all devices have been programmed to ones at the current address; (h) determining that a device has failed if the any device is not programmed to all ones; (i) incrementing the current address; and

(j) repeating steps (b) through (i) all until address locations have been erased in all devices.

27. In a system with a logic supply voltage a method of determining the state of a programming voltage supply line for a programmable memory comprising the steps of:

(a) waiting for a programming or erasure operation to complete; (b) waiting a first predetermined amount of time to monitor other programming or erase operation requests if there are any returning to step (a) ; (c) disabling memory operations; (d) deactivating the programming voltage supply line; and

(e) waiting a second predetermined amount of time for the programming voltage supply line to reach the logic supply voltage; and

(f) reenabling memory operations.

28. In a system with a logic supply voltage a method of determining the state of a programming voltage supply line for a programmable memory comprising the steps of: (a) checking if the programming voltage supply line is in the active state; (b) if the programming voltage supply line is in the active state then return a Vpp active status; (c) if the programming voltage supply line is in the Vpp delay state then return a Vpp Off delay status; and (d) otherwise return Vpp equals line voltage status.

29. The apparatus of claim 1 wherein the microcontroller further comprises a voltage control means that controls the voltage to the plurality of memory means.

30. A data storage apparatus comprising: (a) means for memory address decoding connected to the address output having a decoded address output;

(b) buffer means for buffering data connected to a memory data bus wherein the buffer means also has a buffered data bus;

(c) memory means connected to the decoded address output and the buffered data bus; and (d) control means for reading and writing data and commands to the memory means, wherein the control means generates a command condition code indicating the status of the data storage commands.

31. The data storage apparatus of claim 30 wherein the memory means further comprises a non volatile memory.

32. The data storage apparatus of claim 30 wherein the memory means further comprises a solid state memory.

33. The data storage apparatus of claim 30 wherein the memory means further comprises a non volatile solid state memory.

34. The data storage apparatus of claim 30 wherein the memory means further comprises a plurality of flash memory devices.

35. The data storage apparatus of claim 30 wherein the logic means further comprises:

(a) command register means disposed to receive the command inputs having a registered command output connected to the control means;

(c) device register means for storing device control commands in response to the decode data storage command output, wherein the register means has a device command output and a device data output; and

(d) status register means for storing the condition code connected to the control means having a storage status output.

36. The data storage apparatus of claim 35 wherein the control means also generates address mapping data and wherein the logic means further comprises means for address mapping connected to receive address mapping data from the control means wherein the means for address mapping is connected to the memory address output.

37. The data storage apparatus of claim 36 wherein the memory means further comprises a plurality of memory. devices and wherein the means for address mapping further comprises:

(a) chip enable counting means for determining which device of the plurality of memory device means is being written to or read from;

38. The data storage apparatus of claim 30 wherein the logic means further comprises a direct memory access control means.

39. The data storage apparatus of claim 38 wherein the logic means further comprises a DMA request output and an external bus and wherein the direct memory access control means further comprises:

(a) means for input output decoding connected to the DMA request output having a DMA acknowledge output; and (b) ping-pong data storage buffer means connected to receive data from the external bus and send the data to the memory data bus.

40. A data storage apparatus for use in a system providing data storage command inputs, the data storage apparatus comprising:

(a) logic means for performing data storage functions in response to the command inputs having a memory address output, a memory data bus, and a command input;

(c) buffer means for buffering data connected to the memory data bus having a buffered data bus;

(d) memory means connected to the decoded address output and the buffered data bus having a chip enable control means, and output enable control means, and a write strobe signal;

(e) control means for generating the data storage commands in response to the command inputs, wherein the control means is connected to the logic means and wherein the control means generates a command condition code indicating the status of the data storage commands;

(f) means for command decoding for decoding the data storage commands having a operation data storage command output;

(g) means for controlling a counter connected to the memory address output, wherein the means for controlling a counter generates a counter control signal in response to the memory address output;

(h) means for counting connected to the operation data storage command output and counter control line wherein the means for counting generates a memory state control line output; and

(i) means for memory state and storage command decoding connected to the memory state control line and operational data storage command output wherein the means for memory state and storage command decoding generates a chip enable control signal, output enable control signal, write strobe signal and a counter increment signal, wherein the chip enable enables the memory devices, the output enable enables the reading of the memory devices, the write strobe signal enable the writing of the memory devices and the counter increment signal causes the incrementing of the memory address output.

41. The data storage apparatus of claim 40 wherein the memory means further comprises a plurality of memory devices and wherein the means for address mapping further comprises:

(a) chip enable counting means for determining which device of the plurality of memory device means is being written to or read from; (b) interleave counting means for determining which device of the plurality of memory devices is being written to or read from; and (c) linear device address counting means for determining a device address for the plurality of memory device means.

42. The data storage apparatus of claim 40 wherein the logic means further comprises a direct memory access control means.

43. The data storage apparatus of claim 42 wherein the logic means further comprises a DMA request output and an external bus and wherein the direct memory access control means further comprises:

(b) ping-pong data storage buffer' means connected to receive data from the external bus and send the data to the memory data bus.

44. The data storage apparatus of claim 1 wherein the logic means further comprises a logic storage command input and an external bus and wherein the data storage appratus further comprises a ping-pong data storage buffer means connected to receive data from the external bus and send the data to the memory data bus in response to the logic storage command input.

45. The data storage apparatus of claim 40 wherein the logic means further comprises a logic storage command input and an external bus and wherein the data storage appratus further comprises a ping-pong data storage buffer means connected to receive data from the external bus and send the data to the memory data bus in response to the logic storage command input.