WO1993020505A3 - Superscalar risc instruction scheduling - Google Patents

Superscalar risc instruction scheduling Download PDF

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Publication number
WO1993020505A3
WO1993020505A3 PCT/JP1993/000375 JP9300375W WO9320505A3 WO 1993020505 A3 WO1993020505 A3 WO 1993020505A3 JP 9300375 W JP9300375 W JP 9300375W WO 9320505 A3 WO9320505 A3 WO 9320505A3
Authority
WO
WIPO (PCT)
Prior art keywords
tags
register file
data
register
operands
Prior art date
Application number
PCT/JP1993/000375
Other languages
French (fr)
Other versions
WO1993020505A2 (en
Inventor
Sanjiv Garg
Kevin Ray Iadonato
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25333867&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1993020505(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP51729393A priority Critical patent/JP3730252B2/en
Priority to EP93906834A priority patent/EP0636256B1/en
Priority to DE69311330T priority patent/DE69311330T2/en
Publication of WO1993020505A2 publication Critical patent/WO1993020505A2/en
Publication of WO1993020505A3 publication Critical patent/WO1993020505A3/en
Priority to KR1019940703382A priority patent/KR950701101A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags

Abstract

A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependence check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
PCT/JP1993/000375 1992-03-31 1993-03-26 Superscalar risc instruction scheduling WO1993020505A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP51729393A JP3730252B2 (en) 1992-03-31 1993-03-26 Register name changing method and name changing system
EP93906834A EP0636256B1 (en) 1992-03-31 1993-03-26 Superscalar risc processor instruction scheduling
DE69311330T DE69311330T2 (en) 1992-03-31 1993-03-26 COMMAND SEQUENCE PLANNING FROM A RISC SUPER SCALAR PROCESSOR
KR1019940703382A KR950701101A (en) 1992-03-31 1994-09-28 Superscalar RCS command scheduling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US86071992A 1992-03-31 1992-03-31
US07/860,719 1992-03-31

Publications (2)

Publication Number Publication Date
WO1993020505A2 WO1993020505A2 (en) 1993-10-14
WO1993020505A3 true WO1993020505A3 (en) 1993-11-25

Family

ID=25333867

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1993/000375 WO1993020505A2 (en) 1992-03-31 1993-03-26 Superscalar risc instruction scheduling

Country Status (6)

Country Link
US (7) US5497499A (en)
EP (1) EP0636256B1 (en)
JP (7) JP3730252B2 (en)
KR (3) KR950701101A (en)
DE (1) DE69311330T2 (en)
WO (1) WO1993020505A2 (en)

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