WO1993022770A1 - Method and apparatus for storage of digital information - Google Patents

Method and apparatus for storage of digital information Download PDF

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Publication number
WO1993022770A1
WO1993022770A1 PCT/US1993/003631 US9303631W WO9322770A1 WO 1993022770 A1 WO1993022770 A1 WO 1993022770A1 US 9303631 W US9303631 W US 9303631W WO 9322770 A1 WO9322770 A1 WO 9322770A1
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WO
WIPO (PCT)
Prior art keywords
analog
eeprom
voltage level
digital
converter
Prior art date
Application number
PCT/US1993/003631
Other languages
French (fr)
Inventor
Wayne W. Ballantyne
George Revtai, Jr.
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1993022770A1 publication Critical patent/WO1993022770A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 

Definitions

  • This invention relates generally to memory storage devices, and more specifically to electrically erasable programmable read-only memories (EEPROMs).
  • EEPROMs electrically erasable programmable read-only memories
  • EEPROMs In radio communication devices it is common to use EEPROMs in order to store digital radio information such as channel data, radio user ID'S, radio tuning data, scan list information, etc.
  • EEPROMs typically store either a high or low voltage level in each of its memory cells, with the voltage level found in each cell determining if the memory cell contains .a "1" or a "0" as information.
  • Present day EEPROMs can contain thousands of such memory locations.
  • a memory system comprises a digital-to-analog converter means for encoding a multi-bit digital information signal into an analog voltage level.
  • the memory system also includes an electrically-erasable and programmable read-only-memory (EEPROM) coupled to the digital-to-analog converter for storing the analog voltage level and an analog-to-digital converter means coupled to the EEPROM for decoding the analog voltage level stored in the EEPROM back into the multi-bit digital information signal when the analog voltage level is retrieved from the EEPROM.
  • EEPROM electrically-erasable and programmable read-only-memory
  • FIG. 1 is a block diagram of a radio in accordance with the present invention.
  • FIG. 2 is a flow chart showing the write and read steps in accordance with the present invention.
  • FIG. 3 is a block diagram of an EEPROM in accordance with the present invention.
  • Radio 100 includes a control means such as controller 114 which can be a conventional microprocessor or microcontroller such as a Motorola, Inc. 68HC11 microcontroller. Controller 114 controls the operation of a conventional transmitter 116 and a conventional receiver 118. Transmitter 116 and receiver 118 are selectively coupled to an antenna 122 via antenna switch 120, which could also be a duplexer in a duplex radio.
  • controller 114 can be a conventional microprocessor or microcontroller such as a Motorola, Inc. 68HC11 microcontroller.
  • Controller 114 controls the operation of a conventional transmitter 116 and a conventional receiver 118.
  • Transmitter 116 and receiver 118 are selectively coupled to an antenna 122 via antenna switch 120, which could also be a duplexer in a duplex radio.
  • Controller 114 is coupled to an analog-to-digital converter means such as A/D converter 108, an digital-to-analog converter means such as D/A converter 106 and a EEPROM 102 via a data/address/control line bus 124 which form the memory system of the present invention.
  • the D/A converter 108 and A/D converter 106 are 4-bit devices.
  • EEPROM 102 provides nonvolatile storage of radio information, such as radio ID's, channel information, etc.
  • the present invention in effect allows for the storage of four times (this is assuming the use of 4 bit D/A and A/D converters and 4 bit digital words) the information typically stored in a digital EEPROM.
  • A/D and D/A converters should have resolutions much greater than that of the voltages stored in the analog EEPROM array 102.
  • a transfer characteristic like that of an 8-bit converter integrated on the Motorola, Inc. 68HC11 would be more than sufficient to prevent bit errors in the converted information.
  • the D/A converter could be a converter such as a MaximTM MAX7224 CMOS IC, which has an accuracy of +/- 1/2 LSB.
  • low-pass filters 104 and 110 are used on the output of the D/A converter 106 (LPF 104) and the input to the A/D converter 108 (LPF 110), as shown in FIG. 1.
  • the bandwidth of these filters would be set as low as possible without degrading data throughput (e.g., delays due to settling times of the output voltages of these filters).
  • a dedicated precision voltage reference 112 is used for the A D and D/A converters, rather than the standard Vdd voltage lines used for the digital IC's in radio 100 which tend to be noisier. The additional filtering provided by precision voltage reference 112 reduces the chances of any radio system noise from affecting the analog-to-digital and digital-to- analog conversions.
  • controller 114 sends a digital word containing 4-bits of information to D/A converter 106.
  • D/A converter 106 then converts the 4-bit digital word into a discrete analog voltage level representing the 4-bit digital word. This voltage level is sent through a low-pass filter 104 to filter out any quantization harmonics.
  • the voltage level signal 128 is then stored into a cell location in EEPROM 102.
  • the reverse process is utilized when the information is required to be read from EEPROM 102.
  • the controller addresses the EEPROM 102 requesting the information in one of the EEPROMs cell locations.
  • the output voltage 126 is then sent through another low-pass filter 110 for filtering.
  • the filtered voltage level is then converted back into a 4- bit analog word using A/D (analog-to-digital) converter 108.
  • the 4 bit word is then sent via bus 124 to controller 114 for processing.
  • FIG. 2 there is shown atypical method for storing and reading information from EEPROM 102.
  • the D/A converter 106 is programmed by addressing the device and sending a 4-bit digital word to it as shown in step 202. Also, as part of step 202, D/A 106 encodes the digital word into an analog signal (a discrete voltage level representing the digital word).
  • EEPROM 102 is selected by controller 104 and the analog signal is stored in a selected cell location.
  • the EEPROM read cycle begins by addressing EEPROM 102 and reading the voltage in the desired cell location.
  • step 208 the analog signal (voltage level) is converted back into a digital word by A/D 108 decoding the analog information voltage level and sending the digital word output to controller 114 for processing.
  • FIG. 3 a block diagram of a 64 K x 1 analog EEPROM 300 is shown. In many respects it is similar to a conventional digital EEPROM. The same conventional control lines CE bar, WE bar and OE bar 304 are utilized. The RDY/BUSY status line can be optionally implemented to provide feedback to the main CPU (e.g., controller 114 in FIG. 1) as to when a write cycle is completed.
  • analog EEPROM 300 and conventional digital EEPROMs
  • the data input and output lines 308 and 310 are single data lines, instead of 8-bit bi-directional signal lines.
  • a separate "data in” 308 and “data out” 310 lines are used. This eliminates the need for external analog gating as would be required if a bi-directional data line was used.
  • the I/O buffer block (shown in Fig. 3) comprises analog buffer amplifiers with low DC voltage offsets and precise voltage gain stages rather than digital buffer circuits as found in conventional EEPROMs.
  • the present invention provides for increased storage of information, by converting the digital information to be stored into analog voltages and then reconverting the information when the information is required.
  • each 4-bit digital word is stored in only 1 memory cell location of the EEPROM as compared to the use of four memory cell locations using conventional digital storage techniques.
  • Controller 114 uses each cell of EEPROM 102 to store a 4- bit voltage ranging from 0 to Vdd volts (Vdd is typically 5.0 or 3.3 volts).
  • Vdd is typically 5.0 or 3.3 volts.
  • the voltage being generated by the 4-bit D/A converter 106 which is programmed by controller 114 via address/data bus 124 (could also utilize a serial bus architecture).
  • address/data bus 124 could also utilize a serial bus architecture.
  • analog EEPROM 102 is addressed and the voltage is written into the selected cell location using conventional write bus timing signals commonly used for writing to conventional digital EEPROMs.
  • the present invention provides for a significant improvement in memory storage efficiency over prior EEPROM techniques. The storage efficiency achieved translates into a large cost savings when designing systems such as two-way radios which require significant EEPROM storage. ' What is claimed is:

Abstract

A method and apparatus for storage of digital information includes an EEPROM (102), a D/A converter (106) and an A/D converter (108). Low-pass filters (104 and 110) are included in order to minimize noise during the conversion process. By converting the digital information to be stored into EEPROM (102) into analog voltages representative of the multi-bit digital information and then reconverting the information when required, an increase in storage capability is realized. This increase in storage capability provides for less expensive storage as compared to use of conventional digital EEPROMs.

Description

METHOD AND APPARATUS FOR STORAGE OF DIGITAL INFORMATION
Technical Field
This invention relates generally to memory storage devices, and more specifically to electrically erasable programmable read-only memories (EEPROMs).
Background
In radio communication devices it is common to use EEPROMs in order to store digital radio information such as channel data, radio user ID'S, radio tuning data, scan list information, etc. EEPROMs typically store either a high or low voltage level in each of its memory cells, with the voltage level found in each cell determining if the memory cell contains .a "1" or a "0" as information. Present day EEPROMs can contain thousands of such memory locations.
In recent years it has been determined that conventional EEPROMs can also be used as analog memory devices. In other words, instead of just being able to store two discrete voltage levels at each cell location, EEPROMs have been found to be able to store a range of analog voltage levels. For example, in an article by Tong-Chern Ong, Ping K. Ko and Chenming Hu, entitled "The EEPROM as an Analog Device, IEEE Transactions on Electron Devices, Vol. 36, No. 9, September 1989, the authors disclosed that nonvolatile storage, electrical programming, and erasing of analog signals is possible using conventional EEPROMs. in the last couple of years more development into so called analog EEPROMs has occurred, with the advent of voice message storage systems. These voice storage devices can store analog information in nonvolatile storage arrays which are typically based on CMOS EEPROM technology. These analog EEPROMs are substantially similar to the conventional EEPROMs used to store digital information.
Given the great amount of information that is stored in EEPROMs in communication devices such as two-way radios, the cost of using EEPROM technology per bit of information stored is a large portion of the overall memory cost in a radio. A need thus exists for better ways of reducing the size and cost of using EEPROMs.
Summary of the Invention
Briefly, according to the invention a memory system, comprises a digital-to-analog converter means for encoding a multi-bit digital information signal into an analog voltage level. The memory system also includes an electrically-erasable and programmable read-only-memory (EEPROM) coupled to the digital-to-analog converter for storing the analog voltage level and an analog-to-digital converter means coupled to the EEPROM for decoding the analog voltage level stored in the EEPROM back into the multi-bit digital information signal when the analog voltage level is retrieved from the EEPROM.
Brief Description of the Drawings
FIG. 1 is a block diagram of a radio in accordance with the present invention. FIG. 2 is a flow chart showing the write and read steps in accordance with the present invention.
FIG. 3 is a block diagram of an EEPROM in accordance with the present invention.
Detailed Description of the Preferred Embodiment
Referring now to the drawings and specifically to FIG. 1 there is shown a block diagram of a radio 100 in accordance with the present invention. Radio 100 includes a control means such as controller 114 which can be a conventional microprocessor or microcontroller such as a Motorola, Inc. 68HC11 microcontroller. Controller 114 controls the operation of a conventional transmitter 116 and a conventional receiver 118. Transmitter 116 and receiver 118 are selectively coupled to an antenna 122 via antenna switch 120, which could also be a duplexer in a duplex radio.
Controller 114 is coupled to an analog-to-digital converter means such as A/D converter 108, an digital-to-analog converter means such as D/A converter 106 and a EEPROM 102 via a data/address/control line bus 124 which form the memory system of the present invention. In the preferred embodiment, the D/A converter 108 and A/D converter 106 are 4-bit devices. EEPROM 102 provides nonvolatile storage of radio information, such as radio ID's, channel information, etc.
The present invention in effect allows for the storage of four times (this is assuming the use of 4 bit D/A and A/D converters and 4 bit digital words) the information typically stored in a digital EEPROM. To avoid the possibility of quantization errors during the D/A and A/D conversions, A/D and D/A converters should have resolutions much greater than that of the voltages stored in the analog EEPROM array 102. For example, a transfer characteristic like that of an 8-bit converter integrated on the Motorola, Inc. 68HC11 would be more than sufficient to prevent bit errors in the converted information. Since the accuracy of such a device is typically +/- 1 least-significant-bit (LSB) or less, there is no chance that the four upper MSB's (most- significant-bits) would be in error unless a large amount of noise was present in the bus lines. Likewise, the D/A converter could be a converter such as a Maxim™ MAX7224 CMOS IC, which has an accuracy of +/- 1/2 LSB.
To minimize the effects of noise, low-pass filters 104 and 110 are used on the output of the D/A converter 106 (LPF 104) and the input to the A/D converter 108 (LPF 110), as shown in FIG. 1. The bandwidth of these filters would be set as low as possible without degrading data throughput (e.g., delays due to settling times of the output voltages of these filters). To provide further noise immunity, a dedicated precision voltage reference 112 is used for the A D and D/A converters, rather than the standard Vdd voltage lines used for the digital IC's in radio 100 which tend to be noisier. The additional filtering provided by precision voltage reference 112 reduces the chances of any radio system noise from affecting the analog-to-digital and digital-to- analog conversions.
In operation controller 114 sends a digital word containing 4-bits of information to D/A converter 106. D/A converter 106 then converts the 4-bit digital word into a discrete analog voltage level representing the 4-bit digital word. This voltage level is sent through a low-pass filter 104 to filter out any quantization harmonics. The voltage level signal 128 is then stored into a cell location in EEPROM 102. The reverse process is utilized when the information is required to be read from EEPROM 102. First, the controller addresses the EEPROM 102 requesting the information in one of the EEPROMs cell locations. The output voltage 126 is then sent through another low-pass filter 110 for filtering. The filtered voltage level is then converted back into a 4- bit analog word using A/D (analog-to-digital) converter 108. The 4 bit word is then sent via bus 124 to controller 114 for processing.
In FIG. 2, there is shown atypical method for storing and reading information from EEPROM 102. As mentioned before, the D/A converter 106 is programmed by addressing the device and sending a 4-bit digital word to it as shown in step 202. Also, as part of step 202, D/A 106 encodes the digital word into an analog signal (a discrete voltage level representing the digital word). In step 204, EEPROM 102 is selected by controller 104 and the analog signal is stored in a selected cell location. In step 206, the EEPROM read cycle begins by addressing EEPROM 102 and reading the voltage in the desired cell location. In step 208, the analog signal (voltage level) is converted back into a digital word by A/D 108 decoding the analog information voltage level and sending the digital word output to controller 114 for processing. In FIG. 3, a block diagram of a 64 K x 1 analog EEPROM 300 is shown. In many respects it is similar to a conventional digital EEPROM. The same conventional control lines CE bar, WE bar and OE bar 304 are utilized. The RDY/BUSY status line can be optionally implemented to provide feedback to the main CPU (e.g., controller 114 in FIG. 1) as to when a write cycle is completed. The main difference between analog EEPROM 300 and conventional digital EEPROMs is that in the analog EEPROM of the present invention the data input and output lines 308 and 310, are single data lines, instead of 8-bit bi-directional signal lines. Instead of using bi-directional lines as in conventional digital EEPROMs, a separate "data in" 308 and "data out" 310 lines are used. This eliminates the need for external analog gating as would be required if a bi-directional data line was used. Another difference is that the I/O buffer block (shown in Fig. 3) comprises analog buffer amplifiers with low DC voltage offsets and precise voltage gain stages rather than digital buffer circuits as found in conventional EEPROMs.
As been shown the present invention provides for increased storage of information, by converting the digital information to be stored into analog voltages and then reconverting the information when the information is required. For example, in the case of the preferred embodiment each 4-bit digital word is stored in only 1 memory cell location of the EEPROM as compared to the use of four memory cell locations using conventional digital storage techniques.
Controller 114 uses each cell of EEPROM 102 to store a 4- bit voltage ranging from 0 to Vdd volts (Vdd is typically 5.0 or 3.3 volts). The voltage being generated by the 4-bit D/A converter 106 which is programmed by controller 114 via address/data bus 124 (could also utilize a serial bus architecture). After the D/A 106 is programmed and sufficient time is allowed for its output voltage to settle, analog EEPROM 102 is addressed and the voltage is written into the selected cell location using conventional write bus timing signals commonly used for writing to conventional digital EEPROMs. Although in the preferred embodiment 4-bit D/A and A/D converters have been used, if the accuracy is available in 8-bit or larger devices, these can be substituted in order to get higher efficiency out of the EEPROM. The main problem with using higher resolution devices is that external noise can create bit errors which can not be tolerated. Also, long-term charge leakage on each memory cell of the EEPROM could make one voltage level change to the next lowest quantization level creating a data storage error. In summary, the present invention provides for a significant improvement in memory storage efficiency over prior EEPROM techniques. The storage efficiency achieved translates into a large cost savings when designing systems such as two-way radios which require significant EEPROM storage. ' What is claimed is:

Claims

Claims
1. A memory system, comprising: a digital-to-analog converter means for encoding a multi-bit digital information signal into an analog voltage level; and an electrically-erasable and programmable read-only- memory (EEPROM) coupled to the digital-to-analog converter for storing the analog voltage level.
2. A memory as defined in claim 1 , further comprising: an analog-to-digital converter means coupled to the
EEPROM for decoding the analog voltage level stored in the EEPROM back into the multi-bit digital information signal when the analog voltage level is retrieved from the EEPROM.
3. The electronic device of claim 1 , wherein the EEPROM includes an input data line for receiving the analog voltage level from the digital-to-analog converter and an output data line for outputting the retrieved analog voltage level to the analog-to- digital converter.
4. The electronic device of claim 2, further comprising: a first low pass filter coupled between the digital-to-analog converter and EEPROM, and a second low pass filter coupled between the analog-to-digital converter and EEPROM.
5. A radio, comprising: a controller; and a memory system comprising: a digital-to-analog converter means for encoding a multi-bit digital information signal into an analog voltage level; an electrically-erasable and programmable read-only- memory (EEPROM) coupled to the digital-to-analog converter for storing the analog voltage level; and an analog-to-digital converter means coupled to the EEPROM for decoding the analog voltage level stored in the EEPROM back into the multi-bit digital information signal when the analog voltage level is retrieved from the EEPROM.
6. A method of storing multi-bit digital information signals, comprising the steps of: sending a multi-bit digital information signal to a digital-to-analog converter; encoding the multi-bit digital information signal using the digital-to-analog converter into an analog voltage level signal representative of the multi-bit digital information signal; and storing the voltage level in a memory unit.
7. A method of storing multi-bit digital information signals as defined in claim 6, wherein the memory unit is an electrically- erasable and programmable read-only-memory (EEPROM).
8. A method of retrieving information signals from a memory device, comprising the steps of: requesting information stored in a certain memory location of the memory device; sending the information in the selected memory location to an analog-to-digital converter; and decoding the analog voltage level signal in the memory location to a multi-bit digital information signal representative of the information in the memory location.
9. A method of retrieving information signals from a memory device as defined in claim 8, wherein the information in the memory location is an analog voltage level.
10. A method of retrieving information signals from a memory device as defined in claim 9, comprising the further step of: sending the analog voltage level through a low-pass filter prior to sending the analog voltage level to the analog-to-digital converter.
PCT/US1993/003631 1992-05-01 1993-04-16 Method and apparatus for storage of digital information WO1993022770A1 (en)

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660334A2 (en) * 1993-12-24 1995-06-28 Blaupunkt-Werke GmbH Circuit arrangement for storage of digital audio signals
EP1001429A1 (en) * 1998-11-11 2000-05-17 Fujitsu Limited Ferroelectric memory device
US7233521B1 (en) * 2005-03-11 2007-06-19 National Semiconductor Corporation Apparatus and method for storing analog information in EEPROM memory
WO2007134316A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Off-die charge pump that supplies multiple flash devices
WO2007134319A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Multi-chip package for a flash memory
WO2007134314A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Analog interface for a flash memory die
WO2007134244A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Use of 8-bit or higher a/d for nand cell value
WO2008082591A2 (en) * 2007-01-02 2008-07-10 Marvell World Trade Ltd. High speed interface for multi-level memory
US7551486B2 (en) 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US7568135B2 (en) 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7613043B2 (en) 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7639531B2 (en) 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US7639542B2 (en) 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7701797B2 (en) 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306300A (en) * 1979-12-31 1981-12-15 International Business Machines Corporation Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits
US4771399A (en) * 1985-12-31 1988-09-13 Motorola, Inc. Method and apparatus for programming memory through battery terminals

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306300A (en) * 1979-12-31 1981-12-15 International Business Machines Corporation Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits
US4771399A (en) * 1985-12-31 1988-09-13 Motorola, Inc. Method and apparatus for programming memory through battery terminals

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE TRANSACTIONS ON ELECTRON DEVICES, Volume 36, No. 9, September 1989, by ONG, KO AND HU, "The EEPROM as an Analog Memory Device", pages 1840 and 1841. *
INFORMATION STORAGE DEVICES, INC., "A Non-Volatile Analog Storage Device Using EEPROM Technology", by BLYTH, KHAN AND SIMKO, 1991 DIGEST OF TECHNICAL PAPERS, Volume 34, 38th ISSCC, 13-15 February 1991, page 191-193 and 315. *
INFORMATION STORAGE DEVICES, INC., Single Chip Voice Message System", March 1991, pages 1-7. *

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0660334A2 (en) * 1993-12-24 1995-06-28 Blaupunkt-Werke GmbH Circuit arrangement for storage of digital audio signals
EP0660334A3 (en) * 1993-12-24 1997-05-02 Blaupunkt Werke Gmbh Circuit arrangement for storage of digital audio signals.
EP1001429A1 (en) * 1998-11-11 2000-05-17 Fujitsu Limited Ferroelectric memory device
US7233521B1 (en) * 2005-03-11 2007-06-19 National Semiconductor Corporation Apparatus and method for storing analog information in EEPROM memory
US7568135B2 (en) 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7639542B2 (en) 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
WO2007134314A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Analog interface for a flash memory die
WO2007134244A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Use of 8-bit or higher a/d for nand cell value
WO2007134314A3 (en) * 2006-05-15 2008-03-13 Apple Inc Analog interface for a flash memory die
WO2007134244A3 (en) * 2006-05-15 2008-03-27 Apple Inc Use of 8-bit or higher a/d for nand cell value
WO2007134316A3 (en) * 2006-05-15 2008-03-27 Apple Inc Off-die charge pump that supplies multiple flash devices
US9245616B2 (en) 2006-05-15 2016-01-26 Apple Inc. Dynamic cell state resolution
WO2007134319A3 (en) * 2006-05-15 2008-07-31 Apple Inc Multi-chip package for a flash memory
US9042170B2 (en) 2006-05-15 2015-05-26 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7511646B2 (en) 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
US7551486B2 (en) 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
WO2007134316A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7613043B2 (en) 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7639531B2 (en) 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
WO2007134319A2 (en) * 2006-05-15 2007-11-22 Apple Inc. Multi-chip package for a flash memory
US7701797B2 (en) 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US7852690B2 (en) 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US7911834B2 (en) 2006-05-15 2011-03-22 Apple Inc. Analog interface for a flash memory die
EP2330592A1 (en) * 2006-05-15 2011-06-08 Apple Inc. 8-bit or more A/D conversion for the determination of a NAND memory cell value
EP2330593A1 (en) * 2006-05-15 2011-06-08 Apple Inc. Analog interface for a flash memory chip
US8964469B2 (en) 2006-05-15 2015-02-24 Apple Inc. Off-die charge pump that supplies multiple flash devices
US8127202B2 (en) 2006-05-15 2012-02-28 Apple Inc. Use of alternative value in cell detection
US8356231B2 (en) 2006-05-15 2013-01-15 Apple Inc. Use of alternative value in cell detection
US8432753B2 (en) 2007-01-02 2013-04-30 Marvell World Trade Ltd. High speed interface for multi-level memory
US8638619B2 (en) 2007-01-02 2014-01-28 Marvell World Trade Ltd. High speed interface for multi-level memory
TWI453755B (en) * 2007-01-02 2014-09-21 Marvell World Trade Ltd High speed interface for multi-level memory
US7978541B2 (en) 2007-01-02 2011-07-12 Marvell World Trade Ltd. High speed interface for multi-level memory
WO2008082591A3 (en) * 2007-01-02 2008-12-04 Marvell World Trade Ltd High speed interface for multi-level memory
WO2008082591A2 (en) * 2007-01-02 2008-07-10 Marvell World Trade Ltd. High speed interface for multi-level memory

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