WO1994027210A1 - Speculative history mechanism in a branch target buffer - Google Patents
Speculative history mechanism in a branch target buffer Download PDFInfo
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- WO1994027210A1 WO1994027210A1 PCT/US1994/003897 US9403897W WO9427210A1 WO 1994027210 A1 WO1994027210 A1 WO 1994027210A1 US 9403897 W US9403897 W US 9403897W WO 9427210 A1 WO9427210 A1 WO 9427210A1
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- Prior art keywords
- branch
- branch prediction
- prediction
- history
- speculative
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- 230000007246 mechanism Effects 0.000 title claims abstract description 77
- 239000000872 buffer Substances 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 claims description 18
- 230000003044 adaptive effect Effects 0.000 claims description 9
- 230000003068 static effect Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 238000004590 computer program Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
Definitions
- This invention relates to branch prediction mechanisms for microprocessors. More specifically to a branch prediction mechanism that stores "speculative history" when a branch prediction is made such that branch history is immediately available for branch instructions within small loops.
- microprocessors generally processed instructions one at a time. Each instruction was processed using four sequential stages: instruction fetch, instruction decode, execute, and result writeback. Within such microprocessors, different dedicated logic blocks performed each different processing stage. Each logic block waits until all the previous logic blocks complete operations before beginning its operation.
- microprocessor designers overlapped the operations of the fetch, decode, execute, and writeback stages such that the microprocessor operated on several instructions simultaneously.
- the fetch, decode, execute, and writeback stages concurrently process different instructions.
- the results of each processing stage are passed to the following processing stage.
- Microprocessors that use the technique of overlapping the fetch, decode, execute, and writeback stages are known as "pipelined" microprocessors.
- an instruction fetch unit at the head of the pipeline must continually provide the pipeline with a stream of instructions.
- conditional branch instructions within an instruction stream prevent an instruction fetch unit at the head of a pipeline from fetching the correct instructions until the condition is resolved. Since the condition will not be resolved until further down the pipeline, the instruction fetch unit cannot fetch the proper instructions.
- the speculative branch history consists of the previous branch history plus recent branch predictions for the branch.
- the branch prediction mechanism of the present invention that maintains a speculative history and an actual history for each branch instruction in a branch target buffer.
- the actual branch history contains the branch history for fully resolved occurrences of the branch instruction.
- the speculative branch history contains the actual history plus the "history" of recent branch predictions for the branch. If the speculative branch history contains any recent predictions, then a speculation bit is set. When the speculation bit is set, this indicates that there is speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a misprediction is made for the branch, the speculation bit is cleared since the speculative history contains inaccurate branch history. BRIEF DESCRIPTION OF THE DRAWINGS
- FIGURE 1 is a block diagram of a deep pipeline for processing instructions.
- FIGURE 2a is a simple pseudo-assembly language program that has a tight loop.
- FIGURE 2b is a trace of the instructions in the program in FIGURE 2a going through the deep instruction pipeline illustrated in FIGURE 1 for a system that fetches one instruction at a time and does not use speculative history.
- FIGURE 3 is a block diagram of a branch target buffer entry for a branch prediction mechanism that uses speculative history.
- FIGURE 4 is a flow diagram that lists the steps required to update the speculative history fields in the branch target buffer when a branch prediction is made.
- FIGURE 5 is a flow diagram that lists the steps required to update the appropriate fields in the branch target buffer when a branch becomes fully resolved by the processor.
- FIGURE 6 is a flow diagram that lists the steps required to make a branch prediction based upon the speculative history fields in the branch target buffer.
- FIGURE 7 is a trace of the instructions in the program in FIGURE 2a going through the deep instruction pipeline illustrated in FIGURE 1 for a system that makes predictions based on speculative history.
- FIGURE 8 is a block diagram of a computer system using the teachings of the present invention.
- the operations are machine operations performed in conjunction with a human operator.
- Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices.
- the present invention relates to method steps for operating a computer and processing electrical or other physical signals to generate other desired physical signals.
- the present invention also relates to apparatus for performing these operations.
- This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer.
- the algorithms presented herein are not inherently related to any particular computer or other apparatus.
- various general purpose machines may be used with programs in accordance with the teachings herein, or it may prove more convenient to construct more specialized apparatus to perform the required method steps.
- the required structure for a variety of these machines will appear from the description given below.
- Machines which may perform the functions of the present invention include those manufactured by the Assignee, Intel Corporation, as well as other manufacturers of computer systems.
- a branch prediction mechanism that makes branch predictions based upon speculative branch history is disclosed.
- specific nomenclature is set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well known circuits and devices are shown in block diagram form in order not to obscure the present invention unnecessarily.
- Figure 1 illustrates a set of pipeline stages a deeply pipelined processor. In the instruction pipeline of Figure 1, there are 11 pipeline stages.
- fetch 1 and Fetch 2 Located at the head of the instruction pipeline illustrated in Figure 1 are two instruction fetch substages.
- the two instruction fetch substages are responsible for continually fetching new instructions for the instruction pipeline. Unconditional branch instructions within the instruction stream prevent the fetch substages from simply fetching sequential instructions. Furthermore, conditional branch instructions in the instruction stream prevent the fetch substages from simply fetching instructions along a predefined path. The instruction fetch substages must therefore fetch future instructions without knowing exactly where the program is going.
- the fetch substages at the head of an instruction pipeline are implemented with a branch prediction mechanism.
- the branch prediction mechanism predicts where branch instructions exist in the instruction stream and the outcome of these branch instructions.
- the instruction fetch unit then fetches the stream of instructions as predicted by the branch prediction mechanism.
- branch prediction mechanisms predict the outcome of a branch instruction based upon the outcome of prior occurrences of the branch instruction. Each time a branch instruction is resolved, the branch prediction mechanism stores the branch outcome in a branch history buffer. Upon subsequent occurrences of the branch instruction, the branch prediction mechanism makes a branch prediction based upon the collected branch history. Very high branch prediction rates have been achieved with such branch prediction mechanisms. For example, the Yeh & Patt two-level adaptive branch prediction mechanism achieves prediction rates with over 97% accuracy. (See Tse Yu Yeh and Yale N. Patt, Two-Level Adaptive Branch Prediction, The 24th ACM/IEEE International Symposium and Workshop on Microarchitecture, November 1991, page 60) Deeply pipelined processors can complicate the branch prediction process. Specifically, in deeply pipelined processors the branch instructions in a short program loop are often mispredicted by branch prediction mechanisms that use branch history to make predictions. An illustration of this problem is presented with reference to Figures 1, 2a and 2b.
- the program in Figure 2a comprises a very short loop.
- the first line of the program consists of a load instruction that loads a first register (Rl) with the absolute value 3.
- the second line of the program contains an add instruction that adds the value of the first register (Rl) to a second register (R2).
- the first register (Rl) is then decremented in the third line of the program.
- the program branches back to the second line of the program if the zero flag has not been set. Thus if the first register (Rl) does not yet contain the value 0, the program will loop back to the second line.
- the value in the second register (R2) is stored to memory.
- An accurate branch prediction mechanism can identify this repeating branch pattern and use the repeating branch pattern to make future branch predictions. For example an ideal implementation of the two-level adaptive branch prediction mechanism disclosed by Yeh & Patt would identify this pattern and then always correctly predict the outcome of future occurrences of the branch instruction. However, problems can occur when the branch prediction mechanism is implemented in a real processor with a deep pipeline.
- Figure 2b illustrates the contents of the instruction pipeline stages for the instruction pipeline of Figure 1 as the instructions in the program in Figure 2a flow through the processor.
- the instruction flow illustrated in Figure 2b assumes that instructions are fetched one-by-one and that there are no pipeline stalls. Furthermore, the instruction flow assumes that the branch prediction mechanism has built a "TTNTTNTTN . . .” branch history for the branch instruction in the fourth line of the program wherein T represents taken, N represents not-taken, and the rightmost letter represents the outcome of most recent occurrence of the branch instruction.
- first clock cycle illustrated in Figure 2b clock cycle N, the load instruction is first fetched.
- the load instruction moves to the fetch substage 2 and the first fetch substage fetches the Add instruction from the second line of the program.
- the processor proceeds to sequentially load instructions from memory into the instruction pipeline until the end of clock cycle N+3.
- the first fetch substage must make a branch prediction to load the next instruction. Since the branch history pattern for the branch contains "TTNTTNTTN . . .”, the fetch substage predicts (correctly) that branch will be taken. So at clock cycle N+4 the instruction fetch unit goes back to the second line of the program and fetches the Add instruction. Again, the processor proceeds to sequentially fetch instructions from memory into the instruction pipeline until the end of clock cycle N+6.
- the first fetch substage must again predict the outcome of the branch instruction in order to fetch subsequent instructions.
- the first occurrence of the branch instruction has reached the fourth pipestage, decode 1.
- the branch history still contains "TTNTTNTTN . . .”, since the branch history can not be updated until the branch instruction is fully resolved.
- the fetch substage again predicts (correctly) that branch will be taken. This amounts to a lucky guess since the branch prediction mechanism was actually predicting the first taken branch after the non-taken branch in the repeating pattern. So at clock cycle N+7 the instruction fetch unit again goes back to the second line to fetch the Add instruction.
- the processor then proceeds to sequentially fetch instructions from memory into the instruction pipeline until the end of clock cycle N+9.
- the first fetch substage must once again predict the outcome of the branch instruction in order to fetch subsequent instructions.
- the first occurrence of the branch instruction has reached the seventh pipestage (scheduling) and the second occurrence of the branch instruction has reached the fourth pipestage (decode 1).
- the branch history still contains "TTNTTNTTN . . .”. Therefore, the branch prediction mechanism will again predict that branch will be taken. However, this time its luck has run out since this prediction will eventually prove to be incorrect.
- the instruction fetch unit yet again goes back to the second line to fetch the Add instruction. When the processor eventually detects the misprediction, the Add instruction and all subsequent instructions will need to be flushed from the pipeline.
- the present invention stores a "speculative history" for each branch by assuming that each branch prediction that is made is correct. If the branch prediction accuracy rate is high enough, this technique improves the branch prediction accuracy rate for branches in small loops within a deeply pipelined processor.
- Figure 3 illustrates a branch target buffer entry for a branch prediction mechanism that stores speculative history.
- the first three fields in the branch target buffer entry of Figure 3 store information about the branch instruction used by the branch prediction mechanism.
- the first field of the branch target buffer entry is the tag address field 21.
- the tag address field 21 stores an address that identifies where the branch instruction is in memory.
- the actual history field 22 stores the branch history for all fully resolved occurrences of this particular branch.
- the Precalculated Prediction field 23 stores a branch prediction for the next occurrence of the branch based upon the branch history information stored in the Actual History field 22.
- the Precalculated Prediction field 23 in Figure 3 is an actual taken or not-taken branch prediction based upon the actual branch history field 22.
- the Precalculated Prediction field 23 is calculated whenever the actual history field is updated in order to reduce the time required to make a branch prediction from 2 cycles to 1 cycle.
- the next three fields in the branch target buffer entry of Figure 3 contain information required to maintain and use speculative history for each branch in the branch target buffer.
- the branch prediction mechanism 24 is set when the branch prediction mechanism of the present invention makes a branch prediction using this particular branch target buffer entry. Whenever a branch prediction is made, the branch prediction mechanism also updates the Speculative History field 25 and the Precalculated Prediction field 23.
- the Precalculated Speculative Prediction 26 stores a branch prediction for the next occurrence of the branch based upon the speculative branch history stored in the Speculative History field 25.
- the remaining fields in the branch target buffer entry of Figure 3 store information commonly used in branch target buffers.
- the Return Bit field 27 is set when the branch instruction is a "return from subroutine" instruction. When the Return Bit field 27 is set, the branch prediction mechanism should pop a value off a return stack buffer (RSB) which specializes in predicting return addresses.
- the target address field 28 stores the address where the instruction fetch unit should fetch instructions from if the branch prediction mechanism predicts that the branch will be taken.
- Figure 4 illustrates the method of updating the speculative history fields in the branch target buffer of the present invention.
- the process of updating the speculative history fields begins whenever the branch prediction mechanism makes a branch prediction that is based upon the branch's history as indicated by step 101 in Figure 4. Any type of branch prediction mechanism that is based upon the branch history can be used in the present invention.
- step 102 the condition of the Speculation Bit 24 is tested to see if there is speculative history for the branch instruction.
- the method moves to step 103 which sets Speculation Bit 24 to indicate that the branch target buffer entry will now contain speculative history.
- the Actual History field 22 is copied into the Speculative History field 25 to provide a starting point for the Speculative History.
- the Precalculated Prediction 23 is shifted into the Speculative History field 25 thereby providing the first bit of "Speculative History" since it is only a prediction that may eventually turn out to be wrong.
- step 102 if the Speculation Bit 24 is set, this indicates that earlier branch predictions have been made for this branch target buffer entry and that the Speculative History field 25 contains the history of those earlier predictions. Therefore, when the Speculation Bit 24 is set, the update process moves to step 105 which shifts the Precalculated Speculative Prediction Bit 26 into the Speculative History field 25 thereby adding another bit of "Speculative History" to the Speculative History field 25.
- the Precalculated Speculative Prediction Bit 26 should be recalculated using the new speculative history in the Speculative History field 25.
- the system checks if the branch is a conditional branch or an unconditional branch. If the branch is unconditional then the
- Speculative Precalculated Prediction bit 26 is set at step 108 since the branch is always taken. If the branch is unconditional then the branch prediction mechanism calculates a prediction for the branch based upon the newly updated Speculative History field 25. The new branch prediction is then placed into the Speculative Precalculated Prediction bit field 26 as stated in step 107. Updating the Actual History Fields in the Branch Target Buffer
- the branch instruction After making a branch prediction, the branch instruction continues along the instruction pipeline. Near the end of the instruction pipeline, the branch instruction for which a prediction was made eventual becomes fully resolved. When the branch instruction is fully resolved the branch prediction is verified against the result of the actual resolved branch instruction.
- the processor continues normally. However, if the branch prediction was wrong, then the processor must clear out every instruction in the instruction pipeline located after the mispredicted branch since the instruction fetch unit should not have loaded these instructions.
- the Speculation bit 24 in the branch target buffer is cleared as illustrated in Figure 3.
- Figure 5 illustrates the steps performed when a branch instruction eventually becomes fully resolved.
- the branch instruction becomes fully resolved thereby providing a final taken or not-taken branch outcome.
- the resolved branch outcome is shifted into the actual history field 22.
- the type of branch is examined. If the branch is unconditional, then the prefetched prediction bit 23 is set as stated in step 305. If the branch is unconditional, then the branch prediction mechanism calculates a branch prediction using the actual history in the actual history field 22 and places the prediction in the prefetched prediction bit 23 as stated in step 304.
- the branch prediction made for the branch is compared with the actual resolved branch outcome. If the branch prediction was correct, the update is complete and the processor continues along normally. However if the prediction was correct, the speculation bit 24 is cleared to prevent any further predictions using the incorrect speculative history in the speculative history field 25.
- Figure 6 illustrates how a branch prediction mechanism based upon a branch target buffer with speculative history fields uses the speculative history information to make predictions.
- the first step, step 201 is to search the branch target buffer to see if there is a branch target buffer entry. If there is no branch target buffer entry then the branch target buffer can not be used to make a branch prediction.
- the branch prediction mechanism must make a static branch prediction as stated in step 203.
- the branch prediction mechanism then checks the condition of the return bit 27 in the appropriate branch target buffer entry at step 204. If the return bit 27 is set, indicating that the branch is a "return from subroutine" instruction, then the branch prediction mechanism obtains a prediction from the return stack buffer that specializes in predicting return addresses as stated in step 205.
- the branch prediction mechanism then checks the condition of the Speculation bit 24 in the branch target buffer entry at step 206. This test determines whether the branch prediction mechanism should use the Precalculated Speculative Prediction 26 or the normal Precalculated Prediction 23.
- the Precalculated Speculative Prediction bit 26 is used to select a branch prediction as shown at step 210. If the Precalculated Speculative Prediction bit 26 is set, the branch prediction mechanism will predict a jump to the target address as shown in step 212; else the branch prediction mechanism predicts a fall-through at step 211.
- the normal Speculative Prediction bit 23 is used to select a branch prediction as shown at step 207. If the Speculative Prediction bit 23 is set, the branch prediction mechanism will predict a jump to the target address as shown in step 208; else the branch prediction mechanism predicts a fall-through at step 209.
- the instruction fetch unit fetches instructions along the predicted instruction stream.
- the branch prediction mechanism also uses the new branch prediction to update the speculative history fields as stated in step 213.
- Figure 7 illustrates the contents of the instruction pipeline stages for the instruction pipeline of Figure 1 when the program in Figure 2a is run in a processor that uses speculative history.
- the instruction flow illustrated in Figure 7 assumes that instructions are fetched one-by-one, that there are no pipeline stalls, and that the branch prediction mechanism has built a "TTNTTNTTN . . .” branch history for the branch instruction in the fifth line of the program.
- the processor sequentially loads instructions into the instruction pipeline as illustrated in Figure 7.
- the first fetch substage must make a branch prediction to load the next instruction. Since the branch history pattern for the branch contains "TTNTTNTTN . . .”, the fetch substage predicts (correctly) that branch will be taken. At this time, the Speculation bit for the branch entry will be set and the "branch taken" prediction will be shifted into the speculative history. Thus the speculative history will contain "TTNTTNTTNT . . .”. Since the branch prediction mechanism predicted the branch to be taken, the instruction fetch unit goes back to the second line of the program at clock cycle N+4 and fetches the Add instruction.
- the processor then proceeds to sequentially fetch instructions from memory into the instruction pipeline until the end of clock cycle N+6.
- the first fetch substage must again predict the outcome of the branch instruction in order to fetch subsequent instructions.
- the first occurrence of the branch instruction has reached the fourth pipestage, decode 1.
- the speculative history was updated using the predicted branch such that the speculative branch history now contains "TTNTTNTTNT. . .”. Since the speculation bit is set, the branch prediction mechanism in the fetch substage uses the "TTNTTNTTNT. . .” speculative history to predict (correctly) that branch will be taken. So at clock cycle N+7 the instruction fetch unit again goes back to the second line to fetch the Add instruction. Then the processor proceeds to sequentially fetch instructions from memory into the instruction pipeline until the end of clock cycle N+9.
- the first fetch substage must once again predict the outcome of the branch instruction in order to fetch subsequent instructions.
- the first occurrence of the branch instruction has reached the seventh pipestage (scheduling) and the second occurrence of the branch instruction has reached the fourth pipestage (decode 1).
- the branch history still contains "TTNTTNTTN . . .”.
- the speculative branch history contains "TTNTTNTTNTT. . .”. Since the speculation bit is set, the branch prediction mechanism will predict (correctly) that the branch should not be taken. So at clock cycle N+10 the instruction fetch unit fetches the Store instruction after the branch instruction.
- the branch prediction mechanism of the present invention that uses speculative history will correctly predict the outcome of branches in tight loops.
- Figure 8 illustrates the present invention as used in a typical computer system.
- the present invention comprises a branch prediction apparatus located within a processor.
- the branch prediction apparatus is used to fetch the proper instructions for the processor from the cache memory or the main memory.
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4493224T DE4493224T1 (en) | 1993-05-14 | 1994-04-08 | Speculative history mechanism in a branch target buffer |
AU67017/94A AU6701794A (en) | 1993-05-14 | 1994-04-08 | Speculative history mechanism in a branch target buffer |
JP6525425A JPH09500989A (en) | 1993-05-14 | 1994-04-08 | Inference history in branch target buffer |
KR1019950705082A KR100310581B1 (en) | 1993-05-14 | 1994-04-08 | Inference recording mechanism of branch target buffer |
BR9406606A BR9406606A (en) | 1993-05-14 | 1994-04-08 | Mechanism for speculative history in a branch object buffer |
GB9414028A GB2291513B (en) | 1993-05-14 | 1994-07-12 | Speculative history mechanism in a branch target buffer |
SE9503951A SE515698C2 (en) | 1993-05-14 | 1995-11-08 | Branch prediction apparatus for use in computer processor |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US6201293A | 1993-05-14 | 1993-05-14 | |
US08/062,012 | 1993-05-14 | ||
GB9414028A GB2291513B (en) | 1993-05-14 | 1994-07-12 | Speculative history mechanism in a branch target buffer |
Publications (1)
Publication Number | Publication Date |
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WO1994027210A1 true WO1994027210A1 (en) | 1994-11-24 |
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PCT/US1994/003897 WO1994027210A1 (en) | 1993-05-14 | 1994-04-08 | Speculative history mechanism in a branch target buffer |
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AU (1) | AU6701794A (en) |
BR (1) | BR9406606A (en) |
DE (1) | DE4493224T1 (en) |
GB (1) | GB2291513B (en) |
WO (1) | WO1994027210A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864697A (en) * | 1996-06-28 | 1999-01-26 | Texas Instruments Incorporated | Microprocessor using combined actual and speculative branch history prediction |
US8751776B2 (en) | 2011-01-07 | 2014-06-10 | Fujitsu Limited | Method for predicting branch target address based on previous prediction |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6260138B1 (en) * | 1998-07-17 | 2001-07-10 | Sun Microsystems, Inc. | Method and apparatus for branch instruction processing in a processor |
US6427206B1 (en) * | 1999-05-03 | 2002-07-30 | Intel Corporation | Optimized branch predictions for strongly predicted compiler branches |
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US4679141A (en) * | 1985-04-29 | 1987-07-07 | International Business Machines Corporation | Pageable branch history table |
US5142634A (en) * | 1989-02-03 | 1992-08-25 | Digital Equipment Corporation | Branch prediction |
US5168557A (en) * | 1988-09-21 | 1992-12-01 | Nec Corporation | Instruction prefetching device having a history table for memorizing page last real instruction addresses and page-over all real instruction addresses providing for quicker page-over processing time |
US5210831A (en) * | 1989-10-30 | 1993-05-11 | International Business Machines Corporation | Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations |
US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
US5265213A (en) * | 1990-12-10 | 1993-11-23 | Intel Corporation | Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US4477872A (en) * | 1982-01-15 | 1984-10-16 | International Business Machines Corporation | Decode history table for conditional branch instructions |
-
1994
- 1994-04-08 WO PCT/US1994/003897 patent/WO1994027210A1/en active Application Filing
- 1994-04-08 DE DE4493224T patent/DE4493224T1/en not_active Withdrawn
- 1994-04-08 AU AU67017/94A patent/AU6701794A/en not_active Abandoned
- 1994-04-08 BR BR9406606A patent/BR9406606A/en not_active IP Right Cessation
- 1994-07-12 GB GB9414028A patent/GB2291513B/en not_active Expired - Fee Related
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US4679141A (en) * | 1985-04-29 | 1987-07-07 | International Business Machines Corporation | Pageable branch history table |
US5168557A (en) * | 1988-09-21 | 1992-12-01 | Nec Corporation | Instruction prefetching device having a history table for memorizing page last real instruction addresses and page-over all real instruction addresses providing for quicker page-over processing time |
US5142634A (en) * | 1989-02-03 | 1992-08-25 | Digital Equipment Corporation | Branch prediction |
US5210831A (en) * | 1989-10-30 | 1993-05-11 | International Business Machines Corporation | Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations |
US5226130A (en) * | 1990-02-26 | 1993-07-06 | Nexgen Microsystems | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency |
US5265213A (en) * | 1990-12-10 | 1993-11-23 | Intel Corporation | Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction |
Non-Patent Citations (2)
Title |
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IEEE PUBLICATION, 1991, ALEX PELEG et al., "Future Trends in Microprocessors: Out-of-Order Execution, Speculative Branching and their CISC Performance Potential", pages 263-266. * |
IEEE PUBLICATION, October 1992, SHIEN-TAI PAN et al., "Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation", pages 76-83. * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5864697A (en) * | 1996-06-28 | 1999-01-26 | Texas Instruments Incorporated | Microprocessor using combined actual and speculative branch history prediction |
US8751776B2 (en) | 2011-01-07 | 2014-06-10 | Fujitsu Limited | Method for predicting branch target address based on previous prediction |
Also Published As
Publication number | Publication date |
---|---|
GB2291513B (en) | 1999-04-28 |
AU6701794A (en) | 1994-12-12 |
GB9414028D0 (en) | 1994-08-31 |
DE4493224T1 (en) | 1996-04-25 |
GB2291513A (en) | 1996-01-24 |
BR9406606A (en) | 1996-01-02 |
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