WO1995010086A1

WO1995010086A1 - Implementation of morphology manipulation in programmable hardware

Info

Publication number: WO1995010086A1
Application number: PCT/US1993/010652
Authority: WO
Inventors: Brad Taylor
Original assignee: Giga Operations Corporation
Priority date: 1993-10-05
Filing date: 1993-11-05
Publication date: 1995-04-13
Also published as: AU5592894A

Abstract

A system for and method of applying a morphological manipulation to an imaged object (11) using a configurable hardware device by reading a raster image to access a center pixel (5) and selected neighbor pixels (e.g. 1, 2), examining the neighbor pixels for a selected pattern and selectively modifying the center pixel according to a morphological operator and the state of the neighbor pixels. The output pixel can be combined with similarly processed output pixels to provide an output image. Alternatively, the output pixels can be processed through one or more sequential morphological manipulations (e.g. 102, 103) to provide a further modified output.

Description

IMPLEMENTATION OF MORPHOLOGY MANIPULATION IN PROGRAMMABLE HARDWARE

Field of the Invention

This invention relates to a method of manipulating the morphology of an image in a programmable hardware device and a system to implement the method.

Background of the Invention

One of the more significant processes in image processing is image morphology. See, generally, Edward Dougherty, "MATHEMAΉCAL MORPHOLOGY IN IMAGE PROCESSING," Marcel Dekker, Inc. (1992), and J. Serra, "IMAGE ANALYSIS AND MATHEMAΉCAL MORPHOLOGY," Academic Press (1988). A number of companies and academics are very interested in how to allow a computer to analyze an image and extract information which is often readily interpretable to a human. A typical problem involves identifying the boundaries of an object and often identifying the skeleton or center of the object. One aspect of the general problem is that image often contains noise such as random bits of data. Such noise may arise from a weak or clouded original image.

The Abingdon Cross benchmark has been used since 1982 for evaluating computers used in image processing. Kendall Preston, Jr., "Sci/J-ndustrial Image Processing: New System Benchmark Results," Advanced Imaging, pp. 46-50 & 82 (Sept. 1992). The standard input is an image, which may be used in a range of resolutions. A specified set of tasks must be performed on this image, but any particular solution might apply tasks in a select order and with a select number of iterations different from the choices made in a different solution. The image is noisy, so filtering is required to separate the cross from the noise. Next, morphological operations such as erosion, dilating and thinning are applied, leading to a final computation of the medial axis of the cross. Any resolution, for example 64 x 64 or even 8192x8192 can be used in a particular solution, depending on the resources of the available computing device. The results are normalized to account for different resolutions, cost, and computing power.

A variety of computational machines have been used to evaluate the cross, but none have used programmable logic devices (PLDs) or the systolic processor used in one preferred implementation of the present method and system. Image processors which have been used include a variety of software-only solutions (on conventional PCs and workstations) plus a variety of parallel processors, including massively parallel processors. Using the present method and system, the price performance factor (pixels processed per unit time multiplied by cost) should exceed 1 ,000 and the quality factor (size of image processed per execution time) should exceed 10⁶, which makes the new system among the most powerful available systems for its price. In addition, since the new system is a scaleable architecture, a significantly more powerful machine using the new method and system will allow significant image processing capability within a range of prices.

A morphological manipulation scheme can be implemented readily in a programmable logic device (PLD) such as a field programmable gate array (FPGA). PLDs are available from several manufacturers, including Xilinx, AT&T, Altera,

Atmel and others. In general, a PLD can operate much faster than a general purpose CPU and can handle asynchronous processes. A PLD is rarely as fast as an ASIC but does allow changes to the logic scheme. For most PLDs, the logic changes can be rapid (milliseconds). In most PLD applications the logic is changed only infrequently (only after weeks or months) but the logic can be changed many times a second, if desired.

The field of configurable or programmable hardware is well known and has been the subject of intense engineering development for the last few years. See in general the background section of co-pending, commonly-assigned United States Patent Application Serial No. 07/972,933, filed November 5, 1992, entitled "SYSTEM FOR COMPILING ALGORITHMIC LANGUAGE SOURCE CODE INTO HARDWARE," which is incorporated in full herein by reference.

Previous implementations of morphological manipulation devices have not used

PLDs since even the newest available devices have limited logic resources. The present method and system utilize a maximal amount of PLD resources for processing the algorithms and a minimal amount of PLD resources to interface with the system. The efficiencies of the present system allow a single Xilinx XC-4003 to process four morphological iterations.

Using PLDs provides the additional benefit that the configuration, and therefore the logic of each part, can be downloaded in a few milliseconds. Even more helpful is the fact that certain masking patterns can be loaded into PLD RAM so the same logical organization can be used to apply a wide variety of morphological operators. A new masking pattern can be loaded in a few microseconds. Alternatively, a particular logic scheme can be implemented using selected values in ROM and the entire scheme can be replicated in additional PLD resources, varying the values in ROM in different versions of the logic scheme.

Until this time, engineers have only begun to consider the possibility of "cacheing" functions as hardware configurations. The present method provides a way to implement a wide variety of functions in programmable hardware devices.

Summary of the Invention

The present invention provides a system for and method of applying a morphological manipulation to an image using a configurable hardware device by reading a raster image to access a center pixel and selected neighbor pixels, examining the neighbor pixels for a selected pattern and selectively modifying the center pixel according to a morphological operator and the state of the neighbor pixels. The output pixel can be combined with similarly processed output pixels to provide an output image. Alternatively, the output pixels can be processed through one or more sequential morphological manipulations to provide a further modified output.

The method involves identifying one or more morphological operations which are suitable for implementation in a PLD, delivering three adjacent lines from a frame buffer, selecting a center pixel and neighboring pixels and testing the pattern against one or more masks, then applying a morphological operator to selectively modify certain center pixels, then output the resulting center pixels. One preferred implementation includes implementing two delay lines and related components to provide three adjacent image lines from a single input line.

This system can implement additional operators which may be quite complex. In general, the architecture can be used to implement a variety of operators and provide a compact, fast and economical system for morphological manipulation.

One object of the invention is provide a method of implementing one or more morphological operators and implementing same in programmable hardware.

Another object of the invention is to provide a system to apply a series of morphological manipulations to an image to provide a pipelined image processor operating in real time at video frame rates.

Brief Description of the Drawings

Figure 1 illustrates an arbitrary shape to be analyzed.

Figure 2 illustrates horizontal and vertical edges on the shape of Figure 1.

Figure 3 illustrates a series of erosion operations on the shape of Figure 1. Figure 4 illustrates the result of one or more skeletonization operations on the shape of Figure 1.

Figure 5 illustrates a traditional 8 bit look-up table being combined with a separate bit.

Figure 6 illustrates a representative mask pattern and corresponding combinatorial truth table.

Figure 7 illustrates a preferred processing unit of the present invention, with a diagonal look-up table, a square look-up table and a central pixel being combined to give an output.

Figure 8 illustrates a double delay line to provide three aligned rows of adjacent pixels.

Figure 9 illustrates connecting a double delay line to a series of look-up tables to provide an output word.

Figure 10 illustrates a frame buffer and a series of morphological manipulation operators.

Description of the Preferred Embodiments

The method of the present invention involves identifying a type of image to be analyzed, then selecting an appropriate series of morphological operators required to manipulate the image to provide a desired result. Generally useful morphological operators include erosion, dilation, thickening, thinning and skeletonization. The operators can be applied sequentially to implement a high-throughput system. Many of these operators act on an image at an edge of the image, so it is helpful to identify when a pixel is at an edge. In some instances it is helpful to identify an edge or portion of an object that has a thickness of only one pixel. It also may be helpful to identify a direction of an edge and whether an edge is at an extreme, such as the end of a linear extension from a central portion of an object.

Referring to Figure 1, arbitrary object 10 has lower horizontal edges 11. By evaluating each pixel and its neighboring pixels, each edge can be identified. For example, examining the immediate horizontal, vertical and diagonal neighbors of each pixel gives a 3x3 matrix. Detail view 11 A shows upper 1, center 2 and lower 3 rows and left 4, center 5 and right 6 columns around center pixel 2,5. If the "interior" of the object is taken to be the binary value "1", then "exterior" is "0". One skilled in the art will recognize that the general principles described here can be extended to additional neighbors, e.g. 5x5 or neighbors in additional dimensions, e.g. 3x3x3, or with different intensity levels, e.g. 4-, 8- or 24-bit color.

A particular edge or pattern can be selected as a mask against which any array of pixels can be compared. Referring to Figure 2, appropriate masks can be selected to identify each bottom edge 11, top edge 12, right edge 13, and left edge 14. In like manner, other masks can be selected to identify top-left, top-right, bottom-left and bottom-right diagonals (not shown).

In a preferred implementation, when a match is found which corresponds to an edge, then an operator modifies the center pixel according to the specific match found and the particular operator. Referring to Figure 3, changing each center pixel which was originally at or just inside an edge to be outside will result in an erosion of the original outline 10 through succeeding stages 21 and 22 until the object is reduced to one or more lines 23 and finally to point 24. Referring to Figure 4, an erosion can be modified to not reduce an edge which is also at an appropriate extreme to leave a skeleton of the original object. Another operator can reduce a skeleton to a central point (not shown).

There are a variety of ways to implement such a morphological operator. A basic technique is to provide a look-up table (LUT) for each possible combination of pixel conditions. For a 3x3, 2 dimensional matrix, this can readily be implemented as a 9-bit LUT. Referring to Figure 5, if the center bit is pulled out of the look up table, the table can be reduced to an 8-bit table.

In addition, many patterns of interest include some symmetry, so a pattern can be rotated and tested against a still smaller LUT. Referring to Figure 6, for example, if a pattern involves only the four corners of the neighbor-array, that is, the diagonal neighbors, and the desired pattern is only one diagonal bit set and the others unset, then the mask can be implemented with four four-input OR gates to implement the illustrated truth table (A or B or C or D), or by using four four-input AND gates with the output of each directed to a four input OR gate, or by using a 4-bit LUT. Referring to Figure 7, the preferred implementation evaluates diagonal pixels 1, 3, 7, and 9 in 4-bit diagonal LUT 71, and horizontally and vertically adjacent "square" pixels 2, 4, 6 and 8 in 4-bit square LUT 72, the results of which are passed to central LUT 74 and combined with the state of pixel 5 in the array, center pixel 73 to give a result.

In a preferred implementation, the output of a frame buffer is coupled to two delay lines to provide three vertically adjacent rows of pixels. Referring to Figure 8, the output of frame buffer 81 is directed over line 82 directly to output line 88-0 and as an input to 2-bit latch 83 and delay line 86, which delivers an output one frame line later. For a 128 pixel line, the delay is 128 pixels. Using 8-bit words, this is a 16 word delay. The output 88-1 of delay line 86 is directed to the inputs of 2-bit latch 84 and a second delay line 87 which provides an identical delay on output 88-2 to provide the frame line two lines preceding the output on line 88-0. Output 88-2 is directed also to 2-bit latch 85.

Each 2-bit latch holds the last two bits of the previous output word. The overall result is, at one particular time, an output word, from a reference (current) input line, with bits 0-7 on output 88-0 with bits -2, -1 on latch 83, a second word with bits 0-7 and -2, -1, each offset by one line length or 128 bits, on output line 88-1 and latch 84 and a third word with bits 0-7 and -2, -1, each offset by two line delays or 256 bits on output line 88-2 and latch 85. This outputs word-by-word the current input line synchronized with two preceding lines for additional processing.

The length of the delay line can be modified as needed for any selected frame buffer size.

Each word then can be read out in series or in parallel using center pixels selected from first-delayed output 88-1 starting with pixel -1 then 0, 1, ..., and 6 as center pixels. Figure 9 illustrates a parallel connection where each of blocks 91-0, 91-1, ... 91-7 represent the structure shown in Figure 7 with, for example, the diagonal LUT of 91-0 connected to diagonal pixels -2, 0 of 88-0 and -2, 0 of 88-2 and the square LUT of block 91-0 connected to pixel -1 of 88-0, -2, 0 of 88-1 and -1 of 88-2 and finally a connection to center pixel -1 of 88-1. The center pixel of 91-1 is pixel 0 of 88-1, and the center pixel of 91-7 is pixel 6 of 88-1, with all of the intervening connections made in a corresponding manner. The outputs of 91-0 through 91-7 provide an 8-bit output word on line 92.

The word size selected in the circuit of Figure 8 can be varied from a single bit to a very large word such as 16 bits, 64 bits, or larger but each bit in the word needs a corresponding block of LUTs 91 in the circuit of Figure 9. The word size is not restricted to integral powers of two. Listing 1 is an example of code which can be compiled to provide the components of Figure 9.

Listing 1

PGA part= "4003PC84-6" ; mod_id=0xf0 ; bit ppbuf C;

CLK=C;

int2 line_inhi;

intβ aO,al ,a2 ,a3 ,a4 ,a5 ,a6 ,a7 ,aa; bit aaO, aal , aa2 , aa3 , aa4 , aa5 , aa6 , aa7 ;

bit rom alutOO [16]={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alutl0[16]={0 ,0,0,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom al t20[16]={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alut30[16]={0 ,0,0,0, 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alut40 [16 ]={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alut50[16}={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alutβO [16]={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alut70 [16]={0 ,0 ,0 ,0 , 0,0,0,0, 0,0,0,0, 1,0,0,0}; bit rom alutOl [16}={0 ,0 ,0 ,0 , 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alutll [16]={0,0 ,0 ,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alut21 [16]={0,0,0 ,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alut31 [16]={0, 0,0,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alut41 [16]={0 ,0,0,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alut51[16]={0 , 0,0,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alutβl [16]={0 , 0,0,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; bit rom alut71 [16]={0 ,0,0 ,0 , 0,0,0,0, 1,0,1,0, 1,0,1,0}; /* diag {0,0,0,0, 0,0,0,0, 0,0,0,0, 1,0,0,0}; square{0, 0,0,0, 0,0,0,0, 1,0,1,0, 1,0,1,0}; pat diag square

111 2-3 -3-

XXX 1-2

000 0-1 -0-

3210 3210

1100=c IxxO

1000=8

1010=a

1100=c

1110=e Listing 1 (con't)

*/ bit aoO , aol, ao2 , ao3 , ao4 , ao5 , ao6 , ao7; loc line _inhi={ Oxll ,0x11} ; loc lbuf I={0xl2 ,0x12 ,0x13 ,0x13 ,0x14 ,0x14 ,0x15 ,0x15} ; loc nine_l={0xl2 ,0x12 ,0x13 ,0x13 ,0x14 ,0x14 ,0x15 ,0x15} ; loc line_l={0x22 , 0x22 , 0x23 , 0x23 , 0x24 , 0x24 , 0x25 , 0x25 , 0x21 , 0x21} ; loc lbuf_2={0x32 , 0x32 , 0x33 , 0x33 ,0x34, 0x34 , 0x35 , 0x35} ; loc nine _2= {0x32 , 0x32 , 0x33 , 0x33 , 0x34 , 0x34 , 0x35 , 0x35} ; loc line 2={0x42 ,0x42 ,0x43 ,0x43 ,0x44 ,0x44 ,0x45 ,0x45 ,0x41 ,0x41 } ; loc alut00=0x24 ; loc alut01=0x22; loc ao0=0x052 ; loc alutl0=0x44;loc alutll=0x42; loc aol=0x052 ; loc alut20=0x23;loc alut21=0x23; loc ao2=0x053; loc alut30=0x43;loc alut31=0x43; loc ao3=0x053 ; loc alut40=0x22 ;loc alut41=0x24; loc ao4=0x054 ; loc alut50=0x42 ; loc alut51=0x44; loc ao5=0x054; loc alut60=0x21;loc alut61=0x25; loc ao6=0x055; loc alut 0=0x41; loc alut71=0x45; loc ao7=0x055; loc q={ 0x52 ,0x52 ,0x53 ,0x53 ,0x54 ,0x54 ,0x55 ,0x55} ; int4 adOO ,ad01; int4 adlO ,adll ; int4 ad20,ad21; int4 ad30 ,ad31; int4 ad40,ad41; int4 ad50,ad51; int4 ad60 ,ad61; int4 ad70,ad71; int4 qh, ql; void main(); void morf(); main( )

{ if (go)

{

( )morf; } ) morf ( )

{ line inhi= d; line] ~0===(d )&0x0ff

\(line_inhi«8)&0x300 lbuf_ l[t]=line 0; nine^'_ ~_l=lbuf_l; line^' l=(nine 1 )S0x0ff

! (line_l «8)&0x300; lbuf 2[t]=line 1; nine^' ~_2=lbuf_2; line^' ~2=(nine 2 )&0x0ff

I (line_2 «8)i0x300; Listing 1 ( con't) aO===line_0»0 ; al===line_0»2 ; a2===line_2»0 ; a3===line_2»2 ; a4===line_0»l ; a5===line_l »0; a6===line_l »2 ; a7-==line_2»l ; aa-===I ne 1»1 ; ad00=== (a0«0) &1 i (al«l)&2 J (a2«2)&4 i (a3«3)&8 ad01===(a4«0)&l 1 (a5«l)&2 ! (a6«2)&4

(a7«3)&8

adlO===(aO»l)&l j (al»0)&2 j (a2«l)&4 i (a3«2)&8 adll===(a4»l)&l I (a5»0)62 I (a6«l)&4 j (a7«2)&8

ad20===(aO»2)Sl j (al»l)&2 I (a2»0)&4

(a3«l)&8 ad21===(a4»2)&l i (a5»l ) &2 I (a6»0)&4 i (a7«l)&8

ad30===(a0»3)&l 1 (al»2)&2

(a2»l)&4 (a3»0)&8 ad31==' = (a4»3)&l (a5»2)&2 (a6»l)&4 (a7»0)&8

Listing 1 f con't) ad41===(a4»4)&l (a5»3)&2 (a6»2)&4 (a7»l)&8

ad50===(a0»5)Sl (al»4)&2 (a2»3)&4 (a3»2)&8 ad51===(a4»5)&l (a5»4)&2 (a6»3)&4 (a7»2)&8 ad60===(a0»6)&l (al»5)&2 (a2»4)&4 (a3»3)&8 ad61===(a4»6)Sl (a5»5)&2 (a6»4)&4 (a7»3)68 ad70===(a0»7)&l (al»6)&2 (a2»5)&4 (a3»4)68 ad71===(a4»7)&l

(a5»6)&2

(a6»5)&4

(a7»4)&8 } aaO=== (aa»0)&l; aal=== (aa»l)&l; aa2=== (aa»2)&l; aa3=== (aa»3)&l; aa4=== (aa»4)&l; aa5=== (aa»5)&l; aa6=== (aa»6)&l; aa7=== (aa»7)&l;

/* diags square pt */ ao0===~(alut00[ad00]&alut01 [ad01J)&aaO; aol===~(alutlO[adlOJ&alutll [adllJ)Saal; ao2===- (alut20[ad20]&alut21 [ad21])&aa2; ao3===~(alut30[ad30]&alut31 [ad31J)&aa3; ao4===~ (alut40 [ad40] &alut41 [ad41])&aa4; ao5===~(alut50[ad50]&alut51 [ad51])&aa5; ao6===~(alut60[ad60]&alut61 [ad61])&aaβ; ao7===~(alut70[ad70]&alut71 [ad71])&aa7; ql===

(aoO«0)&Oxl j (aol«l)&0x2

(ao2«2)&0x4 (ao3«3)&0x8 Listing 1 (con 't ) qh===

(ao4«0) &0xl i (ao5«l ) &0x2 j (ao6«2) &0x4 j (ao7«3) S0x8 q= (qh«4 ) &0xf0

\ (ql ) &0x0f

! qq===q;

}

loc lbuf_l_wr={ 0x31 } ; loc lbuf_2_wr={ 0x51} ;

DEND

The diagonal and square look-up tables are implemented as ROM but could be implemented as RAM so an alternative mask can be provided simply by entering new values in the look-up tables. The specific example initializes the LUTs to search for an upper edge such as edge 11 in Figure 1. The listing begins with instructions to connect system input and output, then provides the delay elements illustrated in Figure 8. Look-up tables alutOO - alut70 and alutOl - alut71 are defined as ROM but could also be implemented as RAM. The advantage of using ROM is that a specific configuration is more compact but if a problem called for rapidly modifying the masks, this could be implemented in RAM but at the cost of using more resources in a PLD.

The pattern tested here is a row of "l"s on top, a row of "0"s on the bottom, and a row of "don't care's" in the middle. The positions of the diagonal matrix and the square matrix are shown. For the diagonal test, only one combination will provided the required pattern, which is interpreted with this assignment to binary 1100 or hexadecimal C. For the square matrix, since positions 1 and 2 can be either 1 or 0, any of four specific matches will satisfy these conditions, namely hexadecimal

8, A, C or E.

The next portion of the listing assigns specific registers in a PLD, here a Xilinx XC-4003. Specifically placing these registers results in a more compact device due to certain limitations of the Xilinx .XNF compiler. The address fields of the LUT tables are assigned, followed by a definition of the clocked lines line_0, line_l (delayed by one line) and line_2. A series of and/or tests selects bits adOO - ad71 from each appropriate address field to provide the input for each diagonal and square LUT (the web of connections illustrated in Figure 9). These connections are based on combinatorial logic and are therefore asynchronous, all being interpreted on a single clock pulse. Center pixels are selected as aaO - aa7 and diagonal LUTs are combined with square LUTS and center pixels to provide output bits aoO - ao7. Due to idiosyncracies of the XC-4003, the bits must be merged to provide the final output word qq.

The structure shown in Figure 9 is set up to detect bottom edges. Depending on the operator of interest, the central LUT (74 in Figure 7) can set the state of each center pixel to implement the desired morphological manipulation. For erosion in all directions, for example, a previously set center pixel would be unset. For skeletonization, a previously set center pixel would be unset unless it rests on an edge in at least two directions (e.g. left and right, up and down or diagonally).

By chaining the output of one operator to the input of a second operator, an entire string of operators can be implemented. Referring to Figure 10, a first operator 102 can detect and modify each lower edge, a second operator 103 can detect and modify each upper edge, and subsequent operators 104, 105 can process right and left edges, then diagonal edges. A complete process might involve only a few operators or possibly a large number of operators. Intermediate or final results can be returned to the frame buffer 101. To analyze the Abingdon Cross might involve more than 50 such operators.

In a preferred implementation, the operator described above occupies about one quarter of a Xilinx XC-4003. Thus each 4003 can implement four operators. A PLD with more resources can implement a larger number of operators. The configuration described above can be modified readily to provide additional throughput. In general, one set of LUTs should be provided for each bit in a word being processed. A smaller implementation might have only two sets of LUTs to process a 2 bit word while another implementation might have 16 sets of LUTs to process 16 bit words. A more complex implementation might evaluate a larger number of neighbors or pixels with more than one-bit binary values, which would require a corresponding increase in logic resources.

The configuration can also be modified to implement a variable number of operators, depending on a specific application or any particular hardware resources. Since each operator can be chained in a pipeline or systolic configuration, sufficient processing power can be assembled to process an image of any arbitrary resolution or complexity. Processing 8 bits per clock at 20 Mhz provides a throughput of 20 megabits per second, which will hold true for any number of operators. Full NTSC frame rates are only 13 megapixels per second so this system can readily provide real-time video processing.

The structure of this implementation contains no inherently parallel processes and so can be used in either parallel or serial processing.

Using programmable hardware, a series of operators may be applied to a given input, then a new configuration loaded into the hardware to continue processing.

The method and system described above can be very useful in a more comprehensive hardware implementation of algorithmic language code. An original source code program in a language such as "C" can be compiled to implement a variety of morphological operators and loaded as a configuration in a PLD. See, in general, the methods and systems described in co-pending, commonly-assigned United States Patent Application Serial No. 07/972,933, filed November 5, 1992, entitled "SYSTEM FOR COMPILING ALGORITHMIC LANGUAGE SOURCE CODE INTO HARDWARE," which is incorporated in full herein by reference.

A general description of the system and method of using the present invention as well as a preferred embodiment of the present invention has been set forth above. One skilled in the art will recognize and be able to practice additional variations in the methods described and variations on the device described which fall within the teachings of this invention. The spirit and scope of the invention should be limited only as set forth in the claims which follow.

Claims

ClaimsWhat is claimed is:

1. A method of manipulating an image by applying a morphological operator implemented in a configurable hardware device.

2. The method of claim 1 further comprising selecting a center pixel, selecting a plurality of neighboring pixels, testing said neighboring pixels for a selected pattern of values, and applying said morphological operator to said center pixel.

3. The method of claim 2 wherein said morphological operator is selected from the group consisting of erosion, thinning, thickening, and skeletonizing.

4. The method of claim 2 wherein said selected pattern of values is a pattern which shows the center pixel is at or just inside the edge of an object.

5. The method of claim 4 wherein said edge is selected from the list consisting of a lower edge, an upper edge, a right edge, a left edge, and a diagonal edge.

6. The method of claim 1 further comprising implementing and applying morphological operator to said image.

7. A system for morphological manipulation of an image, said system comprising: an input image of a series of pixels as a series of rows, configurable hardware connected to receive said image, said configurable hardware comprising: a first output line to provide a series of pixels from a first row of said image, a second output line to provide a series of pixels from a first preceding row of pixels of said image, and a third output line to provide a series of pixels from a second preceding row of pixels of said image.

8. The system of claim 7 further comprising: a first delay line with an input connected to said output line, said second output line connected to the output of said first delay line to provide a series of pixels from said first preceding row of pixels of said image, a second delay line with an input connected to said second output line, and said third output line connected to the output of said second delay line to provide a series of pixels from said second preceding row of pixels of said image.

9. The system of claim 7 further comprising an implementation of a morphological operator connected to receive pixels from said first, second and third output lines, identify a selected center pixel from said second output line and a neighbor pixel in a selected relationship to said center pixel, and apply a morphological operator to said selected center pixel, depending on the value of said neighbor pixel.

10. The system of claim 9 further comprising an operator connected to identify a plurality of neighbor pixels and to apply a morphological operator.

11. The system of claim 9 wherein said morphological operator is selected from the group consisting of erosion, thinning, thickening and skeletonization.

12. The system of claim 7 further comprising a look-up table containing a pattern of values, said look-up table connected to one or more of said output lines.

13. The system of claim 7 further comprising a diagonal look-up table connected to said output lines to access a plurality of pixels diagonally adjacent to a selected center pixel on said second output line and a square look-up table connected to said output lines to access a plurality of pixels horizontally and vertically adjacent to said selected center pixel on said second output line.

14. The system of claim 13 further comprising a morphological operator connected to combine the outputs of said diagonal look-up table, said square look-up table, and the value or said selected center pixel and provide an output pixel.

15. The system of claim 14 further comprising a plurality of said morphological operators connected as in claim 14 to output a series of output pixels.

16. The system of claim 14 further comprising a subsequent series of similarly connected components including first, second and third output lines, diagonal look-up table, square look-up table, selected center pixel and a second morphological operator connected to provide a second output pixel.