WO1995022110A1

WO1995022110A1 - Write-read data operation for microprocessor

Info

Publication number: WO1995022110A1
Application number: PCT/US1995/001547
Authority: WO
Inventors: Graham B. Whitted, Iii; James A. Kane; Hsiao-Shih Chang
Original assignee: Meridian Semiconductor, Inc.
Priority date: 1994-02-08
Filing date: 1995-02-08
Publication date: 1995-08-17
Also published as: TW357295B

Abstract

A circuit and a method rapidly and efficiently perform string-move and other memory-to-memory move operations. By recognizing that it is unnecessary to pass the read data through the central processing unit (102) on memory-to-memory move operations, the number of clock cycles required to perform a memory-to-memory move operation is reduced. A higher rate of throughput is thereby achieved. The circuit and method are embodied in a memory control unit (104) of a microprocessor (100). The memory control unit (104) stores the data read from the read portion (T3, T4) of a string move operation or memory-to-memory move operation and writes the stored data to memory (106) during the write portion (T5, T6) of the operation which occurs in the clock cycle (T5) immediately following the read portion of the operation. The central processing unit (102) of the microprocessor (100) is bypassed during the operation.

Description

WMTE-READ DATA OPERATION FOR MICROPROCESSOR

FIELD OF THE INVENTION

This invention relates to microprocessors. In particular, this invention relates to a microprocessor circuit and method for performing a memory-to-memory move operation.

BACKGROUND OF THE INVENTION

Microprocessors commonly employ an internal memory control unit ("MCU") to control accesses to cache and external memory. To access memory, the central processing unit ("CPU") of the microprocessor issues memory access commands to the MCU. These memory access commands are typically in the form of a specified field of a micro-instruction. Micro-instructions are typically issued by the CPU at a rate of one micro-instruction per CPU clock cycle. The MCU responds to memory access commands by performing the requested operation, and returning the requested data, if any, to the CPU.

A number of microprocessors have macroinstructions (hereinafter "instructions") for performing a memory-to-memory operation, wherein the microprocessor reads a data value from one external memory location (or from cache), and then writes the data value to another external memory location. The "string- move" (MOVS) instruction of the 486 microprocessor is an example of such a memory-to-memory move instruction. When the 486 executes a string-move instruction, the CPU initially issues a read command to the MCU requesting that the MCU perform a read operation from a specified read address. Once the read data is available, the MCU returns the data to the CPU. The CPU then issues a write command to the MCU and sends the data back to the MCU, and the MCU writes the data to the specified write address. Most other microprocessors perform memory-to-memory move operations in a similar fashion, with the read data being passed through the CPU before being written back to memory.

For the 486, the string-move of a memory operand not residing in cache normally requires 8 clock cycles. Since individual memory accesses on the external memory bus normally require only two cycles, the external memory bus is utilized during only 4 of the 8 clock cycles. Furthermore, during clock cycles for which the CPU waits for the requested data to be returned from the MCU, the CPU normally suspends all ongoing operations. Thus, this technique for executing string-move instructions tends to be inefficient.

SUMMARY OF THE INVENTION The present invention is a circuit and method for rapidly and efficiently performing string-move and other memory-to-memory move operations with a microprocessor. Memory-to-memory move operations of data values are performed by the microprocessor without passing the data values through the CPU of the microprocessor. The number of clock cycles required to perform such operations is thereby reduced. One aspect of the present invention is a memory control unit (MCU) circuit of a microprocessor that performs memory-to-memory move operations of data values residing in an external memory. The microprocessor has a central processing unit (CPU) that issues memory access commands to the MCU. The MCU circuit comprises a command input bus that receives the memory access commands from the CPU. An address input bus receives addresses from the CPU. The addresses specify locations within the external memory for performing the memory access operations. A bi-directional data input bus transfers the data values between the MCU and the external memory in response to the memory access commands and the addresses received from the CPU. A read buffer is connected to the bi-directional bus to receive and temporarily store the data values read from the external memory on the bi-directional data bus. A write buffer is connected to the bi-directional data bus to temporarily store the data values being written to the external memory. A data router transfers the data values from the read buffer to the write buffer without passing the data values through the CPU, to thereby increase the speed of the memory-to-memory move operations by bypassing the CPU. Preferably, the data router comprises a multiplexer that selects between the data values from the read buffer and data values from the CPU. The multiplexer has a first data input connected to the read buffer, a second data input connected to the CPU, a data output connected to the write buffer, and a control input that selects between the first data input and the second data input.

Another aspect of the present invention is a method of using an MCU of a microprocessor to perform a memory-to-memory move operation of a data value. The memory-to-memory move operation is performed by the MCU in response to memory access commands issued by a CPU of the microprocessor. On a first clock cycle, the CPU of the microprocessor issues a read command to the MCU, and specifies the read address to the MCU. Assuming the data value specified by the read address is not found in cache, the MCU responds to the read command by initiating a read operation on an external memory bus. On the second clock cycle, before the MCU has completed the read operation, the CPU issues a unique "Write Read Data" command to the MCU, and specifies a write address to the MCU. The MCU responds to the Write Read Data command once the read operation is complete by routing the read data value from a read buffer of the MCU to a write buffer of the MCU, without passing the data through the CPU. On the clock cycle immediately following completion of the read operation, the MCU places the data value back out on the external memory bus and initiates a memory write operation. Thus, no unutilized clock cycle or "gap" occurs on the external memory bus between the read operation and the write operation. A faster memory-to-memory move operation is thereby achieved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a high level block diagram of the logic of a microprocessor for accessing external memory;

Fig. 2 illustrates the timing for the execution of a string-move instruction by a 486 microprocessor;

5 Fig. 3 illustrates the timing for the improved method of the present invention for performing a string- move operation; and

Fig. 4 illustrates the data paths within the MCU for performing a Write-Read-Data operation.

In the drawings, like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit of a reference number identifies the drawing in which the reference number 0 first appears.

DETAILED DESCRIPTION OF THE INVENTION

Fig. 1 is a high level block diagram of the logic of a microprocessor for accessing external memory. The diagram is representative of the 486 microprocessor, and other microprocessors which incorporate an internal MCU. The diagram is also representative of a microprocessor suitable for the technique of the present

15 invention.

The microprocessor 100 has a CPU 102 and an MCU 104. The MCU 104 is interfaced to an external memory array 106 ("memory") by a bi-directional data bus 108, and an address/control bus 110. The CPU 102 and MCU 104 are interconnected by a unidirectional command/address bus 120, a unidirectional read-data bus 122, a unidirectional write-data bus 124, and one or more handshaking lines 126. 0 The execution of a string-move instruction as performed by the 486 will now be described with reference to Figs. 1 and 2. During a first clock cycle T1 of execution, the CPU 102 issues a read command (READ CMD) to the MCU 104 on the bus 120. During a second clock cycle T2, the MCU 104 checks the internal cache (not shown) for the requested data, assuming cache is enabled. If the data is not present in cache, as indicated in Fig. 2 by the occurrence of a cache miss, the MCU 104 performs a memory read on

25 the address/control bus 110 and data bus 108 during third and fourth clock cycles T3, T4. The MCU 104 also asserts a wait signal on a handshaking line 126 in order to suspend the operation of the CPU 102 until the requested data is available.

Once the data has been read from memory 106, the data is sent to the CPU 102 on the read-data bus 122. During a fifth clock cycle T5 the CPU 102 issues a write command (WRITE CMD) to the MCU

30 104 on the command/address bus 120, and specifies a write address to the MCU 104 on the command/address bus 120. The CPU 102 also returns the read data to the MCU 104 on the write-data bus 124. The MCU 104 responds during a sixth clock cycle T6 by checking whether a cache entry exists for the specified write address. In this example, the CPU 102 determines that no such entry exists, as indicated by the occurrence of a cache miss during the sixth clock cycle T6. The MCU 104 then writes the data to memory 106 on seventh and eighth clock cycles T7, T8.

As illustrated by Fig. 2, the 486 does not utilize the busses 108, 110 to memory 106 during the fifth and sixth clock cycles T5, T6 for the memory-to-memory move operation described above. Thus, a gap occurs in the memory bus usage as the read data passes through the CPU 104. A similar gap occurs with other microprocessors that pass memory-to-memory move data through the CPU. This gap significantly limits the throughput of these microprocessors when memory-to-memory moves of blocks of data are performed using sequences of consecutive string-move instructions. The solution to this problem involves the use of a unique Write-Read-Data (WRD) command, for instructing the MCU 104 to write to memory 106 the read data currently residing in a read buffer 400 (Fig. 4) of the MCU 104. The Write-Read-Data command can be issued to the MCU 104 before a preceding read operation has been completed by the MCU 104, provided that the read data is present in the read buffer 400 by the time the Write-Read-Data operation is performed by the MCU 104. Fig. 3 illustrates an improved method in accordance with the present invention for performing a memory-to-memory move operation using the WRD command. Referring to Fig. 3, the CPU 102 issues a read command to the MCU 104 on the bus 120 during the first clock cycle Tl, and then issues a WRD command to the MCU 104 on the bus 120 during the second clock cycle T2. The MCU 104 performs the memory read during the third and fourth clock cycles T3, T4, and stores the data in a read buffer 400 (Fig. 4) of the MCU 104. During the fifth and sixth clock cycles T5, T6, immediately following the memory read, the

MCU 104 writes the read data to the memory address specified by the CPU 102 on the bus 120 when the

WRD command was issued during the second clock cycle T2. The microprocessor 100 thus bypasses the

CPU 102 on memory-to-memory operations, and thereby eliminates the 2-cycle gap experienced with the 486.

As illustrated by Fig. 3, the memory-to-memory operation in accordance with the method of the present invention requires only 6 clock cycles. Furthermore, as illustrated by Fig. 3, pipelining permits back- to-back memory-to-memory instructions to be overlapped such that the memory busses 108, 110 can be utilized on every cycle. Thus, memory-to-memory moves of blocks of data can be performed at fastest possible rate permitted by the busses 108, 110.

Fig. 4 is a simplified diagram of the data paths within the MCU 104 for performing a WRD operation. A read buffer 400 is connected to the bus 108 for temporarily storing data read from memory 106. The read buffer 400 is connected to the bus 122 for supplying read data to the CPU 102. The bus 122 has a path 402 allowing the read data to be fed to a multiplexer 404. The multiplexer 404 has a control input 406 for selecting between read data held by the read buffer 400, and write data supplied by the CPU 102 on the bus 124. The control input 406 may be driven by microcode, or by a command register (not shown) of the MCU 104. The output of the multiplexer 404 is fed to a write buffer 408 by a bus 412. The write buffer is connected to the bus 108, allowing data to be written to memory 106.

Referring to Fig. 4, when the MCU 104 receives a read command in response to a memory-to- memory move instruction, the MCU 104 performs a memory read operation and places the read data in the read buffer 400. The data residing in the read buffer 400 at any given time will reflect the most recent memory read operation performed by the MCU 104. When the MCU 104 performs a WRD operation in response to a WRD command, the multiplexer 404 selects the path 402 and routes the read data currently in the read buffer 400 to the write buffer 408. The read data is then written to memory 106.

It should be recognized that the WRD command of the present invention can be utilized whenever a memory-to-memory move operation is performed by the microprocessor, and is not limited to string-move instructions. For example, the WRD command can be issued when a memory read instruction is followed by a memory write instruction wherein the read data is written back to memory. In order to take advantage of the WRD command in this situation, the instruction decode unit of the microprocessor must be designed to recognize the occurrence of such back-to-back memory read/memory write instructions, and to generate the appropriate micro-instruction to perform a WRD operation. Various designs of instruction decode units and instruction control units for generating micro-instructions based on sequences of two or more instructions are well known by those skilled in the art, and are beyond the scope of this invention.

The circuit and method described for performing a memory-to-memory move operation have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A memory control unit (MCU) circuit of a that performs memory-to-memory move operations of data values residing in an external memory, said MCU circuit being internal to a microprocessor, said microprocessor having a central processing unit (CPU) that issues memory access commands to an MCU, said MCU circuit comprising: a command input bus that receives said memory access commands from said CPU; an address input bus that receives addresses from said CPU, said addresses specifying locations within said external memory for performing said memory access commands; a bi-directional data input bus that transfers said data values between said MCU and said external memory in response to said memory access commands and said addresses received from said CPU; a read buffer connected to said bi-directional bus that receives and temporarily stores said data values read from said external memory on said bi-directional data bus; a write buffer connected to said bi-directional data bus that temporarily stores said data values being written to said external memory; and a data router that transfers said data values from said read buffer to said write buffer without passing said data values through said CPU, to thereby increase the speed of said memory-to- memory move operations by bypassing said CPU.

2. The MCU circuit of claim 1, wherein said data router comprises: a multiplexer that selects between said data values from said read buffer and data values from said CPU, said multiplexer having a first data input connected to said read buffer, a second data input connected to said CPU, a data output connected to said write buffer, and a control input for selecting between said first data input and said second data input.

3. The MCU circuit as defined in Claim 1 combined with said external memory for holding said data values.

4. A method of using a memory control unit (MCU) of a microprocessor to perform a memory- to-memory move operation of a data value, said memory-to-memory move operation being performed in response to memory access commands issued by a central processing unit (CPU) of said microprocessor, said memory access commands being issued by said CPU in response a memory-to-memory move macroinstructions issued to said microprocessor, said method comprising the steps of: receiving a first command from said CPU specifying a read operation; receiving a read address from said CPU, said read address specifying a first external memory location for reading said data value from an external memory; responding to said first command by reading said data value from said first external memory location and placing said data value directly into a read buffer of said MCU; receiving a second command from said CPU specifying a Write Read Data operation; receiving a write address from said CPU, said write address specifying a second external memory location for writing said data value to said external memory; transferring said data value from said read buffer of said MCU to a write buffer of said MCU without passing said data value through said CPU; and writing said data value from said write buffer to said external memory location specified by said write address.

5. The method of claim 4, wherein said step of receiving a second command is performed by said MCU before said step of responding to said first command is completed by said MCU.

6. A method for performing a memory-to-memory move operation of a data value using a microprocessor having a central processing unit (CPU) and a memory control unit (MCU), said memory-to- memory move operation being performed in response to a memory-to-memory macroinstruction issued to said microprocessor, said method comprising the steps of: reading said data value from a first memory location of an external memory into a read buffer of said MCU; transferring said data value from said read buffer of said MCU to a write buffer of said

MCU without passing said data value through said CPU; and writing said data value from said write buffer of said MCU to a second memory location of said external memory.

7. The method of claim 6, wherein said step of reading said data value and said step of writing said data value occur during consecutive cycles of a CPU clock.