WO1996023252A1

WO1996023252A1 - Data transmission system

Info

Publication number: WO1996023252A1
Application number: PCT/SE1996/000049
Authority: WO
Inventors: Carl-Erik Arvidsson; Martin Lindblom
Original assignee: Telefonaktiebolaget Lm Ericsson
Priority date: 1995-01-27
Filing date: 1996-01-19
Publication date: 1996-08-01
Also published as: EP0806004A1; DE69620583T2; SE9500289L; DE69620583D1; US5892920A; AU4637196A; SE9500289D0; SE503914C2; EP0806004B1

Abstract

A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.

Description

Data transmission system.

Technical Field of the Invention.

The present invention generally relates to data transmission with speeds of the order of magnitude of several Gigabits/sec between two clock domains, of which each may be constituted by e.g. a CPU, a part of an ATM switch or other equipment which sends and receives data. ATM allows transmission of large data quantities over arbitrary media with the use of data packages with a prescribed length and small overhead. More specifically, the invention relates to a data transmission system, in which data streams are to be transmitted at a large speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds.

Description of Related Art.

In two data transmission systems, which are operating with approximately the same clock frequency generated by two separate oscillators, one in each system, and which are to be connected and transmit data to each other, a certain drift may occur between the frequencies. Because of this a buffer must be inserted between the two systems, which may emit data faster than it receives it, or vice versa, depending on which system's clock frequency is the larger one. In the US patent 5,305,253 a memory with separate read and write buses, two address ring counters, one for write and one for read operations, and an alarm which detects when the buffer is empty and full, is described. Since it is very difficult to make memories with a reply time shorter than 7 ns without resorting to the use of GA, this solution is not usable at frequencies of the order of magnitude of Gigabits/sec.

In the US patent 4,819,201 an asynchronous FIFO circuit is described which includes consecutive data storage registers. which relay incoming data if the following register is empty. When the FIFO circuit is empty data will accordingly be let through from the beginning of the register stack to its end. This may cause risk for degradation of data and is furthermore a slow solution.

Among other publications relating to the same subject, the following may be mentioned.

US patent 5,319,597 "FIFO memory and line buffer",

US patent 5,084,837 "FIFO buffer with folded data transmission path permitting selective bypass of storage",

US patent 4,803,654 "Circular first-in, first-out buffer system for generating input and output addresses for read/write memory independently" .

Summary.

An object of the present invention is to provide a fast, small and simple data buffer between the two clock domains in the data transmission system defined above by way of introduction. This is achieved according to the invention through a data buffer, which includes a number of data storage elements, a tree shaped structure of multiplexer elements, a write address generator and a read address generator. The data storage elements have data inputs connected in parallel to an input for a data stream from the sending clock domain. The tree shaped structure of multiplexer elements is arranged to receive data from the data storage elements, and emits on an output a data stream to the receiving clock domain. The write address generator generates, controlled by a write clock signal from the clock of the sending clock domain, read addresses for entering data from the sending clock domain into the data storage elements, one at a time. The read address generator generates, controlled by a read clock signal from the clock generator of the receiving clock domain, read addresses for reading out data from the data storage elements in the same order as they were entered.

The tree shaped structure can have a first level of multiplexer elements connected to receive data in parallel from each a number of the data storage elements. A number of following levels of storage elements are connected to receive data from a number of the multiplexer elements of the previous level. A last level includes a multiplexer element, on the output of which a data stream is emitted to the receiving clock domain.

More specifically, the multiplexer elements of the first level can each be connected to receive data from at least two of the data storage elements, and each of the multiplexer elements of the following levels can be connected to receive data from at least two of the multiplexer elements of the preceding level.

Brief Description of the Drawings.

Embodiments of the invention will now be described more closely with reference to the attached drawings. On the drawings

Fig. 1 is a principle diagram of a data transmission system,

Fig. 2 shows a first embodiment of the data transmission system according to the invention,

Fig. 3 shows a more detailed embodiment of the data transmission system according to Fig. 2, Fig. 4 shows an address generator included in the embodiment according to Fig. 3,

Fig. 5 shows signals appearing in the circuit according to Figs. 3 and 4.

Detailed Description of Embodiments.

In Fig. 1 102 and 104 each denotes a clock domain. The clock domains 102 and 104 may e.g. each be a CPU, a part of an ATM switch or some other equipment sending and receiving data respectively. The clock domain 102 has an internal clock oscillator which operates with a first clock speed, and the clock domain 104 has an internal clock oscillator operating with a second clock speed, which differs from the first clock speed.

Data shall be transmitted from the clock domain 102 to the clock domain 104. Because of the different clock speeds of the two clock domains, a buffer 106 must be present in the transmission stage, which causes serial data dl, leaving the first clock domain 102 with the first clock speed, to enter the second clock domain 104 in the form of serial data d2 with the second clock speed. The circuit 106 has a control input 110 for a clock signal cl from the sending clock domain 102 and a control input 112 for a clock signal c2 from the receiving clock domain 104. A corresponding arrangement may be present in the opposite direction, i.e. from the clock domain 104 to the clock domain 102.

The circuit in Fig. 2 corresponds to the buffer 106 in Fig. l. It contains a number of data storage elements 202-L .. -202_n , which are connected in parallel via each a data input 204-_j^ .. -204_n to the data input di which receives a serial data stream from the sending clock domain 102. The data storage elements 202--_ ...202_n furthermore each have a control input 208 ...208_n . The control inputs 208₂ ...208_n are connected to a write address generator 210, which, controlled by the clock signal arriving on a control input 212 from the clock of the sending clock domain 102, addresses the data storage elements 202 ...202_n , one by one, for entering therein data arriving on the data input di.

The data storage elements 202 ...202_n each have a data output 21 2 •••214_n and are pairwise connected with a respective data output 214₂ • • -²¹⁴n ^{to a} multiplexer n a first level of multiplexers 216₂ ...216_n/₂ - The multiplexers 216₂ • • -²¹⁶n/2 ^{forτn tne to}P most level in a tree structure of multiplexers, indicated by an arrow 218, which are ended by an output multiplexer 220, from data output 222 of which the serial data stream d2 is supplied to the receiving clock domain 104. A read address generator 224 is arranged, controlled by the clock signal c2 appearing on a control input 226 from the clock generator of the receiving clock domain 104, to read the multiplexers in the tree structure 218 in the same order as data has been entered into the data storage elements 202₂ ...202_n, for reading out data from the buffer 106.

The data storage elements may consist of data flip-flops, latches or other elements with memory functionality. As the man of the art well knows a data flip-flop enters and stores data at e.g. positive or negative edges of a control signal. As is also known a latch is transparent at a first logical level on the input, i.e. data on the input is visible on the output after a certain time delay, and this data content is stored at a second logical level, i.e. becomes insensitive to changes on the input.

As concerns the above mentioned multiplexers it may also here be the question of circuits of a type well known to the man of the art. As an example, circuits of flip-flop type may be mentioned, where data is entered on one input or the other on a rising and falling edge, respectively, of a control signal, or circuits of channel selector type. Circuits of the latter type may e.g. present two inputs and be made-up of two NAND gates, connected so that data on one input or the other may pass through in case of e.g. a 1 or 0, respectively, of a control signal.

A more detailed embodiment of the general embodiment of the invention indicated in Fig. 2 is shown in Fig. 3. The circuit in Fig. 3 contains four data storage elements 302, 304, 306 and 308, corresponding to the data storage elements 202₂ ...202_n . The data storage elements 302, 304, 306 and 308 are here assumed to consist of edge triggered data flip-flops. The data flip-flops 302, 304, 306 and 308 each have a data input and a control input connected in the same way as in Fig. 2. Thus, the data inputs in the same way as in Fig. 2 are connected in parallel to the data input di, which is connected to receive the serial data stream dl from the sending clock domain, and the control inputs are, in a way to be explained closer below, connected to a read address generator. The control inputs of the data flip-flops 304 and 308 are inverted. The tree structure in Fig. 3, corresponding to the tree structure 218 in Fig. 2, in this case only contains two levels of multiplexers, which in this case are assumed to consist of circuits of channel selector type of the kind mentioned above. The first level includes multiplexers 310 and 312, connected with their respective two inputs to receive data from the flip- flops 302 and 304, and 306 and 308, respectively. The respective data outputs of the multiplexers 310 and 312 are connected to each one of the two inputs of an output multiplexer 314 on the output level. On the data output of the multiplexer 314 the resulting serial data stream d2 is emitted to the receiving clock domain 104.

In Fig. 3 the read address generator is denoted 316 and the write address generator 318. An example of the realization of the read address generator is shown more in detail in Fig. 4.

The read address generator according to Fig. 4 includes a four phase clock dividing circuit with two flip-flops 402 and 404, respectively. The flip-flops 402 and 404 on a respective control input 406 and 408, respectively, receive the clock signal cl via an input ci. The flip-flops 402 and 404 further each have two clock outputs coO and co2, and col and co3, respectively. The clock output co3 of the switch 404 is connected to an additional control input 410 of the switch 402, and the clock output coO of the switch 402 is connected to an additional control input 412 of the switch 404.

The way of operation of a circuit of the kind shown in Fig. 4 is well known to the man of the art and need therefore not be described more closely here. It will, however, appear partially and indirectly in the below following description of the signal generation of the circuit in Fig. 3.

The clock outputs coO, col, co2 and co3 are connected to each one of the control inputs, denoted 320, 322, 324 and 326, respectively, of the data flip-flops 302, 304, 306 and 308, respectively.

The read address generator 318 can be implemented in the same way as the above described write address generator 316, and the same description need thus not be repeated here. It receives on its control input the clock signal c2, and its clock outputs col, co2 and co3 are connected to each a control input 328, 330 and 332, respectively, of the multiplexers 310, 314 and 312, respectively.

In Fig. 5 the signals appearing in Figs. 3 and 4 are shown, the same designations of these signals being used in Figs. 3 and 4. The clock signals received on the control inputs 320, 322, 324 and 326, respectively, of the data flip-flops 302, 304, 306 and 308, respectively, are denoted clO, ell, cl2 and cl3, respectively. The data signals from the data flip- flops 302 and 304 received on the two data inputs of the multiplexer 310 are denoted dsO and dsl, respectively, and the data signals from the data flip-flops 306 and 308 received on the two data inputs of the multiplexor 312 are denoted ds2 and ds3, respectively. The output data signals from the multiplexers 310 and 312 on the two data inputs of the output multiplexer 314 are denoted mO and ml, respectively. The clock signals from the clock outputs col, co2 and co3 of the read address generator are denoted c21, c22 and c23, respectively.

On its first row Fig. 5 shows the clock signal cl from the sending clock domain 102 on the control input ci of the write address generator 316. Thereafter follows, on the second row, the data signal including four bits 502 from the sending clock domain 102 on the data input of the data flip-flops 302, 304, 306 and 308, respectively.

If the system in Fig. 3 starts from 0 the first output clock signal with a rising edge will be clO, whereupon ell, cl2 and cl3, respectively, follow in the order mentioned. Each rising edge of cl0-cl3 will appear on each a rising edge of the clock signal cl from the sending clock domain. That stated appears in Fig. 5 from the arrows 504, 506, 508 and 510, which lead from the rising edge of each one of a sequence of four consecutive pulses of the clock signal cl to the rising edge of each one of consecutive pulses of the clock signals clO, ell, cl2 and cl3, respectively. It is also indicated by the respective additional arrows from the rising edge of the sequence in question of four pulses of the clock signal cl, that these rising edges also serve to end the respective previous pulse cl2, cl3, clO and ell, respectively, cf. e.g. arrow 511 from the rising edge of the fourth cl pulse to the falling edge of the first ell pulse. In other words, each change of the signals cl0-cl3 occurs on the rising edge of a cl pulse. This is a consequence of the feed-back loops leading to the control inputs 408 and 410 in Fig. 4.

It also appears from Fig. 5 that the frequency of the signals cl0-cl3 constitutes a fourth of the frequency of the clock signal cl.

As indicated by arrows 512, 514, 516 and 518 consecutive pulses of the data signals dsO, dsl, ds2 and ds3, respectively, appear on the rising edge of consecutive pulses of the clock signals clO, ell, cl2 and cl3, respectively.

The data signal mO is composed of the data signals dsl and dsO, and the data signal ml is composed of the data signals ds3 and ds2. Arrows 520, 522 and 524 indicate that dsl and dsO are chosen when the clock signal c21 is low and high, respectively. In a similar way arrows 526, 528 and 530 indicate that ds2 and ds3 are chosen when the clock signal c23 is high and low, respectively.

From Fig. 5 it finally also appears how the data signal d2 is composed of the data signals mO and ml, which is achieved by the multiplexer 314 controlled by the clock signal c22.

Claims

Claims.

1. A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, characterized by a data buffer between the clock domains including a number of data storage elements the data inputs of which are connected in parallel to an input for a data stream from the sending clock domain, a tree shaped structure of multiplexer elements, which are connected to receive data from the data storage elements, and to emit a data stream to the receiving clock domain, a write address generator, which controlled by a write clock signal from the clock of the sending clock domain generates read addresses for entering data from the sending clock domain into the data storage elements, one at a time, a read address generator, which controlled by a read clock signal from the clock generator of the receiving clock domain generates read addresses for reading out data from the data storage elements in the same order as they were read in.

2. A system according to claim 1, characterized in that the tree shaped structure has a first level of multiplexer elements connected to receive data in parallel from each a number of data storage elements, a number of following levels of storage elements, which are connected to receive data from a number of the multiplexer elements of the preceding level, and a last level including a multiplexer element, on the output of which a data stream is emitted to the receiving clock domain.

3. A system according to claim 2, characterized in that each of the multiplexer elements of the first level are connected to receive data from at least two of the data storage elements, and that each of the multiplexer elements of the following levels are connected to receive data from at least two of the multiplexer elements of the preceding level.