WO1996039759A1

WO1996039759A1 - Controlling the flow of atm cells in an atm network

Info

Publication number: WO1996039759A1
Application number: PCT/US1996/008906
Authority: WO
Inventors: Trevor Jones
Original assignee: General Datacomm, Inc.
Priority date: 1995-06-05
Filing date: 1996-06-05
Publication date: 1996-12-12
Also published as: GB2301985A; GB9511319D0; GB9611706D0; CA2222413A1; EP0878068A1; EP0878068A4; GB2301985B

Abstract

Method of controlling flow of ATM cells by signalling to the source of cells on a connection to reduce transmission rate when congestion occurs in a switch in an ATM network. The step of signalling being carried out by way of inserting into the Resource Management cells a new Explicit Rate ER value (28) for the connection at a given point in the network. The ER value being obtained is a function of the number of Available Bit Rate (ABR) cells output from the buffer in an interval. The method includes determining the Number of ABR Virtual Containers VCs with more than a predetermined number of cells stored, determining the number of cells on the connection stored, determining the total number of cells currently stored and the remaining capacity of the buffer, and calculating the ER value from a given formula.

Description

CONTROLLING THE FLOW OF ATM CELLS IN AN ATM NETWORK

Field of the Invention

This invention relates to a method of controlling the flow of ATM cells in an ATM network, and to an ATM network switch in which the method is carried out.

Background to the Invention

The ABR (Available Bit Rate) service in Asynchronous Trans¬ fer Mode (ATM) networks is intended to make the best use of remaining capacity after higher priority services such as CBR (Constant Bit Rate) and VBR (Variable Bit Rate) have been pro¬ vided for. To achieve this, special ATM cells known as Resource Management or Rm cells are sent from the source, through the destination and back to the source to provide information on the congestion level in the switches in the path. This is used by the source to modify its transmission rate, the objective being to utilize link capacity fully while not losing any cells as a result of congestion. An Explicit Rate (ER) parameter is set in the Rm cells passing through the switch in the forwards and backwards directions, the ER being reduced as congestion occurs down to the Minimum Cell Rate (MCR) value to reduce the rate at which the source sends.

In addition, the Message Type field in the Rm cell includes Congestion Indication (CI) and No Increase (NI) bits which may be set respectively to signal to the source that a predetermined decrease in the transmission rate should be effected and that the source should not automatically increase the send rate - it is normally arranged to keep pushing the send rate up again after the ER has signalled a reduction, in order to ensure that the rate is not permanently depressed. The switch may generate a backwards Rm cell (known as BECN) to the source to indicate congestion, the rate of these being limited to 10 per second per connection. The Explicit Rate or ER parameter thus dictates the maximum rate at which the source is allowed to send in cells per second. MCR dictates the minimum rate at which a source may always send. ER must therefore not be set less than MCR.

Summary of the Invention

The present invention provides a method of controlling the flow of ATM cells in an ATM network, comprising signalling to the source of cells on a connection to reduce the transmission rate when congestion occurs in a switch in the network, the signalling being carried out by way of insertion into Resource Management Rm cells of a new Explicit Rate (ER) value for the connection, wherein the ER value is obtained at a given point in the network for each cell arriving at said point, said point including a buffer for the cells, by: counting the number of ABR cells output from the buffer within a predetermined time interval to give an ABR Output Band¬ width value (AOB) ;and calculating an ER value as a function of AOB.

Preferably, the method comprises: determining the Number Nact of ABR VCs with more than a predetermined number of cells stored in the buffer; determining the number of cells VcCnt on the connection stored in the buffer; determining the total number of cells TSC currently stored in the buffer and the remaining capacity BS of the buffer; and calculating the ER value as a function of AOB, Nact, VcCnt, TSC and BS.

More preferably, the ER value is calculated from the fol¬ lowing formula:

d-.VcCnn I. TSC

~r MAX BS+K_β wherein MAX is a predetermined function reflecting the delay from the source of ABR cells in the network to the said point, and Ker is a predetermined offset value which determines the occupancy of the buffer for the VC on which the cell is being transmitted.

Preferably, N is a value which is incremented when a cell is written into the buffer on a VC having a VcCnt of less than

16, and the formula is:

Preferably, the method includes multiplying the number of ABR cells output during the predetermined period by a predeter¬ mined constant to give the AOB value.

The invention further provides an ATM network switch com¬ prising a buffer means for buffering the flow of ATM cells and means for calculating the Explicit Rate (ER) value for a connec¬ tion thereon, the calculating means comprising: means for counting the number of ABR cells output from the buffer within a predetermined time interval to give an ABR Output Bandwidth value (AOB) ; and means for calculating an ER value as a function of AOB.

Preferably the switch comprises: means for determining the Number Nact of ABR VCs with more than a predetermined number of cells stored in the buffer; means for determining the number of cells VcCnt stored in the buffer for the cell's VC; means for determining the total number of cells TSC cur¬ rently stored in the buffer and the remaining capacity BS of the buffer; and wherein the calculating means is arranged to calculate the ER value as a function of AOB, Nact, VcCnt, TSC and BS. More preferably, the switch comprises means for storing for each VC established through the switch an offset value Ker which determines the maximum occupancy of the buffer for the connection and a value MAX which is a predetermined function reflecting the delay from the source of ABR cells in the network to the switch, and the calculating means is arranged to calculate the ER value according to the following formula:

^ N_lct * {^l MAX p i¹ BS+K_e

Another aspect of the invention provides an ATM network switch comprising transmitting means and receiving means associ¬ ated with an external data link to the switch, and memory means connected to the transmitting means and to the receiving means, and wherein the transmitting means is arranged to write to the memory means congestion data contained in Resource Management (Rm) cells being transmitted by the transmitting means and the receiving means is arranged to read the said data from the memory means and to modify in accordance with the said data congestion data contained in reverse Rm cells arriving at the receiving means from the external data link.

The congestion data preferably comprises the ER, NI and CI fields in the Rm cell, and may be modified in the reverse Rm cells so as to OR the NI and CI fields with the values from the memory means and to set the reverse Rm ER value as the MCR or the lowest of the new and old ER values if this is greater than the MCR value.

Brief Description of the Drawings

In the drawings, which illustrate an exemplary embodiment of the invention:

Figure 1 is a diagrammatic representation of the ER calcu¬ lating means in an ATM network switch;

Figure 2 is a diagrammatic representation of further com¬ parison means; and

Figure 3 is a diagrammatic representation of the ATM switch. Detailed Description of the Illustrated Embodiment

Referring to Figure 1, the formula is first translated in to the form:

4 x AOB x ABRATE x (MAX-NcCnt) x (BS+K_g-TSC) ^ER" Ν_^xMAXx(BS+K where ABRATE is a factor which converts AOB, the number of cells in a predetermined arbitrary period, into a uniform rate of cells per unit time, this is because divisions are difficult to im¬ plement in hardware, and this form requires only one division operation, with the numerator and denominator being calculated separately before the division is performed. (In the formula shown above, a factor of 4 is used because Νact is divided by four in the implementation described to reduce the size of the numbers to be accommodated in an 18x18 multiplier.)

Multiplexers 11 and 12 (Fig la) pass the successive inputs to the adder/subtracter 13. First the Buffer Space BS and the offset Ker are added together and the result stored in a first register 14. The Total of Stored Cells TSC is then supplied to the adder/subtracter 13 via multiplexer 12 and the BS+K result is read out of register 14 and returned to the adder/subtracter 13 via multiplexer 11, a subtraction operation yielding BS+K-TSC, which is stored in register 15. Finally, the value MAX is sup¬ plied to the adder/subtracter 13 via multiplexer 11 and the VcCnt value is supplied via multiplexer 12, and another subtraction operation is performed to yield MAX-VcCnt, which is stored in register 16. If the result of either subtraction is negative, a flag is stored in register 17, the flag signalling that ER is to be set to zero.

Referring back to the translated formula shown above, the multiplication operations are carried out in the second part of the mechanism, illustrated in Figure lb. The results of the addition and subtractions are supplied to the multiplier 18 via multiplexers 19 and 20 via holding registers 21 and 22. Since the products of the various numerator and denominator parameters lead potentially to 68 bit values, the calculation is simplified by treating the numbers as powers of two, with an 18 bit mantissa and 7 bit exponent. The splitter 25 receives the 36-bit numbers from the multiplier and converts the numbers to 18/7 format by left-justifying all results, using the full 18 bits for the number, even if a negative exponent results, to ensure a constant resolution. After each multiplication, the resulting mantissa is passed back to the relevant one of the multiplexers 19 and 20 until the full calculation is complete, when the result is stored in registers 23a and 23b for the mantissas. The exponents are accumulated in accumulators 24a and 24b, these being reset to zero at the beginning of each calculation cycle. The mantissas are then passed to divider 27 while the exponents pass to subtracter 26. Converter 28 outputs the results of these calcu¬ lations as a 9 bit mantissa with a 5 bit exponent, which matches the format of the cell rates in the Rm cell.

Figure 2 shows the next stage in which the newly-calculated ER is compared in turn with the old ER value and the MCR value from the Rm cell, the comparator 29 performing the following: if NewER < MCR set ERout = MCR else, if NewER < OldER set ERout = NewER else set ERout = OldER.

Figure 2 represents the situation at the receive side of the switch. In the case of the transmit side of the switch, the comparison is carried out additionally with the ER value calcu¬ lated at the receive side. The ER value is transmitted from the receiver to the transmitter across the switch fabric by writing it to the MCR field in the cell. At the transmitter, the ER value is read out again, and replaced by the MCR value which is stored in the routing table in the switch when the VC is set up. Figure 3 illustrates in simplified form an ATM switch having a receiver 30 receiving cells on a connection from its source, a switch fabric 31, and a transmitter 32 passing the cells on to the next stage of the connection. A second receiver 33 receives Rm cells being returned to the source from the destination, a second transmitter 34 passing the cells on to the next stage back towards the source. A dual-ported RAM 35 is connected to the transmitter 32 and to the second receiver 33. It will be appre¬ ciated that connections may be configured with a source at each end so that forward and backward Rm cells will flow through each link to the switch.

When a forward data cell is received by the receiver 30, the state of congestion is assessed in the manner described in our co-pending application GDC-082PCT filed on even date herewith. If the EFCI Threshold has been reached, then:

- for EFCI switch behavior, the EFCI bit is set in all user data cells, and when a Rm cell arrives, the CI or NI bits are used according to programmable options (per connection) ;

- for ER switch behavior, action is only taken for Rm cells (no EFCI bits are set) . The new ER is calculated and placed in the cell (if less than the existing ER and more than MCR) , and CI or NI bits are optionally set. If the receiver 30 is congested, then an internal code is set in the ATM cell for the transmitter 32 to act on.

The transmitter 32 performs the same behavior as the re¬ ceiver 30, but also with the option of writing ER, CI and NI data to the dual-ported RAM 35.

The switch can function with two alternative modes: simple, in which the new ER value is written to the cell for forward transmission, the changed ER then being signalled back to the source from the destination; or more complex, in which the cell is passed onwards or forwards with the old ER value unchanged, the test establishing the lowest value of ER to be written to the DPRAM 35. In the receiver 33 the ER value stored is written in to the next cell only if it is lower than the existing value in the cell. If there is no congestion, the maximum possible value of ER is put into the DPRAM so that the backward ER in the back¬ ward cells is not changed.

Claims

1. A method of controlling the flow of ATM cells in an ATM network, comprising signalling to the source of cells on a con¬ nection to reduce the transmission rate when congestion occurs in a switch in the network, the signalling being carried out by way of insertion into Resource Management Rm cells of a new Explicit Rate (ER) value for the connection, wherein the ER value is obtained at a given point in the network for each cell arriving at said point, said point including a buffer for the cells, by: counting the number of ABR cells output from the buffer within a predetermined time interval to give an ABR Output Band¬ width value (AOB) ; and calculating an ER value as a function of AOB.

2. A method according to Claim 1, comprising: determining the Number Nact of ABR VCs with more than a predetermined number of cells stored in the buffer; determining the number of cells VcCnt on the connection stored in the buffer; determining the total number of cells TSC currently stored in the buffer and the remaining capacity BS of the buffer; and calculating the ER value as a function of AOB, Nact, VcCnt,

TSC and BS.

3. A method according to Claim 2, wherein the ER value is cal¬ culated from the following formula:

AOB / VcCnt \ ( TSC

N_ια ^X( MAXJ^X( BS+K_e wherein MAX is a predetermined function reflecting the delay from the source of ABR cells in the network to the said point, and Ker is a predetermined offset value which determines the occupancy of the buffer for the VC on which the cell is being transmitted.

4. A method according to Claim 3, wherein Nact is a value which is incremented when a cell is written into the buffer on a VC having a VcCnt of less than 16, and the formula is:

5. A method according to any preceding claim, comprising multi¬ plying the number of ABR cells output during the predetermined period by a predetermined constant to give the AOB value.

6. A method of controlling the flow of ATM cells in an ATM network, substantially as described with reference to the draw¬ ings.

7. An ATM network switch comprising a buffer means for buffering the flow of ATM cells and means for calculating the Explicit Rate

(ER) value for a connection thereon, the calculating means com¬ prising: means for counting the number of ABR cells output from the buffer within a predetermined time interval to give an ABR Output Bandwidth value (AOB) ; and means for calculating an ER value as a function of AOB.

8. A switch according to Claim 7, comprising means for deter¬ mining the Number N of ABR VCs with more than a predetermined number of cells stored in the buffer; means for determining the number of cells VcCnt stored in the buffer for the cell's VC; and means for determining the total number of cells TSC cur¬ rently stored in the buffer and the remaining capacity BS of the buffer; and wherein the calculating means is arranged to calculate the ER value as a function of AOB, Nact, VcCnt, TSC and BS.

9. A switch according to Claim 8, comprising means for storing for each VC established through the switch an offset value Ker which determines the maximum occupancy of the buffer for the connection and a value MAX which is a predetermined function reflecting the delay from the source of ABR cells in the network to the switch, and wherein the calculating means is arranged to calculate the ER value according to the following formula:

10. A switch according to Claim 9, wherein Nact is a value which is incremented when a cell is written into the buffer on a VC having a VcCnt of less than 16, and the formula is:

11. A switch according to any of Claims 7 to 10, wherein the calculating means comprises means for multiplying the number of ABR cells output during the predetermined period by a predeter¬ mined constant to give the AOB value.

12. An ATM network switch, substantially as described with reference to the drawings.

13. An ATM network switch comprising transmitting means and receiving means associated with an external data link to the switch, and memory means connected to the transmitting means and to the receiving means, and wherein the transmitting means is arranged to write to the memory means congestion data contained in Resource Management (Rm) cells being transmitted by the transmitting means and the receiving means is arranged to read the said data from the memory means and to modify in accordance with the said data congestion data contained in reverse Rm cells arriving at the receiving means from the external data link.

14. A switch according to Claim 13, wherein the memory means comprises a dual-ported Random Access Memory.