WO1996042112A1 - Semiconductor integrated circuit device, production thereof, and semiconductor wafer - Google Patents

Semiconductor integrated circuit device, production thereof, and semiconductor wafer Download PDF

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Publication number
WO1996042112A1
WO1996042112A1 PCT/JP1996/000940 JP9600940W WO9642112A1 WO 1996042112 A1 WO1996042112 A1 WO 1996042112A1 JP 9600940 W JP9600940 W JP 9600940W WO 9642112 A1 WO9642112 A1 WO 9642112A1
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Prior art keywords
semiconductor
integrated circuit
circuit device
layer
insulating layer
Prior art date
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PCT/JP1996/000940
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French (fr)
Japanese (ja)
Inventor
Shinichiro Wada
Tamotsu Miyake
Nobuo Tamba
Akihisa Uchida
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Hitachi, Ltd.
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Publication of WO1996042112A1 publication Critical patent/WO1996042112A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a SOI (Silicon On Insulator) structure.
  • SOI Silicon On Insulator
  • SOI technology in which a thin semiconductor layer is formed on a semiconductor substrate via an insulating layer and an element is formed in this semiconductor layer, is capable of complete element isolation. Therefore, when a semiconductor element is formed on a single-crystal silicon substrate, The following advantages are obtained as compared with.
  • the above-mentioned document discloses a technique for forming a sufficiently thin semiconductor layer and completely depleting the channel region when a gate voltage is applied, as a measure for preventing floating of the channel region.
  • Japanese Patent Application Laid-Open No. 62-109355 discloses that as a measure for preventing floating of a channel region, a second p-type semiconductor region electrically connected to a p-type semiconductor region where a channel region is formed is an n-channel type. It discloses a technique that is formed at the end of the source / drain region (n-type semiconductor region) of the MIS FET and applies a fixed potential to this second p-type semiconductor region.
  • An object of the present invention is to provide a technique capable of preventing a threshold voltage of a MIS FET formed on an S01 substrate from fluctuating and setting a threshold voltage to an enhancement type.
  • Another object of the present invention is to provide a technique capable of preventing a fluctuation of a threshold voltage of an MIS FET formed on an SOI substrate and improving a current driving capability. It is in.
  • an MIS FET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer, and the MIS FET is formed on the insulating layer below a channel region of the MIS FET.
  • An opening is provided, and the channel region and the semiconductor substrate are electrically connected through the opening.
  • the method for manufacturing a semiconductor integrated circuit device includes the steps of: forming a MISFET on a substrate having an SOI structure in which a semiconductor layer is formed on a semiconductor substrate via an insulating layer;
  • the channel region of the MIS FET is electrically connected to the semiconductor substrate through the opening in the insulating layer, fluctuation of the threshold voltage due to floating of the channel region is prevented. Thus, stable operation of the MIS FET can be achieved.
  • the threshold voltage can be controlled without reducing the thickness of the semiconductor layer until the channel region is completely depleted when the gate voltage is applied, the resistance values of the source and drain regions can be prevented from increasing.
  • the current drive capability of the MIS FET can be improved.
  • FIG. 1 is a plan view of a main part of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II in FIG. 1
  • FIG. 4 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 5 is a sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 6 is a sectional view of a semiconductor according to the first embodiment of the present invention.
  • FIG. 1 is a plan view of a main part of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II in FIG. 1
  • FIG. 4 is a cross-sectional view of a main part of an SOI substrate showing a
  • FIG. 7 is a perspective view of an SOI substrate showing a method of manufacturing an integrated circuit device
  • FIG. 7 is a sectional view of a main part of the SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 9 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 10 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 12 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a manufacturing method.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 12 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a manufacturing method.
  • FIG. 13 is
  • FIG. 15 is a view illustrating a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 16 is a sectional view of a main part of an SOI substrate, and FIG. 16 is an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • Fragmentary cross-sectional view, FIG. 1 7 is a fragmentary cross-sectional view of a SOI substrate showing a method of manufacturing another semiconductor integrated circuit device which is an embodiment of the present invention. Best mode for implementing
  • FIG. 1 and 2 show a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view of a main part of the SOI substrate
  • FIG. 2 is a cross-sectional view taken along line II in FIG.
  • the semiconductor integrated circuit device according to the present embodiment includes a semiconductor substrate 1 and semiconductor layers 3 a and 3 b formed on the semiconductor substrate 1 via an insulating layer 2.
  • a CMOS (Complimentary MOS) circuit composed of an n-channel MIS FETQn and a p-channel MISFETQp is formed.
  • the semiconductor substrate 1 is made of P-type single-crystal silicon (Si), and an n-type well 4 is formed on a part thereof.
  • the insulating layer 2 is composed of a silicon oxide layer having a large number of openings 5 formed at equal intervals.
  • the semiconductor layer 3a is made of an n-type epitaxial single-crystal silicon, and is electrically connected to the n-type well 4 through an opening 5 formed in the insulating layer 2 thereunder.
  • the semiconductor layer 3b is made of p-type epitaxial single crystal silicon, and is electrically connected to the p-type semiconductor substrate 1 through an opening 5 formed in the insulating layer 2 thereunder.
  • the n-channel type MISFETQn is formed on the main surface of the active region of the p-type semiconductor layer 3b surrounded by the element isolation field insulating film 6 made of silicon oxide.
  • the n-channel type MIS FETQn includes an n-type semiconductor region (source region, drain region) 7 formed in the semiconductor layer 3 b, a silicon oxide gate insulating film 8 formed on the surface of the semiconductor layer 3 b, A gate electrode 9 made of polycrystalline silicon formed on the gate insulating film 8.
  • the semiconductor layer 3 b immediately below the gate electrode 9, that is, the channel region, is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2.
  • a wiring 12 is connected to another active region of the p-type semiconductor layer 3b through a connection hole 11 formed in a silicon oxide insulating film 10, and a substrate potential of about 12 V is supplied. Is done.
  • the semiconductor layer 3b is formed with the n-channel type MIS FETQn. Like the semiconductor layer 3b, the semiconductor layer 1b is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2 thereunder.
  • the n-channel type MISFETQn electrically connects the channel region to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 and supplies a substrate potential to the channel region, thereby forming the channel region.
  • the P-channel type MISFETQp is formed on the main surface of the active region of the IT type semiconductor layer 3a surrounded by the field insulating film 6.
  • the p-channel type MIS FETQp includes a p-type semiconductor region (source region and drain region) formed in the semiconductor layer 3a, a gate insulating film 8 formed on the surface of the semiconductor layer 3a, and a gate insulating film 8 And a gate electrode 9 formed thereon.
  • the semiconductor layer 3 a immediately below the gate electrode 9, that is, the channel region is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2.
  • a wiring 12 is connected to another region of the IT type semiconductor layer 3 a through a connection hole 11 formed in the insulating film 10, and a gate potential of about 2 V is supplied.
  • the semiconductor layer 3a is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2 below the semiconductor layer 3a, similarly to the semiconductor layer 3a on which the p-channel type MIS FETQ is formed. .
  • the p-channel type MIS FETQp electrically connects the channel region to the n-type well 4 through the opening 5 of the insulating layer 2 and supplies a jewel potential to the channel region, thereby forming a channel. This prevents the area from floating.
  • the threshold voltage is controlled without reducing the thickness of the semiconductor layers 3a and 3b until the channel region is completely depleted when the gate voltage is applied.
  • the resistance of the source and drain regions (n-type semiconductor region 7 and p-type semiconductor region 13) is prevented from increasing, and the current drive capability of each of the n-channel MIS FETQn and p-channel MIS FETQp Can be improved.
  • the threshold voltage can be prevented from lowering due to the manifestation of the parasitic bipolar transistor effect, and the threshold voltage can be set to an enhancement type.
  • a fixed potential is supplied to the channel region through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b.
  • the current drive capability of each of the n-channel MISFETQn and the p-channel MISFETQp can be improved. Further, it is possible to prevent an increase in the junction capacitance of the source and drain regions (the n-type semiconductor region 7 and the p-type semiconductor region 13), thereby improving the operation speed.
  • the heat generated during the operation of the n-channel MIS FETQn and the p-channel MIS FETQp is transferred to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b. Since the heat can escape, the heat dissipation of the SOI substrate can be improved.
  • the insulating layer 2 and the photoresist 15 are formed.
  • removing the photoresist 15 see FIG.
  • an opening 5 reaching the semiconductor substrate 1 and an opening 5 reaching the n-type well 4 are formed.
  • the openings 5 are formed at equal intervals along directions orthogonal to each other on the main surface of the insulating layer 2.
  • the opening 5 is formed such that its diameter is smaller than the gate length of the gate electrode of the MISFET.
  • the interval between the openings 5 that are in contact with each other is smaller than the MIS that is in contact with each other along the gate length direction. It is set to be lZn (n is a natural number) of the interval between the gate electrodes of the FET.
  • a ⁇ -type semiconductor layer 3b is selectively formed on each surface of the semiconductor substrate 1 and the n-type well 4 exposed at the bottom of the opening 5. Epitaxial growth. The semiconductor layer 3 b is grown until the semiconductor layers 3 b grown through the respective openings 5 are connected to each other at the upper part of the insulating layer 2 so as to cover the entire surface of the insulating layer 2.
  • the semiconductor layer 3b is removed by CMP (Chemical Mechanical Polishing). (ng; chemical mechanical polishing) method or etch back, and the surface is flattened.
  • CMP Chemical Mechanical Polishing
  • the semiconductor layer 3b has a thickness at least such that the channel region is not completely depleted when a gate voltage is applied.
  • an n-type impurity (phosphorous or arsenic) is implanted into the semiconductor layer 3 b in the region where the p-channel MIS FET Qp is formed using the photoresist 17 as a mask.
  • An ⁇ -type semiconductor layer 3a is formed.
  • a thick field insulating film 6 for device isolation and a gate insulating film 8 are formed on each surface of the semiconductor layers 3a and 3b.
  • the gate electrode 9 is formed on the gate insulating film 8 of each of the semiconductor layers 3a and 3b by patterning the polycrystalline silicon film deposited by the CVD method as shown in FIG. .
  • a p-type impurity (boron) is implanted into the semiconductor layer 3a to form a source / drain region (p-type semiconductor region 13) of the P-channel type MIS FET Qp.
  • a source / drain region (n-type semiconductor region 7) of n-channel type MIS FETQn is formed.
  • an insulating film 10 of silicon oxide is deposited on each of the n-channel type MISFETQn and the p-channel type MISFETQp by the CVD method.
  • the wiring 12 is connected to each of the source and drain region (p-type semiconductor region 13) of the channel type MIS FETQp and the source and drain region (n-type semiconductor region 7) of the ⁇ -channel type MIS FETQn.
  • the CMOS circuit shown in FIGS. 1 and 2 is completed by connecting the wiring 12 for supplying the gate potential to the semiconductor layer 3a and the wiring 12 for supplying the substrate potential to the semiconductor layer 3b in another region. I do.
  • the SOI substrate composed of the semiconductor substrate 1, the insulating layer 2, and the semiconductor layers 3a and 3b made of epitaxial silicon single crystal was used. After implanting oxygen ions into the semiconductor substrate 1 made of, the semiconductor substrate 1 is heat-treated to form a silicon oxide insulating layer therein.
  • An SOI substrate obtained by a so-called SI OX (Separation by Implanted Oxygen) method can also be used.
  • the insulating film (or photoresist) 18 of silicon oxide or the like formed on the p-type semiconductor substrate 1 is used as a mask to form a semiconductor in the formation region of the p-channel type MIS FETQp.
  • an n-type impurity phosphorous or arsenic
  • the insulating film 18 is removed, and then, as shown in FIG.
  • the epitaxial semiconductor layer 19b is epitaxially grown.
  • island-shaped insulating film patterns 20 are formed at equal intervals on the semiconductor layer 19b, oxygen ions are formed inside the semiconductor layer 19b using the insulating film pattern 20 as a mask. inject.
  • the island-shaped insulating film pattern 20 is formed, for example, by patterning a silicon oxide film formed on the semiconductor layer 1b.
  • the dimensions and intervals of the insulating film pattern 20 are the same as those of the openings 5 formed in the insulating layer 2 of the SOI substrate used in the first embodiment.
  • the semiconductor substrate 1 is heat-treated to react silicon with oxygen, thereby forming an insulating layer 21 made of silicon oxide on the bottom of the semiconductor layer 19b.
  • the SOI since the insulating layer 21 is not formed in the region below the insulating film pattern 20 where the oxygen ions have not been implanted, the SOI has a structure substantially similar to that of the first embodiment shown in FIG. A substrate is obtained.
  • CMOS gate array may be formed according to the steps shown in FIGS. 9 to 12 of the first embodiment.
  • a fixed potential is supplied to each channel region of the n-channel MIS FETQn and the p-channel MISFETQp constituting the CMOS gate array.
  • a fixed potential may be supplied only to the channel region.
  • the insulating layer 2 formed on the semiconductor substrate 1 is etched to form the opening 5, as shown in FIG. 2 may be removed entirely. In this case, the region from which the insulating layer 2 has been removed does not have an SOI structure. It is possible to form a MIS FET with different characteristics. That is, MIS FETs having different characteristics can be mixed on the same semiconductor substrate 1.
  • the present invention can be applied not only to a CMOS gate array but also to a case where a circuit is constituted only by n-channel MIS FETQn. That is, the present invention can be widely applied to a semiconductor integrated circuit device including a MIS FET formed on an SOI substrate.
  • the semiconductor integrated circuit device of the present invention can suppress the fluctuation of the threshold voltage of the MIS FET formed on the semiconductor layer of the SOI substrate, and can achieve the stable operation of the MIS FET. It is suitable for use in various LSIs using SOI substrates.

Abstract

A semiconductor integrated circuit device having an SOI substrate comprises a p-channel MISFET Qp and an n-channel MISFET Qn formed on the main face of semiconductor layers (3a and 3b) formed over a semiconductor substrate (1) (n well 4) through an insulating layer (2). A hole (5) is bored in the insulating layer (2) below the channel region of each of the p-channel MISFET Qp and n-channel MISFET Qn. Each channel region and the semiconductor substrate (1) (n well 4) are electrically connected together through this hole (5).

Description

明 細 書 半導体集積回路装置およびその製造方法ならびに半導体ウェハ 技術分野  Description: Semiconductor integrated circuit device, method of manufacturing the same, and semiconductor wafer
本発明は、 半導体集積回路装置およびその製造技術に関し、 特に、 S O I (Sil icon On Insulator)構造の半導体集積回路装置に適用して有効な技術に関するも のである。 背景技術  The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a SOI (Silicon On Insulator) structure. Background art
半導体基板上に絶縁層を介して薄い半導体層を形成し この半導体層に素子を 形成する S O I技術は、 完全な素子分離が可能であることから、 単結晶シリコン の基板に半導体素子を形成する場合に比べて次のような利点が得られる。  SOI technology, in which a thin semiconductor layer is formed on a semiconductor substrate via an insulating layer and an element is formed in this semiconductor layer, is capable of complete element isolation. Therefore, when a semiconductor element is formed on a single-crystal silicon substrate, The following advantages are obtained as compared with.
( 1 ) 配線一基板間の寄生容量や拡散層容量が低減されるので、 L S Iの勲作速 度の向上が可能となる。  (1) Since the parasitic capacitance and the diffusion layer capacitance between the wiring and the substrate are reduced, it is possible to improve the operation speed of the LSI.
( 2 ) α線による電子一正孔対の発生が薄い半導体層に限られるので、 ソフトェ ラー耐性が高く、 メモリ素子の微細化に有利である。  (2) Since the generation of electron-hole pairs due to α rays is limited to a thin semiconductor layer, the resistance to software is high, which is advantageous for miniaturization of memory devices.
( 3 ) 寄生パイポーラトランジスタのような能動的寄生効果が低減されるので、 ラッチアップフリーの相補型 M I S F E Tを形成できる。  (3) Since active parasitic effects such as parasitic bipolar transistors are reduced, a latch-up-free complementary MISFET can be formed.
しかしその反面、 S O I技術の問題点として、 半導体層に形成された M I S F E Tのしきい値電圧が変動し易いことが指摘されている。  However, on the other hand, it has been pointed out that a problem with the SOI technology is that the threshold voltage of the MISFET formed on the semiconductor layer is likely to fluctuate.
例えばアイ 'ィ一 'ィ一'ィ一、 トランザクションズ (IEEE Transactions on Electron Devices Vol.38, No.6, June 1991. ρ.1384 ~ p.1391 "Analysis and Oon t rol of Floating -Body Bipolar Effects in Fully Depleted Submicrometer SOI MOSFET's") には、 S O I基板に形成された M I S F E Tのチャネル領域がソー ス領域とドレイン領域とで周囲を囲まれ、 基板からも絶縁分離されてフローティ ング状態になると、 ゲート電圧一ドレイン電流特性にキンク（kink)特性が生じる ために、 しきい値電圧が変動するという事実が報告されている。  For example, I-I-I-I-I-I, Transactions (IEEE Transactions on Electron Devices Vol. 38, No. 6, June 1991. ρ.1384-p.1391 "Analysis and Ontrol of Floating -Body Bipolar Effects In Fully Depleted Submicrometer SOI MOSFET's "), the channel region of the MISFET formed on the SOI substrate is surrounded by the source region and the drain region, and is isolated from the substrate as well. It has been reported that the threshold voltage fluctuates due to the occurrence of a kink characteristic in one drain current characteristic.
従って、 S O I基板に形成された M I S F E Tの安定動作を確保するためには、 M I S FETのチャネル領域がフローティング状態にならないような構造を実現 する必要がある。 Therefore, to ensure stable operation of the MISFET formed on the SOI substrate, It is necessary to realize a structure in which the channel region of the MIS FET does not float.
例えば前述した文献は、 チャネル領域のフローティングを防止する対策として、 半導体層の膜厚を十分に薄く形成し、 ゲート電圧の印加時にチャネル領域を完全 に空乏化させる技術を開示している。  For example, the above-mentioned document discloses a technique for forming a sufficiently thin semiconductor layer and completely depleting the channel region when a gate voltage is applied, as a measure for preventing floating of the channel region.
また、 特開昭 62 - 109355号公報は、 チャネル領域のフローティングを 防止する対策として、 チャネル領域が形成される p型半導体領域に電気的に接続 された第 2の p型半導体領域を nチャネル型 MI S FETのソース、 ドレイン領 域 （n型半導体領域） の端部に形成し、 この第 2の p型半導体領域に固定電位を 印加する技術を開示している。  Japanese Patent Application Laid-Open No. 62-109355 discloses that as a measure for preventing floating of a channel region, a second p-type semiconductor region electrically connected to a p-type semiconductor region where a channel region is formed is an n-channel type. It discloses a technique that is formed at the end of the source / drain region (n-type semiconductor region) of the MIS FET and applies a fixed potential to this second p-type semiconductor region.
しかし、 ゲート電圧の印加時にチャネル領域が完全に空乏化するようになるま で半導体層を薄く形成する第 1の従来技術においては、  However, in the first prior art in which the semiconductor layer is formed thin until the channel region is completely depleted when the gate voltage is applied,
(1) 半導体層に形成されるソース、 ドレイン領域の抵抗値が増大するために、 MI S FETの電流駆動能力が低下する。  (1) The current drive capability of the MIS FET is reduced because the resistance values of the source and drain regions formed in the semiconductor layer increase.
(2) 寄生パイポーラトランジスタ効果が顕在化するために、 しきい値電圧が低 下し、 エンハンスメント型の MI S FETを得ることが困難になる。  (2) Since the parasitic bipolar transistor effect becomes apparent, the threshold voltage drops, making it difficult to obtain an enhancement-type MISFET.
といった問題が生じる。 Such a problem arises.
また、 nチャネル型 MI S FETのソース、 ドレイン領域 （n型半導体領域） の端部に固定電位供給用の P型半導体領域を形成する第 2の従来技術の場合は、 (1) この p型半導体領域を設けた分、 MI S FETの実効的なゲート幅が減少 するために、 電流駆動能力が低下する。  In the case of the second conventional technique in which a P-type semiconductor region for supplying a fixed potential is formed at the end of the source / drain region (n-type semiconductor region) of an n-channel type MIS FET, (1) Since the semiconductor region is provided, the effective gate width of the MIS FET is reduced, so that the current driving capability is reduced.
(2) ソース、 ドレイン領域の接合容量が大きくなるために、 MI S FETの動 作速度が低下する。  (2) The operating speed of the MIS FET decreases because the junction capacitance of the source and drain regions increases.
といった問題が生じる。 Such a problem arises.
本発明の目的は、 S 01基板に形成された MI S FETのしきい値電圧の変動 を防止すると共に、 しきい値電圧をェンハンスメント型に設定することのできる 技術を提供することにある。  An object of the present invention is to provide a technique capable of preventing a threshold voltage of a MIS FET formed on an S01 substrate from fluctuating and setting a threshold voltage to an enhancement type.
本発明の他の目的は、 SO I基板に形成された M I S FETのしきい値電圧の 変動を防止すると共に、 電流駆動能力を向上させることのできる技術を提供する ことにある。 Another object of the present invention is to provide a technique capable of preventing a fluctuation of a threshold voltage of an MIS FET formed on an SOI substrate and improving a current driving capability. It is in.
本発明の前記ならびにその他の目的と新規な特徴は、 明細書の記述および添付 図面から明らかになるであろう。 発明の開示  The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings. Disclosure of the invention
本発明による S O I構造の半導体集積回路装置は、 半導体基板上に絶縁層を介 して形成された半導体層の主面に M I S FETが形成され、 前記 MI S FETの チャネル領域下の前記絶縁層に開孔が設けられ、 前記チャネル領域と前記半導体 基板とが前記開孔を通じて電気的に接続されている。  In a semiconductor integrated circuit device having an SOI structure according to the present invention, an MIS FET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer, and the MIS FET is formed on the insulating layer below a channel region of the MIS FET. An opening is provided, and the channel region and the semiconductor substrate are electrically connected through the opening.
本発明による半導体集積回路装置の製造方法は、 半導体基板の上部に絶縁層を 介して半導体層を形成した SO I構造の基板に MI S FETを形成するにあたり、 The method for manufacturing a semiconductor integrated circuit device according to the present invention includes the steps of: forming a MISFET on a substrate having an SOI structure in which a semiconductor layer is formed on a semiconductor substrate via an insulating layer;
(a) 半導体基板上に絶縁層を形成した後、 前記絶縁層をエッチングして前記半 導体基板に達する複数の開孔を所定の間隔で形成する工程、 (a) forming an insulating layer on a semiconductor substrate, and then etching the insulating layer to form a plurality of openings reaching the semiconductor substrate at predetermined intervals;
( b ) 前記それぞれの開孔の底部に露出した前記半導体基板上に半導体層をェピ タキシャル成長させ、 前記絶縁層の上部の全面を前記半導体層で覆う工程、  (b) epitaxially growing a semiconductor layer on the semiconductor substrate exposed at the bottom of each of the openings, and covering the entire upper surface of the insulating layer with the semiconductor layer;
(c) 前記半導体層を所定の膜厚となるまで薄膜化した後、 前記半導体層の主面 に素子分離用の絶縁膜を形成する工程、  (c) forming the insulating layer for element isolation on the main surface of the semiconductor layer after thinning the semiconductor layer to a predetermined thickness;
(d) 前記半導体層の主面に、 チャネル領域の一部が前記開孔上に配置された M I S FETを形成する工程、  (d) forming a MISFET in which a part of a channel region is arranged on the opening on the main surface of the semiconductor layer;
を合んでいる。 It is.
上記した構成によれば、 絶縁層の開孔を通じて MI S FETのチャネル領域と 半導体基板とを電気的に接続したことにより、 チャネル領域のフローティングに 起因するしきい値電圧の変動が防止されるので、 MI S FETの安定動作を図る ことができる。  According to the configuration described above, since the channel region of the MIS FET is electrically connected to the semiconductor substrate through the opening in the insulating layer, fluctuation of the threshold voltage due to floating of the channel region is prevented. Thus, stable operation of the MIS FET can be achieved.
また、 ゲート電圧の印加時にチャネル領域が完全に空乏化するまで半導体層を 薄くしなくとも、 しきい値電圧の制御を行うことができるので、 ソース、 ドレイ ン領域の抵抗値の増大を防ぎ、 MI S FETの電流駆動能力を向上させることが できる。 さらに、 寄生バイポーラトランジスタ効果の顕在化によるしきい値電圧 の低下を防ぎ、 MI S FETのしきい値電圧をエンハンスメント型に設定するこ とができる。 Also, since the threshold voltage can be controlled without reducing the thickness of the semiconductor layer until the channel region is completely depleted when the gate voltage is applied, the resistance values of the source and drain regions can be prevented from increasing. The current drive capability of the MIS FET can be improved. Furthermore, it is possible to prevent the threshold voltage from being lowered due to the manifestation of the parasitic bipolar transistor effect, and to set the threshold voltage of the MISFET to the enhancement type. Can be.
また、 半導体層の下部の絶縁層に設けた開孔を通じてチャネル領域に固定電位 を供給することができるので、 実効的なゲート幅の減少を防ぎ、 M I S F E Tの 電流駆動能力を向上させることができる。 さらに、 ソース、 ドレイン領域の接合 容量の増大を防ぎ、 M I S F E Tの動作速度を向上させることができる。 図面の簡単な説明  In addition, since a fixed potential can be supplied to the channel region through the opening provided in the insulating layer below the semiconductor layer, a decrease in the effective gate width can be prevented, and the current driving capability of the MISFET can be improved. Further, an increase in the junction capacitance of the source and drain regions can be prevented, and the operating speed of the MISFET can be improved. BRIEF DESCRIPTION OF THE FIGURES
図 1は、 本発明の第 1実施例である半導体集積回路装置を示す S O I基板の要 部平面図、 図 2は、 図 1の II一 ΙΓ 線に沿った断面図、 図 3は、 本発明の第 1実 施例である半導体集積回路装置の製造方法を示す S O I基板の要部断面図、 図 4 は、 本発明の第 1実施例である半導体集積回路装置の製造方法を示す S O I基板 の要部断面図、 図 5は、 本発明の第 1実施例である半導体集積回路装置の製造方 法を示す S O I基板の要部断面図、 図 6は、 本発明の第 1実施例である半導体集 積回路装置の製造方法を示す S O I基板の斜視図、 図 7は、 本発明の第 1実施例 である半導体集積回路装置の製造方法を示す S O I基板の要部断面図、 図 8は、 本発明め第 1実施例である半導体集積回路装置の製造方法を示す S O I基板の要 部断面図、 図 9は、 本発明の第 1実施例である半導体集積回路装置の製造方法を 示す S O I基板の要部断面図、 図 1 0は、 本発明の第 1実施例である半導体集積 回路装置の製造方法を示す S O I基板の要部断面図、 図 1 1は、 本発明の第 1実 施例である半導体集積回路装置の製造方法を示す S O I基板の要部断面図、 図 1 2は、 本発明の第 1実施例である半導体集積回路装置の製造方法を示す S O I基 板の要部断面図、 図 1 3は、 本発明の第 2実施例である半導体集積回路装置の製 造方法を示す S O I基板の要部断面図、 図 1 4は、 本発明の第 2実施例である半 導体集積回路装置の製造方法を示す S 0 I基板の要部断面図、 図 1 5は、 本発明 の第 2実施例である半導体集積回路装置の製造方法を示す S O I基板の要部断面 図、 図 1 6は、 本発明の第 2実施例である半導体集積回路装置の製造方法を示す S O I基板の要部断面図、 図 1 7は、 本発明の他の実施例である半導体集積回路 装置の製造方法を示す S O I基板の要部断面図である。 明を実施するための最良の形態 FIG. 1 is a plan view of a main part of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II in FIG. 1, and FIG. FIG. 4 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 5 is a sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 6 is a sectional view of a semiconductor according to the first embodiment of the present invention. FIG. 7 is a perspective view of an SOI substrate showing a method of manufacturing an integrated circuit device, FIG. 7 is a sectional view of a main part of the SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. FIG. 9 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 10 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. 11 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 12 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a manufacturing method. FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 15 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 15 is a view illustrating a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 16 is a sectional view of a main part of an SOI substrate, and FIG. 16 is an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. Fragmentary cross-sectional view, FIG. 1 7 is a fragmentary cross-sectional view of a SOI substrate showing a method of manufacturing another semiconductor integrated circuit device which is an embodiment of the present invention. Best mode for implementing
本発明をより詳述するために、 添付の図面に従ってこれを説明する。 なお、 実 施例を説明するための全図において、 同一機能を有するものは同一符号を付け、 その繰り返しの説明は省略する。  The present invention will be described in more detail with reference to the accompanying drawings in order to explain it in more detail. In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.
(第 1実施例）  (First embodiment)
本発明の第 1実施例である半導体集積回路装置を図 1、 図 2に示す。 図 1は、 SO I基板の要部平面図、 図 2は、 図 1の II一 ΙΓ 線に沿った断面図である。 本実施例の半導体集積回路装置は、 半導体基板 1と、 この半導体基板 1上に絶 縁層 2を介して形成された半導体層 3 a, 3 bとで構成される SO I基板の主面 上に、 nチャネル型 MI S FETQ nと pチャネル型 MI S FETQpとで構成 される CMOS (Complimentary MOS)回路を形成したものである。  1 and 2 show a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 1 is a plan view of a main part of the SOI substrate, and FIG. 2 is a cross-sectional view taken along line II in FIG. The semiconductor integrated circuit device according to the present embodiment includes a semiconductor substrate 1 and semiconductor layers 3 a and 3 b formed on the semiconductor substrate 1 via an insulating layer 2. In addition, a CMOS (Complimentary MOS) circuit composed of an n-channel MIS FETQn and a p-channel MISFETQp is formed.
半導体基板 1は P型の単結晶シリコン （S i) からなり、 その一部には n型ゥ エル 4が形成されている。 絶縁層 2は多数の開孔 5が等間隔に形成された酸化シ リコン層で構成されている。半導体層 3 aは n-型のェピタキシャル単結晶シリコ ンカ らなり、 その下部の絶縁層 2に形成された開孔 5を通じて n型ゥエル 4と電 気的に接緣されている。半導体層 3 bは p-型のェピタキシャル単結晶シリコンか らなり、 その下部の絶縁層 2に形成された開孔 5を通じて p型の半導体基板 1と 電気的に接続されている。  The semiconductor substrate 1 is made of P-type single-crystal silicon (Si), and an n-type well 4 is formed on a part thereof. The insulating layer 2 is composed of a silicon oxide layer having a large number of openings 5 formed at equal intervals. The semiconductor layer 3a is made of an n-type epitaxial single-crystal silicon, and is electrically connected to the n-type well 4 through an opening 5 formed in the insulating layer 2 thereunder. The semiconductor layer 3b is made of p-type epitaxial single crystal silicon, and is electrically connected to the p-type semiconductor substrate 1 through an opening 5 formed in the insulating layer 2 thereunder.
nチャネル型 MI S FETQnは、 酸化シリコンからなる素子分離用のフィー ルド絶縁膜 6で周囲を囲まれた p-型の半導体層 3 bの活性領域の主面に形成さ れている。 nチャネル型 MI S FETQnは、 半導体層 3 bに形成された n型半 導体領域 （ソース領域、 ドレイン領域） 7と、 半導体層 3 bの表面に形成された 酸化シリコンのゲート絶縁膜 8と、 ゲート絶縁膜 8上に形成された多結晶シリコ ンのゲート電極 9とで構成されている。 このゲート電極 9の直下の半導体層 3 b すなわちチャネル領域は、 前記絶縁層 2の開孔 5を通じて半導体基板 1と電気的 に接続されている。  The n-channel type MISFETQn is formed on the main surface of the active region of the p-type semiconductor layer 3b surrounded by the element isolation field insulating film 6 made of silicon oxide. The n-channel type MIS FETQn includes an n-type semiconductor region (source region, drain region) 7 formed in the semiconductor layer 3 b, a silicon oxide gate insulating film 8 formed on the surface of the semiconductor layer 3 b, A gate electrode 9 made of polycrystalline silicon formed on the gate insulating film 8. The semiconductor layer 3 b immediately below the gate electrode 9, that is, the channel region, is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2.
上記 p-型の半導体層 3 bの別の活性領域には、酸化シリコンの絶縁膜 10に形 成された接続孔 1 1を通じて配線 12が接続され、 〜一 2 V程度の基板電位が供 給される。 この半導体層 3 bは、 前記 nチャネル型 MI S FETQnが形成され た半導体層 3 bと同様、 その下部の絶縁層 2の開孔 5を通じて半導体基板 1と電 気的に接続されている。 A wiring 12 is connected to another active region of the p-type semiconductor layer 3b through a connection hole 11 formed in a silicon oxide insulating film 10, and a substrate potential of about 12 V is supplied. Is done. The semiconductor layer 3b is formed with the n-channel type MIS FETQn. Like the semiconductor layer 3b, the semiconductor layer 1b is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2 thereunder.
このように、 上記 nチャネル型 M I S F E T Q nは、 絶縁層 2の開孔 5を通じ てチャネル領域と半導体基板 1とを電気的に接続し、 このチャネル領域に基板電 位を供給することによって、 チャネル領域のフローティングを防いでいる。 一方、 Pチャネル型 M I S F E T Q pは、 フィールド絶縁膜 6で周囲を囲まれ た IT型の半導体層 3 aの活性領域の主面に形成されている。 pチャネル型 MI S FETQpは、 半導体層 3 aに形成された p型半導体領域 （ソース領域、 ドレイ ン領域） と、 半導体層 3 aの表面に形成されたゲート絶縁膜 8と、 ゲート絶縁膜 8上に形成されたゲート電極 9とで構成されている。 このゲート電極 9の直下の 半導体層 3 aすなわちチャネル領域は、 前記絶縁層 2の開孔 5を通じて n型ゥェ ル 4と電気的に接続されている。  As described above, the n-channel type MISFETQn electrically connects the channel region to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 and supplies a substrate potential to the channel region, thereby forming the channel region. To prevent floating. On the other hand, the P-channel type MISFETQp is formed on the main surface of the active region of the IT type semiconductor layer 3a surrounded by the field insulating film 6. The p-channel type MIS FETQp includes a p-type semiconductor region (source region and drain region) formed in the semiconductor layer 3a, a gate insulating film 8 formed on the surface of the semiconductor layer 3a, and a gate insulating film 8 And a gate electrode 9 formed thereon. The semiconductor layer 3 a immediately below the gate electrode 9, that is, the channel region, is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2.
上記 IT型の半導体層 3 aの別の領域には、絶縁膜 10に形成された接続孔 1 1 を通じて配線 12が接続され、 〜 2 V程度のゥエル電位が供給される。 この半導 体層 3 aは、 前記 pチャネル型 M I S FETQ が形成された半導体層 3 aと同 様、 その下部の絶縁層 2の開孔 5を通じて n型ゥエル 4と電気的に接続されてい る。  A wiring 12 is connected to another region of the IT type semiconductor layer 3 a through a connection hole 11 formed in the insulating film 10, and a gate potential of about 2 V is supplied. The semiconductor layer 3a is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2 below the semiconductor layer 3a, similarly to the semiconductor layer 3a on which the p-channel type MIS FETQ is formed. .
このように、 上記 pチャネル型 MI S FETQpは、 絶縁層 2の開孔 5を通じ てチャネル領域と n型ゥエル 4とを電気的に接続し、 このチャネル領域にゥエル 電位を供給することによって、 チャネル領域のフローティングを防いでいる。 上記のように構成された本実施例によれば、 ゲート電圧の印加時にチャネル領 域が完全に空乏化するまで半導体層 3 a, 3 bを薄くしなくとも、 しきい値電圧 の制御を行うことができるので、 ソース、 ドレイン領域 （n型半導体領域 7、 p 型半導体領域 13) の抵抗値の増大を防ぎ、 nチャネル型 MI S FETQn、 p チャネル型 MI S FETQpのそれぞれの電流駆動能力を向上させることができ る。 さらに、 寄生バイポーラトランジスタ効果の顕在化によるしきい値電圧の低 下 防ぎ、 しきい値電圧をエンハンスメント型に設定することができる。  As described above, the p-channel type MIS FETQp electrically connects the channel region to the n-type well 4 through the opening 5 of the insulating layer 2 and supplies a jewel potential to the channel region, thereby forming a channel. This prevents the area from floating. According to the present embodiment configured as described above, the threshold voltage is controlled without reducing the thickness of the semiconductor layers 3a and 3b until the channel region is completely depleted when the gate voltage is applied. The resistance of the source and drain regions (n-type semiconductor region 7 and p-type semiconductor region 13) is prevented from increasing, and the current drive capability of each of the n-channel MIS FETQn and p-channel MIS FETQp Can be improved. Further, the threshold voltage can be prevented from lowering due to the manifestation of the parasitic bipolar transistor effect, and the threshold voltage can be set to an enhancement type.
また、 本実施例によれば、 半導体層 3 a， 3 bの下部の絶縁層 2の開孔 5を通 じてチャネル領域に固定電位を供給するので、 実効的なゲート幅の減少を防ぎ、 nチャネル型 M I S F E T Q n、 pチャネル型 M I S FETQpのそれぞれの電 流駆動能力を向上させることができる。 さらに、 ソース、 ドレイン領域 （n型半 導体領域 7、 p型半導体領域 13) の接合容量の増大を防ぎ、 動作速度を向上さ せることができる。 Further, according to the present embodiment, a fixed potential is supplied to the channel region through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b. The current drive capability of each of the n-channel MISFETQn and the p-channel MISFETQp can be improved. Further, it is possible to prevent an increase in the junction capacitance of the source and drain regions (the n-type semiconductor region 7 and the p-type semiconductor region 13), thereby improving the operation speed.
また、 本実施例によれば、 nチャネル型 M I S FETQn、 pチャネル型 MI S FETQpの動作時に発生する熱を半導体層 3 a， 3 bの下部の絶縁層 2の開 孔 5を通じて半導体基板 1に逃がすことができるので、 S O I基板の放熱性を向 上させることができる。  Further, according to the present embodiment, the heat generated during the operation of the n-channel MIS FETQn and the p-channel MIS FETQp is transferred to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b. Since the heat can escape, the heat dissipation of the SOI substrate can be improved.
次に、 図 3〜図 12を用いて本実施例の CMOSゲートアレイの製造方法を説 明する。  Next, a method of manufacturing the CMOS gate array according to the present embodiment will be described with reference to FIGS.
まず、 図 3に示すように、 p型の半導体基板 1を熱処理してその表面に酸化シ リコンの絶縁層 2を形成した後、 図 4に示すように、 絶縁層 2およびフォトレジ スト 15をマスクにして pチャネル型 M I S FETQpの形成領域の半導体基板 1に n型の不純物 （リンまたはヒ素） を打ち込み、 n型ゥエル 4を形成する p 次に、 フォトレジスト 15を除去した後、 図 5に示すように、 新たなフオトレ ジスト 16をマスクにして絶縁層 2をドライエッチングすることにより、 半導体 基板 1に達する開孔 5と n型ゥエル 4に達する開孔 5とを形成する。  First, as shown in FIG. 3, after heat-treating the p-type semiconductor substrate 1 to form an insulating layer 2 of silicon oxide on the surface thereof, as shown in FIG. 4, the insulating layer 2 and the photoresist 15 are formed. Implant an n-type impurity (phosphorous or arsenic) into the semiconductor substrate 1 in the formation region of the p-channel MIS FET Qp as a mask to form an n-type well 4 p. Next, after removing the photoresist 15, see FIG. As shown, by dry-etching the insulating layer 2 using the new photoresist 16 as a mask, an opening 5 reaching the semiconductor substrate 1 and an opening 5 reaching the n-type well 4 are formed.
図 6に示すように、 上記開孔 5は、 絶縁層 2の主面の互いに直交する方向に沿 つて等間隔に形成する。 開孔 5は、 その径が M I S FETのゲ一ト電極のゲ一ト 長よりも小さくなるように形成する。 また、 本実施例では、 MI S FETのチヤ ネル領域の下に少なくとも 1個の開孔 5が配置されるので、 互いに瞵接する開孔 5の間隔は、 ゲート長方向に沿って互いに瞵接する M I S FETのゲート電極の 間隔の lZn (nは自然数） となるように設定する。  As shown in FIG. 6, the openings 5 are formed at equal intervals along directions orthogonal to each other on the main surface of the insulating layer 2. The opening 5 is formed such that its diameter is smaller than the gate length of the gate electrode of the MISFET. Further, in the present embodiment, since at least one opening 5 is arranged under the channel region of the MIS FET, the interval between the openings 5 that are in contact with each other is smaller than the MIS that is in contact with each other along the gate length direction. It is set to be lZn (n is a natural number) of the interval between the gate electrodes of the FET.
次に、 フォトレジスト 15を除去した後、 図 7に示すように、 開孔 5の底部に 露出した半導体基板 1と n型ゥエル 4のそれぞれの表面に ρ·型の半導体層 3 b を選択的にェピタキシャル成長させる。 半導体層 3 bは、 それぞれの開孔 5を通 じて成長した半導体層 3 b同士が絶縁層 2の上部で互いにつながり合って、 絶縁 層 2の全面を覆うようになるまで成長させる。  Next, after removing the photoresist 15, as shown in FIG. 7, a ρ-type semiconductor layer 3b is selectively formed on each surface of the semiconductor substrate 1 and the n-type well 4 exposed at the bottom of the opening 5. Epitaxial growth. The semiconductor layer 3 b is grown until the semiconductor layers 3 b grown through the respective openings 5 are connected to each other at the upper part of the insulating layer 2 so as to cover the entire surface of the insulating layer 2.
次に、 図 8に示すように、半導体層 3 bを CMP (Chemical Mechanical Polishi ng;化学的機械研磨)法あるいはエッチバックで薄膜化すると共に、その表面を平 坦化する。 この半導体層 3 bは、 少なくともゲート電圧の印加時にチャネル領域 が完全に空乏化しない程度の膜厚を有するものとする。 Next, as shown in FIG. 8, the semiconductor layer 3b is removed by CMP (Chemical Mechanical Polishing). (ng; chemical mechanical polishing) method or etch back, and the surface is flattened. The semiconductor layer 3b has a thickness at least such that the channel region is not completely depleted when a gate voltage is applied.
次に、 図 9に示すように、 フォトレジスト 17をマスクにして pチャネル型 M I S FETQpの形成領域の半導体層 3 bに n型の不純物 (リンまたはヒ素） を 打ち込み、 n型ゥエル 4の上部に η·型の半導体層 3 aを形成する。  Next, as shown in FIG. 9, an n-type impurity (phosphorous or arsenic) is implanted into the semiconductor layer 3 b in the region where the p-channel MIS FET Qp is formed using the photoresist 17 as a mask. An η-type semiconductor layer 3a is formed.
次に、 フォトレジスト 17を除去した後、 図 10に示すように、 半導体層 3 a， 3 bのそれぞれの表面に素子分離用の厚いフィ一ルド絶縁膜 6とゲ一ト絶縁膜 8 とを形成した後、 図 1 1に示すように、 CVD法で堆積した多結晶シリコン膜を パターユングすることにより、 半導体層 3 a, 3 bのそれぞれのゲート絶縁膜 8 上にゲート電極 9を形成する。  Next, after removing the photoresist 17, as shown in FIG. 10, a thick field insulating film 6 for device isolation and a gate insulating film 8 are formed on each surface of the semiconductor layers 3a and 3b. After formation, the gate electrode 9 is formed on the gate insulating film 8 of each of the semiconductor layers 3a and 3b by patterning the polycrystalline silicon film deposited by the CVD method as shown in FIG. .
次に、 図 12に示すように、 半導体層 3 aに p型の不純物 （ホウ素） を打ち込 んで Pチャネル型 MI S FETQpのソース、 ドレイン領域 （p型半導体領域 1 3) を形成し、 半導体層 3 bに n型の不純物 （リンまたはヒ素） を打ち込んで n チャネル型 MI S FETQnのソース、 ドレイン領域 （n型半導体領域 7) を形 成する。  Next, as shown in FIG. 12, a p-type impurity (boron) is implanted into the semiconductor layer 3a to form a source / drain region (p-type semiconductor region 13) of the P-channel type MIS FET Qp. By implanting an n-type impurity (phosphorus or arsenic) into layer 3b, a source / drain region (n-type semiconductor region 7) of n-channel type MIS FETQn is formed.
その後、 nチャネル型 MI S FETQn、 pチャネル型 M I S F E T Q pのそ れぞれの上部に C VD法で酸化シリコンの絶縁膜 10を堆積した後、 この絶縁膜 10に形成した接続孔 1 1を通じて pチャネル型 M I S FETQpのソース、 ド レイン領域 （p型半導体領域 13) 、 πチャネル型 MI S FETQnのソース、 ドレイン領域 （n型半導体領域 7) のそれぞれに配線 12を接続すると共に、 別 の領域の半導体層 3 aにゥエル電位供給用の配線 12を、 別の領域の半導体層 3 bに基板電位供給用の配線 12をそれぞれ接続することにより、 前記図 1、 図 2 に示す CMO S回路が完成する。  After that, an insulating film 10 of silicon oxide is deposited on each of the n-channel type MISFETQn and the p-channel type MISFETQp by the CVD method. The wiring 12 is connected to each of the source and drain region (p-type semiconductor region 13) of the channel type MIS FETQp and the source and drain region (n-type semiconductor region 7) of the π-channel type MIS FETQn. The CMOS circuit shown in FIGS. 1 and 2 is completed by connecting the wiring 12 for supplying the gate potential to the semiconductor layer 3a and the wiring 12 for supplying the substrate potential to the semiconductor layer 3b in another region. I do.
(第 2実施例）  (Second embodiment)
前記第 1実施例では、 半導体基板 1、 絶縁層 2、 ェピタキシャルシリコン単結 晶からなる半導体層 3 a, 3 bで構成された SO I基板を用いた場合について説 明したが、 シリコン単結晶からなる半導体基板 1の内部に酸素イオンを打ち込ん だ後、 半導体基板 1を熱処理してその内部に酸化シリコンの絶縁層を形成する、 いわゆる S I OX(Separation by Implanted Oxygen)法で得られる S O I基板 を用いることもできる。 In the first embodiment, the case where the SOI substrate composed of the semiconductor substrate 1, the insulating layer 2, and the semiconductor layers 3a and 3b made of epitaxial silicon single crystal was used was described. After implanting oxygen ions into the semiconductor substrate 1 made of, the semiconductor substrate 1 is heat-treated to form a silicon oxide insulating layer therein. An SOI substrate obtained by a so-called SI OX (Separation by Implanted Oxygen) method can also be used.
この場合は、 まず図 13に示すように、 p型の半導体基板 1上に形成した酸化 シリコンなどの絶縁膜 （またはフォトレジスト） 18をマスクにして、 pチヤネ ル型 M I S FETQpの形成領域の半導体基板 1に n型の不純物 （リンまたはヒ 素） を打ち込んで n型ゥエル 4を形成した後、 絶縁膜 18を除去し、 続いて図 1 4に示すように、半導体基板 1の全面に p-型の半導体層 19 bをェピタキシャル 成長させる。  In this case, first, as shown in FIG. 13, the insulating film (or photoresist) 18 of silicon oxide or the like formed on the p-type semiconductor substrate 1 is used as a mask to form a semiconductor in the formation region of the p-channel type MIS FETQp. After an n-type impurity (phosphorous or arsenic) is implanted into the substrate 1 to form an n-type well 4, the insulating film 18 is removed, and then, as shown in FIG. The epitaxial semiconductor layer 19b is epitaxially grown.
次に、 図 15に示すように、 半導体層 19 b上に島状の絶縁膜パターン 20を 等間隔に形成した後、 この絶縁膜パターン 20をマスクにして半導体層 19 bの 内部に酸素イオンを注入する。 島状の絶縁膜パターン 20は、 例えば半導体層 1 b上に形成した酸化シリコン膜をパターユングして形成する。 この絶縁膜パタ —ン 20の寸法および間隔は、 前記第 1実施例で用いた S O I基板の絶縁層 2に 形成した開孔 5のそれと同じにする。  Next, as shown in FIG. 15, after island-shaped insulating film patterns 20 are formed at equal intervals on the semiconductor layer 19b, oxygen ions are formed inside the semiconductor layer 19b using the insulating film pattern 20 as a mask. inject. The island-shaped insulating film pattern 20 is formed, for example, by patterning a silicon oxide film formed on the semiconductor layer 1b. The dimensions and intervals of the insulating film pattern 20 are the same as those of the openings 5 formed in the insulating layer 2 of the SOI substrate used in the first embodiment.
次に、 絶緣膜パターン 20を除去した後、 図 16に示すように、 半導体基板 1 を熱処理してシリコンと酸素とを反応させることにより、 半導体層 19 bの底部 に酸化シリコンからなる絶縁層 21を形成する。 このとき、 絶縁膜パターン 20 の下方の酸素イオンが注入されなかった領域には、 絶縁層 2 1が形成されないの で、 前記第 1実施例の図 8に示すものとほぼ同様の構造を有する S O I基板が得 られる。  Next, after the insulating film pattern 20 is removed, as shown in FIG. 16, the semiconductor substrate 1 is heat-treated to react silicon with oxygen, thereby forming an insulating layer 21 made of silicon oxide on the bottom of the semiconductor layer 19b. To form At this time, since the insulating layer 21 is not formed in the region below the insulating film pattern 20 where the oxygen ions have not been implanted, the SOI has a structure substantially similar to that of the first embodiment shown in FIG. A substrate is obtained.
その後は、 前記第 1実施例の図 9〜図 12に示す工程に従って CMO Sゲート アレイを形成すればよい。  Thereafter, a CMOS gate array may be formed according to the steps shown in FIGS. 9 to 12 of the first embodiment.
以上、 本発明者によってなされた発明を実施例に基づき具体的に説明したが、 本発明は前記第 1実施例、 第 2実施例に限定されるものではなく、 その要旨を逸 脱しない範囲で種々変更可能であることはいうまでもない。  As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first embodiment and the second embodiment, and a scope that does not depart from the gist of the invention is described. It goes without saying that various changes can be made.
前記第 1、 第 2実施例では、 CMOSゲートアレイを構成する nチャネル型 M I S FETQn、 pチャネル型 MI S F E T Q pのそれぞれのチャネル領域に固 定電位を供給したが、 例えば nチャネル型 MI S FETQnのチャネル領域のみ に固定電位を供給するようにしてもよい。 また、 前記第 1実施例において、 半導体基板 1上に形成した絶縁層 2をエッチ ングして開孔 5を形成する際、 図 17に示すように、 半導体基板 1の一部の領域 の絶縁層 2を全部除去してもよい。 このようにすると、 絶縁層 2を除去した領域 は S O I構造とはならないので、 この領域の半導体基板 1上にェピタキシャル成 長させた半導体層 3 b上に、 S O I基板上に形成される M I S F ETとは特性が 異なる MI S FETを形成することができる。 つまり、 同一の半導体基板 1上に 異なる特性の MI S FETを混在させることができる。 In the first and second embodiments, a fixed potential is supplied to each channel region of the n-channel MIS FETQn and the p-channel MISFETQp constituting the CMOS gate array. A fixed potential may be supplied only to the channel region. In the first embodiment, when the insulating layer 2 formed on the semiconductor substrate 1 is etched to form the opening 5, as shown in FIG. 2 may be removed entirely. In this case, the region from which the insulating layer 2 has been removed does not have an SOI structure. It is possible to form a MIS FET with different characteristics. That is, MIS FETs having different characteristics can be mixed on the same semiconductor substrate 1.
本発明は CMOSゲートアレイのみならず、 nチャネル型 MI S FETQnだ けで回路を構成するような場合にも適用することができる。 すなわち、 本発明は、 SO I基板上に形成した MI S FETで構成される半導体集積回路装置に広く適 用することができる。 産業上の利用可能性  The present invention can be applied not only to a CMOS gate array but also to a case where a circuit is constituted only by n-channel MIS FETQn. That is, the present invention can be widely applied to a semiconductor integrated circuit device including a MIS FET formed on an SOI substrate. Industrial applicability
以上のように、 本発明の半導体集積回路装置は、 SO I基板の半導体層に形成 された MI S FETのしきい値電圧の変動を抑制し、 MI S FETの安定動作を 図ることができるので、 SO I基板を使用する各種 LS Iに用いて好適なもので ある。  As described above, the semiconductor integrated circuit device of the present invention can suppress the fluctuation of the threshold voltage of the MIS FET formed on the semiconductor layer of the SOI substrate, and can achieve the stable operation of the MIS FET. It is suitable for use in various LSIs using SOI substrates.

Claims

請 求 の 範 囲 The scope of the claims
1. 半導体基板上に絶縁層を介して形成された半導体層の主面に MI S FETが 形成された半導体集積回路装置であって、 前記 MI S FETのチャネル領域下の 前記絶緑層に開孔が設けられ、 前記チャネル領域と前記半導体基板とが前記開孔 を通じて電気的に接続されていることを特徴とする半導体集積回路装置。 1. A semiconductor integrated circuit device in which a MIS FET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer, wherein the MIS FET is formed in the green layer below a channel region of the MIS FET. A semiconductor integrated circuit device, wherein a hole is provided, and the channel region and the semiconductor substrate are electrically connected through the opening.
2. 請求項 1記載の半導体集積回路装置であって、 前記絶縁層には、 前記開孔が 互いに等しい間隔で設けられていることを特徴とする半導体集積回路装置。  2. The semiconductor integrated circuit device according to claim 1, wherein the openings are provided at equal intervals in the insulating layer.
3. 請求項 1記載の半導体集積回路装置であって、 前記半導体基板には、 前記 M I S FETが形成されていない領域の前記半導体層とその下の前記絶縁層に設け られた前記開孔とを通じて固定電位が供給されることを特徴とする半導体集積回  3. The semiconductor integrated circuit device according to claim 1, wherein, in the semiconductor substrate, the semiconductor layer is formed in a region where the MIS FET is not formed and through the opening provided in the insulating layer below the semiconductor layer. A semiconductor integrated circuit characterized in that a fixed potential is supplied.
4. 請求項 1記載の半導体集積回路装置であって、 互いに隣接する開孔同士の間 隔は、 ゲート長方向に沿って互いに隣接する M I S FETのゲート電極同： tの間 隔の lZn (nは自然数） に設定されていることを特徴とする半導体集積回路装 置。 4. The semiconductor integrated circuit device according to claim 1, wherein the distance between the openings adjacent to each other is the same as that of the gate electrodes of the MIS FETs adjacent to each other along the gate length direction: lZn (n Is a natural number).
5. 請求項 1記載の半導体集積回路装置であって、 前記半導体層の第 1の領域に は nチャネル型 M I S F E Tが形成され、 前記半導体層の第 2の領域には pチヤ ネル型 MI S FETが形成されていることを特徴とする半導体集積回路装置。  5. The semiconductor integrated circuit device according to claim 1, wherein an n-channel MISFET is formed in a first region of the semiconductor layer, and a p-channel MISFET is formed in a second region of the semiconductor layer. Wherein the semiconductor integrated circuit device is formed.
6. 請求項 5記載の半導体集積回路装置であって、 前記 nチャネル型 MI S FE T、 ρチャネル型 M I S FETのそれぞれのソース、 ドレイン領域は、 それらの 底部が前記絶縁層に接していることを特徴とする半導体集積回路装置。  6. The semiconductor integrated circuit device according to claim 5, wherein each of the source and drain regions of the n-channel MISFET and the ρ-channel MISFET has a bottom part in contact with the insulating layer. A semiconductor integrated circuit device characterized by the above-mentioned.
7. 半導体基板上に絶縁層を介して形成した半導体層の主面に MI S FETを形 成する半導体集積回路装置の製造方法であって、  7. A method for manufacturing a semiconductor integrated circuit device in which a MIS FET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer,
(a) 半導体基板上に絶縁層を形成した後、 前記絶縁層をエッチングして前記半 導体基板に達する複数の開孔を所定の間隔で形成する工程、  (a) forming an insulating layer on a semiconductor substrate, and then etching the insulating layer to form a plurality of openings reaching the semiconductor substrate at predetermined intervals;
( b ) 前記それぞれの開孔の底部に露出した前記半導体基板上に半導体層をェピ タキシャル成長させ、 前記絶縁層の上部の全面を前記半導体層で覆う工程、 (b) epitaxially growing a semiconductor layer on the semiconductor substrate exposed at the bottom of each of the openings, and covering the entire upper surface of the insulating layer with the semiconductor layer;
(c) 前記半導体層を所定の膜厚となるまで薄膜化した後、 前記半導体層の主面 に素子分離用の絶縁膜を形成する工程、 (c) after thinning the semiconductor layer to a predetermined thickness, the main surface of the semiconductor layer Forming an insulating film for element isolation in
(d) 前記半導体層の主面に、 チャネル領域の一部が前記開孔上に配置された M I S FETを形成する工程、  (d) forming a MISFET in which a part of a channel region is arranged on the opening on the main surface of the semiconductor layer;
を舍むことを特徴とする半導体集積回路装置の製造方法。 A method of manufacturing a semiconductor integrated circuit device.
8. 内部に絶縁層が形成されたシリコン基板の主面に MI S FETを形成する半 導体集積回路装置の製造方法であつて、 8. A method of manufacturing a semiconductor integrated circuit device in which a MIS FET is formed on a main surface of a silicon substrate having an insulating layer formed therein,
(a) シリコン基板上に所定の間隔で離間された島状のパターンを形成した後、 前記島状のパターンをマスクにして前記シリコン基板に酸素イオンを注入するェ 程、  (a) forming island-shaped patterns spaced at predetermined intervals on a silicon substrate, and then implanting oxygen ions into the silicon substrate using the island-shaped patterns as a mask;
(b) 前記シリコン基板を熱処理してシリコンと酸素とを反応させることにより、 前記島状のパターン下の領域を除く前記シリコン基板の内部に酸化シリコン層を 形成する工程、  (b) forming a silicon oxide layer inside the silicon substrate except for a region under the island-shaped pattern by heat-treating the silicon substrate to react silicon with oxygen;
(c) 前記シリコン基板の主面に素子分離用の絶縁膜を形成した後、 前記シリコ ン基板の主面に、 チャネル領域の一部が前記酸化シリコン層が形成されていない 領域上に配置された M I S F E Tを形成する工程、  (c) After forming an insulating film for element isolation on the main surface of the silicon substrate, a part of the channel region is disposed on a region where the silicon oxide layer is not formed on the main surface of the silicon substrate. Forming a MISFET,
を舍むことを特徴とする半導体集積回路装置の製造方法。 A method of manufacturing a semiconductor integrated circuit device.
9. 半導体基板上に絶縁層を介して半導体層が形成された S O I構造の半導体ゥ ェハであって、 前記絶縁層に所定の間隔で開孔が形成され、 前記それぞれの開孔 の内部を舍む前記絶縁層の上部に前記半導体層が形成されていることを特徴とす る半導体ウェハ。  9. A semiconductor wafer having an SOI structure in which a semiconductor layer is formed on a semiconductor substrate via an insulating layer, wherein openings are formed at predetermined intervals in the insulating layer, and the inside of each of the openings is formed. A semiconductor wafer, wherein the semiconductor layer is formed on the insulating layer.
10. 請求項 9記載の半導体ウェハであって、 前記半導体基板の一部の領域には、 前記絶縁層が形成されていないことを特徴とする半導体ウェハ。  10. The semiconductor wafer according to claim 9, wherein the insulating layer is not formed in a partial region of the semiconductor substrate.
PCT/JP1996/000940 1995-06-12 1996-04-05 Semiconductor integrated circuit device, production thereof, and semiconductor wafer WO1996042112A1 (en)

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