WO1998003978A1

WO1998003978A1 - Reference apparatus, reference level setting method, self-diagnosis method and nonvolatile semiconductor memory

Info

Publication number: WO1998003978A1
Application number: PCT/JP1997/002269
Authority: WO
Inventors: Nobuyoshi Takeuchi
Original assignee: Nkk Corporation
Priority date: 1996-07-18
Filing date: 1997-07-01
Publication date: 1998-01-29

Abstract

A reference apparatus capable of handling the multi-level data while establishing sufficient correlation with memory cells, without increasing the area of the circuits. The reference apparatus is provided with a pluraltiy of reference cells sets each of which comprises a reference cell having a gate coupling ratio smaller than that of the memory cells, and a reference cell having a gate coupling ratio larger than that of the memory cells. The reference cells sets are programmed according to the number of pulses which is an integral multiple of the number of program pulses fed to the memory cells or according to the time that corresponds to the number of pulses, whereby a reference level is set.

Description

. Specification

Reference mounting method, reference level setting method, self-diagnosis method, and nonvolatile semiconductor memory device

Technical field

The present invention relates to a semiconductor device, in particular ^{EP ROM, E '2 P ROM} , reference device and its's Reference level setting for data references in the nonvolatile memory device such as a hula Sshumemo Li. In addition, the present invention relates to a self-diagnosis method using the reference device, and further relates to a nonvolatile semiconductor memory device including the reference device.

Background art

In non-volatile memory devices such as EP ROM, E ² P ROM, flash memory, etc., it is necessary to judge whether the memory cell is “0” or “1”. This is done by comparing the output with a sense amplifier.

Such a reference cell is generally made of the same type as the memory cell in order to represent the characteristics of the memory cell. For example, U.S. Pat. Nos. 4,223,394 describe an isomorphic reference cell in an EPROM. By the way, in recent years, multi-valued memory has become an issue as a technique for increasing memory integration. Has become. Here, multi-value is not “0” or “1” but “0”,

It means that it has 2 ⁿ (n> 1) states like four values of “0.33”, “0.66”, and “1”.

Conventionally, in order to determine such multi-valued information, the voltage applied to the reference cell is multi-staged, the output is multi-valued, or a plurality of sense amplifiers having different sense ratios are prepared, and the sense amplifier is operated according to the output. A method has been proposed to support multi-leveling by using different methods. However, in the case of responding to multi-leveling by the above-described method, the circuit itself becomes complicated and the circuit area increases. In addition, the setting of multi-leveling is not a reference cell itself, but a so-called reference. The problem is that the correlation with the memory cell becomes difficult because the external environment of the reference cell is changed.

The present invention has been made in view of the above circumstances, and a reference device and a reference level setting thereof capable of coping with multi-leveling without increasing a circuit area and sufficiently correlating with a memory cell. The task is to provide a method.

Disclosure of the invention

In order to solve the above-mentioned problems, the present invention provides a reference cell set including a reference cell having a gate power ripple ratio smaller than that of a memory cell and a reference cell having a gate coupling ratio larger than that of the memory cell. To provide a reference device characterized by having a plurality of

Further, according to the present invention, in the above reference device, two reference cells constituting each reference cell set may have a gate power ratio of ± 0.5 to 7.0 with respect to a gate power ratio of a memory cell. Providing a reference device with a gate couple ratio of

The present invention provides a reference device having a plurality of reference cell sets each including a reference cell having a gate couple ratio smaller than a memory cell and a reference cell having a gate coupling ratio larger than the memory cell. A method for setting a reference level, wherein the reference cell set is programmed and set to a reference level only when the number of Hals is an integral multiple of a program pulse for a memory cell or at a time corresponding thereto. Provides a reference level setting method. _The present invention also provides a reference cell including a plurality of reference cell sets each including a reference cell having a gate couple ratio smaller than that of a memory cell and a reference cell having a gate coupling ratio larger than that of the memory cell. A self-diagnosis method for a memory device, wherein the memory cell and the reference cell are simultaneously programmed or erased, and a threshold of the memory cell is compared with a threshold of a reference cell to determine Providing a self-diagnosis method characterized by confirming that a cell threshold value is between the reference cell threshold values.

Further, the present invention includes a memory cell, a reference cell having a smaller gate power ruffle ratio than the memory cell, and a reference cell having a larger gate power ruffle ratio than the memory cell. ₂ to provide a non-volatile semi-conductor memory device characterized by comprising a's Reference device having a plurality of re files Rensuseruse' DOO

In the present invention, a multi-valued reference cell set including a reference cell having a gate couple ratio smaller than that of a memory cell and a reference cell having a gate couple ratio larger than the memory cell is used. The _{three reference} cell sets prepared for each level are programmed according to the number of multi-levels, using pulses that are an integral multiple of the number of voltage pulses used to program the memory cells. As described above, each reference cell set is set so as to maintain the margin of each level according to the number of pulses and also have a margin corresponding to the multilevel level. The specified level will always be at the point where the memory cell was pulsed. Therefore, without increasing the circuit area, it is possible to cope with multi-leveling while sufficiently correlating with the memory cell.

BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a diagram showing a nonvolatile memory circuit including a cell array and a reference device according to an embodiment of the present invention.

Figure 2 shows the program characteristics of the memory cell and each reference cell.

FIG. 3 is a diagram showing program characteristics of a memory cell and each reference cell when a multi-level level setting reverse to that of FIG. 2 is performed.

4, _c Figure 5 A and 5 B is a cross-sectional view showing an example of Jozo memory cell used in the present invention is a diagram showing an example in which occupies different Getokatsupuru ratio of the reference cell.

FIG. 6 is a plan view showing another example of the structure of the memory cell and the reference cell used in the present invention.

FIG. 7 is a cross-sectional view taken along the line XX ′ of FIG.

FIG. 8 is a sectional view taken along line YY ′ of FIG.

FIG. 9 is a schematic diagram showing another example of the structure of the reference cell used in the present invention.

FIGS. 10A and 10B are plan views showing the reference cell shown in FIG. 9, respectively.

FIGS. 11A and 11B are plan views each showing another example of the reference cell.

FIG. 12 is a diagram showing an example of a specific nonvolatile memory circuit using the reference device of the present invention.

FIG. 13 is a diagram showing another example of a specific nonvolatile memory circuit using the reference device of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be specifically described. FIG. 1 is a diagram showing a nonvolatile memory circuit including a cell array and a reference device according to an embodiment of the present invention.

The cell array 1 has a plurality of memory cells 2, each of which is connected to a reference selection circuit 4 via a sense amplifier 3. The reference selection / selection circuit 4 has a plurality of reference cell sets 5 ₂ , 5, 5, 5 ₂ , 5, and 5, according to the levels R, R ₂ , R, of multi-level quantization. The reference cell set is composed of a reference cell having a smaller gate coupling ratio than a memory cell and a reference cell having a larger gate coupling ratio than the memory cell.

Program each reference cell set according to the level of multi-leveling using a pulse that is an integral multiple of the voltage pulse that programs the memory cell.

Figure 2 shows the program characteristics of memory cells and each reference cell, with the number of pulses (logarithm) on the horizontal axis and the threshold value on the vertical axis. This shows the program characteristics of EPROM. As shown in this figure, the threshold value of notes Riseru is between Li off Arensuseruse' bets 5, the threshold value of each re fa Rensuseru of ~ 5 _n. Then, if the difference between the number of program pulses or the total program time is sufficiently large, the reference levels at each pulse number can be made not to overlap:

It should be noted that the characteristics are not limited to the flash EPROM by the Fauula-Nordheim tunnel electron injection, and other programming methods such as hot carrier injection have similar characteristics.

From the above,

(1) An integer multiple of the number of program pulses of the memory cell, or a time program equivalent to that, must be programmed for a certain period of time. Determine the reference level for the cell set.

(2) Apply a program pulse to the memory cell according to the multi-level level and program the memory cell.

(3) Next, select an appropriate reference cell set and check whether the memory cell is within the reference level.

It can be understood that the multi-value determination can be performed by the following procedure.

As shown in Fig. 3, it is also possible to set a multi-level level opposite to that of Fig. 2 by extracting electrons from the high threshold voltage through the Fowler-Nordheim tunneling electron. Next, the memory cell and reference cell set Explain the relationship with the program and the program time.

A problem arises when the gate coupling ratio (hereinafter abbreviated as the “kapple ratio”) of the reference cell set is too different from that of the memory cell. If it is small, the threshold change will be slow. For this reason, the memory cell must have a threshold between each reference cell in the reference cell set; an overlap with other multi-levels; and a reference level. It is necessary to consider the margin of the bezel, that is, the threshold width that can absorb the program variation of the memory array. In addition, the number of multilevel levels ( ²ⁿ ) also becomes a problem.

Considering the above, the difference between the two reference cells that make up each reference cell set is within ± 0.5 to ± 7.0% of the memory cell couple ratio. It is desirable that the magnitude ratio of the reference ratio of the reference cells in each set is not necessarily symmetric. In other words, if one of the reference cells is + 3%, the force ripple ratio of the other reference cell does not have to be 1: 1 :.

Regarding the program time, as shown in Fig. 2, _? Because there is a reversal area, the use of the initial area must be avoided. The threshold inversion region occurs because the initial threshold is low and the program speed is high when the coupling ratio is large, but the initial threshold is high and the program speed is low when the force-pull ratio is low. is there. This reversal area tunnel oxide thickness and applied electric -: it also affects the like, generally of the order one number mu sec from the initial state then, the _c generally describing a self-diagnosis function of the reference apparatus of the present invention The proof of writing or erasing is made by comparison with the reference level. At this time, the reference level is a specific value.

On the other hand, there is a problem of how to set a certain memory cell to an arbitrary value. That is, in the prior art, to prepare an arbitrary reference level, the number of reference cells セル the reference setting voltage becomes enormous. To meet such demands, the reference device of the present invention may be configured as follows.

The memory cell and the reference set of the present invention are programmed or erased at the same time, and the threshold value of the memory cell is changed by an arbitrary number of pulses, and then the verify operation is performed. Can be.

Furthermore, if the reference cell set is normal and the verification fails in the above verification, the characteristics of the memory cell are found to be abnormal. This is because the threshold value of the memory cell must be within the threshold width of the reference cell set.

That is, if the present invention is used,

(1) Arbitrary threshold setting and self-diagnosis, and

(2) Two self-diagnoses can be performed: abnormal cell characteristics and normal self-diagnosis.

The second self-diagnosis is a self-diagnosis of threshold change abnormalities in the form of a conventional bit. The present invention is characterized in that it can be performed on a one-to-one basis with the memory cell to be diagnosed. The first optional threshold setting and self-diagnosis are the effects unique to the present invention.

The self-diagnosis function of the present invention will be described in more detail. In conventional EPROM ゃ flash memory, the threshold value after programming or erasing is compared with the threshold value of the reference cell to confirm that the cell has been programmed or erased. More specifically,

@ 1: A voltage V1 is applied to the gate of the reference cell, and the output of the memory cell should be lower than the output of the reference cell at that time; and

@ 2: When the voltage V 2 (> V 1) is applied to the gate of the reference cell and the output of the memory cell is higher than the output of the reference cell at that time

The threshold of the memory cell is checked. Therefore, the output component when a voltage V such that VI <V <V2 is applied is a margin. Thus, in the conventional method, the level at which the change in the threshold value of the memory cell is confirmed is determined. And it is difficult to set it to any value.

On the other hand, according to the present invention, there are two cells in the reference cell set, one of which has a smaller gate cut ratio than the memory cell, the other has a larger size than the memory cell. The transistor characteristics of the and reference cells are similar except for the gate couple ratio. Therefore, if a memory cell and the reference cell set have the same initial state, and if they are programmed or erased simultaneously, the threshold value of the memory cell will always fall between the threshold values of the cells in the reference cell set. This means that the programming and erasing speed depends only on the gate-cable ratio if other parameters are common, and the gate voltage of the programming and erasing on the memory device to avoid complexity. Are commonly used for memory cells and reference cells. Or

Therefore, according to the present invention, the memory cell and the reference cell set are programmed or erased only at an arbitrary time, and the threshold value of the memory cell is compared with the threshold value of the reference cell set. It can be confirmed that the threshold value is between the threshold values of the cells in the reference cell set. In other words, it is possible to confirm whether the memory cell is really programmed or erased. That is, according to the present invention, an arbitrary threshold value can be set and confirmed, that is, self-diagnosis can be performed.

By the way, the state of the memory cell and the reference cell set before programming or erasing are the same if the programming or erasing time exceeds several tens of milliseconds, even if the initial threshold is different. If so, for example, after programming to a certain value, the memory cell threshold can be clamped by the reference cell set threshold in subsequent programming or erasing. This is because the program or erase after enough time for the initial state of the memory cell and the reference cell to be different regardless of the initial threshold value, for example, several tens μsec to several msec. This is because the characteristic curve becomes common depending on the value of the gate force ripple ratio.In other words, the characteristic curve is applied only depending on the gate couple ratio, and the characteristic curve is different if the gate couple ratio is different. It is possible to beat.

Therefore, the memory cell and the reference cell are simultaneously programmed or erased for a period of time sufficient for the initial state of the memory cell and the reference cell to be different, and the threshold and reset of the memory cell are performed. Self-diagnosis is performed by comparing the threshold value of the reference cell set with the threshold value of the reference cell and confirming that the threshold value of the memory cell is within the threshold value of the reference cell. The initial state of the memory cell differs from that of the reference cell. The sufficient time to become fully assumes that voltage is applied when the memory cell and the reference cell program or erase, obtained is several tens mu ec order one _r

As described above, in the present invention, the threshold value of a memory cell can be arbitrarily set using a reference cell set.

Here, it is assumed that the memory cell is an abnormal cell :: In this case, the programming or erasing speed shows an abnormal value independent of the clickable ratio. Therefore, even though programming or erasing is started at the same time as the reference cell set, after a certain time, the threshold value of the memory cell is compared with the threshold value of the reference cell set. This means that the memory cell can be self-diagnosed as being abnormal. If there is a memory cell exhibiting the bit characteristics, the memory cell can be diagnosed by using this reference cell / reset. It can be estimated that the characteristics have deteriorated.

To explain in more detail, for a memory cell that exhibits this tail bit characteristic, it is possible to program or erase the memory cell alone and the reference cell set at the same time and shoot the threshold of the memory cell with the threshold of the reference cell set. This indicates that the cell alone is normal. Nevertheless, if it shows tail bit characteristics, it is presumed that the cell cannot be supplied with seven-seventh voltage. For example, when the entire cell array is operated, the leak current is too large in each memory cell, and the terminal memory cell at the end is affected by the potential drop due to the leak.

Next, an example of the structure of the memory cell and the reference cell will be described. According to the present invention, a force for forming a reference cell set by a reference cell having a smaller power ratio than a memory cell and a reference cell having a larger coupling ratio than the memory cell; For example, the reference cell needs to have similar characteristics to the memory cell, so the basic structure of the memory cell and the reference cell is the same. Change the power rubble ratio by changing the area of the part facing the control port _c

Here, an example using a P o 1 y—S i cap type opening gate cell will be described. A P o 1 y—S i cap type floating gate cell is disclosed in US Pat. This is shown in No. 14 and has a structure as shown in FIG. 4, for example. That is, the n-type source 22 and the drain 23 are formed on the main surface of the p-type substrate 2〗, and the P o is formed on the channel region 24 therebetween through the gate insulating film 25. 1 Floating gate 26 of y-Si is formed, and Poly-Si cap 27 is formed on it. Poly-Si cap 27 is formed. A via hole 29 made of Po 1 y—S i is formed on the substrate through an interlayer insulating layer 28 made of, for example, ONO (oxide-nitride-oxide). Note that an insulating layer 30 is formed on the side of the floating gate 26.

The floating gate 26 is provided so as to cover the channel region 24, and the P o 1 y—S i cap 27 on the floating gate 26 is part or all of the source 22 and the drain 23. Alternatively, it has an eaves shape that covers a part of the element isolation region such as a field oxide film. The P o 1 y—S i cap 27 functions as a part of the floating gate 26. By providing the P o 1 y- S i cap 2 7, _c it is possible to increase the capacitance between the floating gate Ichito and control one Ruge Bok Here, since the coupling ratio can be changed by changing the capacitance between the floating gate and the control gate, the area of the poly-Si cap 27 in the above structure is changed, The power rubble ratio can be changed by changing the area of the portion where the oly-Si cap 27 and the control port 29 overlap.

For example, let the cell shown in FIG. 4 be a memory cell, and as shown in FIG. 5A, use a Po 1 y-Si cap 27 ′ with a shorter length (that is, a smaller area) than the cap 27. The cell having a small coupling ratio corresponds to the reference cell, and as shown in FIG. 5B, a cell having a Poly-Si cap 27 "longer (that is, larger in area) than the cap 27. To the reference cell with a large force ripple ratio

The above cell has a Po1y-Si cap on the opening gate, but without such a cap, the floating gate itself has a Po1y-S i It may have a cap function. Figures 6 to 8 show cells with such a structure. FIG. 6 is a plan view showing a part of the cell array of such a cell, FIG. 7 is a sectional view taken along line X--X ', and FIG. 8 is a sectional view taken along line Y--Y'. As shown in these figures. Further, in this cell, the floating gate 37 is designed to cover a part of the source 32 and the drain 33 and a part of the element isolation region 36. The specific structure of this cell is shown in FIGS. 7 and 8. That is, the n-type source 32 and the drain 33 are formed on the main surface of the ρ-type substrate 31. On the channel region 34, a gate insulating film 35 is formed. A floating gate 37 of P o 1 y—Si is formed on the gate insulating film 35, and an interlayer made of, for example, ONO (oxide mononitride monoxide) is further formed thereon. A control / legate 39 made of Po 1 y—Si is formed via an insulating layer 38, and these cells are formed. Are separated by an element isolation region;

In a cell having such a configuration, the area of the floating gate 37 is changed to change the area of the portion where the floating gate 37 and the control port 39 overlap. Thus, the capacitance between the floating gate and the control gate can be changed, thereby changing the gate couple ratio.

Although the example in which the floating gate is extended in the direction orthogonal to the arrangement direction of the source and the drain is shown, it goes without saying that the floating gate may be provided so as to extend in the arrangement direction of the source and the drain. Nor.

The following example is an example, and there is a method in which the opening gate is not stacked. In any case, it is simple and effective to adjust the cell characteristics by adjusting the floating gate length.

Next, the case where the floating gate is not stacked and the cell characteristics are adjusted by changing the overlapping area between the active region and the common gate will be described.

For example, FIG. 9 shows an example in which a 1-poly EPROM according to the 1993 VLSI Symposium 52-A is used as a reference cell. The cell 4 0, p-type part of the substrate 4 1 n-Ueru 4 2 is formed of, _n - Ueru 4 n + -type source to 2 other portions 4 3 and drain 44 power n - Ueru 4 A source 45 and a drain 46 are respectively formed in the portion 2 and a common floating gate 49 is formed on the channel regions 47 and 48 therebetween through a gate oxide film (not shown). Is provided. That is, it has a CMOS structure in which NMOS and PMQS are combined. The voltage Ve is applied to the source 43 and the drain 44 from the power supply 51, the source 4 and the drain 46 are grounded, and the NMOS part is read. The transistor functions as a transistor, and the PMOS portion functions as a control gate portion. Reference numeral 52 denotes a high-concentration region for improving grounding characteristics.

In such a 1 po Iy type EPROM structure, the gate couple ratio depends on the amount of threshold ion implantation, the thickness of the gate oxide film, and the floating in the control gate portion (PMOS). It depends on the area of the portion where the gate and the active region overlap, and the area ratio of the portion where the floating gate and the active region overlap in the readout transistor section (NMOS) (hereinafter referred to as the area ratio of the active region). By making these different, the gate cut ratio can be changed, and thus the threshold can be made different.

Next, a detailed description will be given of a case where the gate power ratio is changed depending on the cell due to the difference in the area ratio of the active region between the control gate unit (PMOS) and the readout transistor unit (NVIOS).

As shown in FIG. 10A, in the first reference cell 6 () of the 1 po 1 y-type EPROM structure, the control gate (NMOS) 61 and the read-out transistor (PMOS) 6 In each of 2, a floating gate 63 common to both is provided on each active area 64, 65. Here, the area of the overlapping portion between the active region 64 of the contact gate portion 61 and the contacting gate 63: An, the active region 65 of the read transistor portion 62, and the floating gate. Area of the overlapping portion with the point 63: Ratio to Ap (hereinafter, referred to as area ratio of the overlapping portion): The gate force ripple ratio of the reference cell 60 depends on Ap / An.

Therefore, for example, as shown in FIG. 10B, in the reference cell 70 of the second 1 po 1 y type EPROM structure, the active area 73 of the contact opening part 71 is Area of overlapping part with floating gate 6 3: A n ′ is the same as the area of the first reference cell 60: A n, and the active area Ί4 of the read transistor section 72 is overlapped with the floating gate 63 ′). p 'is made larger than the area of the first reference cell 60: Ap. Thus, the overlap in the second reference cell 70') The area ratio of the portion: Ap '/ A n' force The area ratio of the overlapping portion in the first reference cell: larger than A p / A n. As a result, the gate couple ratio of the first reference cell 60 is changed to be different from the gate coupling ratio of the second reference cell 70 by changing the gate coupling ratio of the second reference cell 70. Can be different.

Note that, in this case, the area ratio of the overlapping portion of the read transistor portion 72 in the second reference cell 70: Ap ′ is determined by the read transistor portion 65 in the first reference cell 60. The area of the overlapping portion of the control gates is different from Ap, but is not limited thereto. The area of the overlapping portion of the control gate portions 64, 71 of both: An, An 'is mutually different. The areas of the overlapping portions in the read transistor portions 65, 72 may be the same: Ap, Ap 'may be the same, or the control portion portions 64, 71 of both may be different. The area of the overlapping portion of An: An and An 'and the area of the overlapping portion in both read transistor portions 65, 72: Both Ap and Ap' may be different.

In the reference cells 40, 60, and 70 shown in FIGS. 9, 108, and 14B, the readout transistors are set as the NMOS transistors for the connection port units 61 and 71. An example of a CMOS structure in which the parts 62 and 72 are PMOS is shown. However, conversely, the reference cells 40, 60, and 70 have a CMOS transistor in which the control gate sections 61 and 71 are PMOS and the read transistor sections 62 and 72 are NMOS. May be a structure 丄 b In addition, the common floating gate 63 is formed of the same conductive layer, and is electrically connected between the gate of the PMOS transistor and the gate of the NMOS transistor. It suffices if the layer forming the gate and the layer connecting the gates are different, and the layer forming the gate of the PMOS transistor and the gate of the NMOS transistor may be different. It is also possible that the active layer of the PMOS transistor and the active part of the NMOS transistor are electrically connected to each other. It is enough if it is absent

In this case, in the case of changing the threshold ion dose and the method of changing the thickness of the gate oxide film, the number of steps increases, but the area ratio of the active region is changed. The method is more preferable because there is no possibility of increasing the number of steps. That is, the area ratio of the active region is determined by changing the area (gate oxide film area) of the PMOS and NMOS channel regions in the element isolation region forming photostep or by changing the floating gate formation photostep. The number of stages can be increased by changing the area of the floating gate, but in order to change these areas, it is simple to improve the photomask in the same manner as in the above example without increasing the number of steps. The technique is sufficient.

Figures 11A and 11B show modified examples of the reference cell.

In FIG. 11A, in a first reference 161, an n-type diffusion layer 162 formed on a p-type substrate and a common polysilicon gate provided on the n ⁺ diffusion layer 162 are provided. The control port part 164 is constituted by 163. In addition, a source 165 and a drain 1666 consisting of n ⁺ regions formed on the same P-type substrate and separated from each other are formed between the source 165 and a drain 1666 _^? A channel region 1 6 8 which is, formed via a gate insulating film (not Shimese Figure) on the channel region 1 6 8, and controls the gate portion 1 64 and the common policy Rikonge sheet 1 64 A read transistor section 169 having an NMOS structure is configured. The first reference cell 161 is composed of the control gate section 164 and the read transistor section 169.

In a first re file Rensuseru 1 6 1 of such a structure, the area of heavy Do Ri fit portion between the n ^J diffusion layer 1 6 2 and polysilicon Kongeto 1 6 3 in Con preparative port Ichiru gate unit 1 64: The area ratio of the area where A 1 overlaps the active area 170 of the read transistor section 16 9 with the polysilicon gate 16 3: area ratio with A 2: A 2 / A 1, the first memory cell 1 6] depends on the gate coupling ratio:

Therefore, as shown in FIG. 11B, in the second reference cell 171, the area of the overlapping portion between the n + diffusion layer 173 of the control gate portion 172 and the polysilicon gate 174 is : A 1 'and the area ratio of the overlapping area of the active region 1776 of the readout transistor section 17 5 and the polysilicon gate 1 74: A 2': Area ratio of Λ 1 ΖΑ '2, FIG. By making the area ratio of the first reference cell 161 shown in FIG. 9 different from that of A2ZA1, the gate force ruffle ratio of the two can be made different.

In this modification, n ⁺ diffusion layer 1 6 2 1 7 3 and NMO S transistor read transistor unit 1 6 9 consisting of data, 1 7 5 and the first, the second riff A Rensuseru 1 6 1 , 171, but conversely, the P-diffusion layer and the PMOS transistor may constitute the first and second reference cells. E In any of the reference cells described above, the floating gate Length of the active area and the overlap between the active area and the common floating gate. 1 O It is simple and effective to adjust cell characteristics by adjusting the area where

Next, an example of a specific nonvolatile memory circuit configured using cells having such a structure is shown in FIG. 12. In FIG. 12, each cell is illustrated in FIG. 4 to FIG. The floating gate length is shown differently: Here, the sense amplifier 3a determines whether the threshold value is equal to or greater than the lower limit (L) and the sense amplifier determines whether the threshold value is equal to or less than the upper limit (H). It has two sense amplifiers, amplifier 3b, which are connected to a memory cell switching circuit 6 and a reference cell selection circuit 4. Judgment state (Depending on the L or H force, the switching circuit 6 switches only the sense amplifier, and the selection circuit 4 switches the sense amplifier and selects the reference level R _; FIG. In FIG. 2, the reference cell set 5 corresponding to the reference level R j is shown; the other reference cell sets are connected in the same way:

In the selection circuit 4, it is simplest to determine R, which is selected from the balun scan or the program time.

The following describes how to use this circuit.

First, according to the multi-value level / LES to be set each reference cell set flogger to ram: If the standard pulse and SOO nsec, the 3 0 pulse, R ₂ is a multi-level programmed 6 0 pulse and the like Make settings.

Next, the memory cell is programmed. The memory cell is provided with a width of about ± 5 pulses for each setting pulse in consideration of manufacturing variations of each cell. For example, in R1, verification starts from 25 pulses, and program ends (verification OK). ) Stop the program pulse at the time. If verifying NG is not performed even with 35 pulses, use program NG. This is the method that is also used in binary programs. After verifying the program, for example, select the L level sense amplifier 3a, first check the L level, then select the H level / level sense amplifier 3b and check the H level, It is checked whether the threshold value of the memory cell is within this range. For example, at the R level, after programming 25 pulses, L → H verification starts and continues until OK or 35 pulses. 3 5 Even if the valley is verified NG, the cell program is NG.

If NG appears, erase all cells, return to the initial state (or a state close to the initial state), and restart the program from the beginning.

If these operations are performed for each level, the program ends.

Next, another specific example of the non-volatile memory circuit is shown in FIG. _{13. In} this example, one sense amplifier 3 ′ is used without using the switching circuit 6 in FIG. 12. By doing so, the effect that the operation speed is faster than in the case of FIG. 12 can be obtained.

In the above example, a stacked gate type memory cell and reference cell were used, but a 1 po 1 y type cell as shown in Figs. 9 to 11 can also be used. However, the type of the reference cell may be selected so as to facilitate the process design.

As described above, according to the present invention, a reference device and a reference level thereof capable of coping with multi-leveling without increasing a circuit area and having a sufficient correlation with a memory cell. A setting method is provided.

Claims

The scope of the claims

1. A reference cell having a plurality of reference cell sets each including a reference cell having a gate couple ratio smaller than that of a memory cell and a reference cell having a gate coupling ratio larger than that of a memory cell. Reference equipment

2. The method according to claim 1, wherein the two reference cells constituting each of the reference cell sets have a gate coupling ratio of ± 0.5 to ± 7.0% with respect to a gate coupling ratio of a memory cell. Reference device

3. Each reference cell includes a semiconductor substrate of a first conductivity type having a main surface, a source and a drain of a second conductivity type formed on the main surface, and a source and a drain between the source and the drain of the main surface. A floating gate provided on the channel region via an insulating layer, a conductive cap provided continuously on the floating gate so as to protrude from the floating gate, and an insulating layer provided on the conductive cap. And a control gate provided

2. The reference device according to claim 1, wherein an area of the conductive cap is different between the two reference cells.

4. Each reference cell includes a first conductivity type semiconductor substrate having a main surface, a second conductivity type source and drain formed on the main surface, and a channel region between the source and drain on the main surface. A contacting gate provided on the substrate via an insulating layer,

2. The reference according to claim 1, wherein the area of a portion of the surface facing the control gate of the floating gate in the two reference cells with respect to the control gate is different depending on the two reference cells. 3. Reference device.

5. Each of the reference cells includes an active portion formed on a main surface of a semiconductor substrate and a gate portion disposed on the main surface with a gate oxide film interposed therebetween. And an active portion of the first MOS transistor and an active portion of the second MOS transistor are electrically insulated from each other, and a gate portion of the first MOS transistor is electrically connected to the active portion of the first MOS transistor. A gate portion of the second MOS transistor is electrically coupled;

The ratio of the area of the overlapping part of the active part and the gate part of the first MOS transistor to the area of the overlapping part of the active part and the gate part of the second MOS transistor is between the two reference cells. The reference device according to claim 1, which is different.

6. A reference device having a plurality of reference cell sets each including a reference cell having a gate couple ratio smaller than the memory cell and a reference cell having a gate couple ratio larger than the memory cell. A reference level setting method, wherein the reference cell set is programmed by a pulse number that is an integral multiple of a programming pulse to a memory cell or a time equivalent thereto, and the reference level is set. Lens level setting method

7. The reference device having a plurality of reference cell sets each including a reference cell having a gate coupling ratio smaller than the memory cell and a reference cell having a gate coupling ratio larger than the memory cell. A self-diagnosis method, wherein the memory cell and the reference cell are simultaneously programmed or erased, and a threshold value of the memory cell is compared with a threshold value of the reference cell to determine a threshold value of the memory cell. Self-diagnosis method, wherein it is confirmed that the value is within a threshold value of the reference cell.

8. The self-diagnosis method according to claim 7, wherein the memory cell and the reference cell are simultaneously programmed or erased for a time sufficient for the initial states of the memory cell and the reference cell to be different.

9. The self-diagnosis method according to claim 8, wherein the memory cell and the reference cell are simultaneously programmed or erased for several tens of microseconds.

1 0. The memory cell and

A reference including a plurality of reference cell sets each including a reference cell having a gate couple ratio smaller than that of the memory cell and a reference cell having a gate coupling ratio larger than that of the memory cell. A nonvolatile semiconductor memory device, comprising: a device;

11. The two reference cells constituting each of the reference cell sets have a gate coupling ratio of ± 0.5 to 7.0% with respect to a gate coupling ratio of a memory cell. The nonvolatile semiconductor memory device according to claim 1.

12. Each reference cell includes a semiconductor substrate of a first conductivity type having a main surface, a source and a drain of a second conductivity type formed on the main surface, and a source and a drain of the main surface. A floating gate provided on the intervening channel region via an insulating layer; a conductive cap provided continuously on the floating gate so as to protrude from the floating gate; And a contact port provided with an insulating layer interposed therebetween.

10. The non-volatile semiconductor memory device according to claim 10, wherein the surface area of the conductive cap is different between the two reference cells.

1. Each reference cell includes a semiconductor substrate of a first conductivity type having a main surface, a source and a drain of a second conductivity type formed on the main surface, and a source and a drain of the main surface. A floating gate provided on the channel region of the

10. The device according to claim 10, wherein an area of a portion of the surface of the two reference cells facing the control gate of the floating gate with respect to the control gate is different between the two reference cells. Nonvolatile semiconductor memory Moly device-.

1 4. Each of the reference cells has an active portion formed on a main surface of a semiconductor substrate and a gate portion disposed on the main surface with a gate oxide film interposed therebetween. An active portion of the first MOS transistor and an active portion of the second MOS transistor are electrically insulated from each other, and the gate portion of the first MOS transistor and the active portion of the first MOS transistor are electrically insulated from each other. The gate portion of the second MOS transistor is electrically coupled,

The ratio of the area of the overlapping part of the active part and the gate part of the first MOS transistor to the area of the overlapping part of the active part and the gate part of the second MOS transistor is the two reference cells. The nonvolatile semiconductor memory device according to claim 10, wherein the nonvolatile semiconductor memory device differs between the nonvolatile semiconductor memory devices.