WO1998020654A1 - System for adaptive transmission line equalization and mlt-3 to nrz data conversion - Google Patents

System for adaptive transmission line equalization and mlt-3 to nrz data conversion Download PDF

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Publication number
WO1998020654A1
WO1998020654A1 PCT/US1997/010864 US9710864W WO9820654A1 WO 1998020654 A1 WO1998020654 A1 WO 1998020654A1 US 9710864 W US9710864 W US 9710864W WO 9820654 A1 WO9820654 A1 WO 9820654A1
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WO
WIPO (PCT)
Prior art keywords
transmission line
digitally
equalizer
signal
comparator
Prior art date
Application number
PCT/US1997/010864
Other languages
French (fr)
Inventor
Yi Cheng
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1998020654A1 publication Critical patent/WO1998020654A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Definitions

  • This invention relates generally to integrated circuit technology used in data communication systems.
  • a digitally-controlled transmission line equalizer for adaptive compensation of a signal distorted by the transmission line.
  • a transmitter sends analog/digital signals over a transmission medium such as a transmission line or cable to a receiver the received analog/digital signals may become distorted due to the signals being transmitted through a certain length of the transmission line.
  • a 100BaseT Ethernet receiver (follow- ing the Ethernet standard ANSI/IEEE Std. 802.3u) must be able to receive a three-level analog signal at the rate of 125 megabits per second, after such signal has passed through a transmission line having a length up to 100 meters.
  • a digitally-controlled transmission line equalizer for receiving MLT-3 distorted signals transmitted through a transmission line and for adaptively compensating for the signal distortion.
  • the digitally-controlled equalizer includes an input terminal for receiving the distorted signals transmitted through the transmission line.
  • a peak detection circuit is responsive to the distorted signals for determining the signal distortion and generating a peak detected signal .
  • A/D converter is provided for converting the peak detected signal to a digital control signal.
  • An equalizer circuit is responsive to the distorted signal and to the digital control signal for generating first and second adaptive restored MLT-3 signals.
  • a converter circuit is responsive to the first and second adaptive restored signals for converting the same to a NRZ data output signal.
  • FIG. 1 is a simplified block diagram of a data communication system employing a digitally-controlled transmission line equalizer 12, constructed in accordance with the principles of the present invention
  • FIG. 2 is a detailed block diagram of the equalizer 12 of Figure 1;
  • Figures 3 (a) through 3 (d) are waveforms at various points in Figures 1 and 2, useful in explaining the oper- ation of the present invention.
  • FIG. 1 a simplified block diagram of a data communication system 10 utilizing a digitally-controlled transmission line equalizer 12, which is constructed in accordance with the principles of the present invention.
  • the data communication system 10 is comprised of a MLT-3 transmitter 14, a transmission medium 16, the digitally-controlled equalizer 12 of the present inven- tion, and an Ethernet receiver 18.
  • the transmission medium 16 is preferably a transmission line or cable having a length up to 100 meters. Since the transmission line has a limited bandwidth, the signals being transmitted therethrough will have amplitude loss and phase shift, the amount being dependent upon the signal frequency. The higher frequency signals will have more loss in amplitude and more phase shift, which will thus cause signal distortion.
  • the digitally-controlled transmission line equalizer 12 is designed to enhance the high frequency components in a signal, after it has been transmitted through the transmission line, so as to adaptively compensate (equalize) the transmission line distortion. Accordingly, the digitally-controlled equalizer receives the distorted signals from the transmission line 16 on its input on lines 40, 42 and provides on its output on line 20 a NRZ data output signal, which is delivered to the receiver 18.
  • FIG 2 there is shown a more detailed block diagram of the digitally-controlled equalizer 12 of Figure 1, according to the present invention.
  • the equal- izer 12 has thus been designed to adaptively compensate for the signal distortion of the transmission line 16.
  • the equalizer 12 is comprised of a peak detection circuit 24, an algorithmic A/D converter 26, an equalizer circuit 28, a first comparator 30, a second comparator 32, and an OR logic gate 34.
  • the single- ended input voltage signals V IN1 and V IN0 on the respective lines 36 and 38 connected to the output of the transmitter 14 are applied to the input of the transmission line 16.
  • the corresponding single-ended distorted MLT-3 signals V p and V N (after being transmitted through 100 meters of the transmission line 16), are applied via lines 40, 42 to the input of the digitally-controlled equalizer 12 of the present invention.
  • the distorted signals V p and V N are fed via line 44 to the input of the peak detector circuit 24 which serves to sense the distorted signals from the transmission line to determine signal distortion.
  • the distorted signals are also fed via line 46 to the first input of the equalizer circuit 28.
  • the peak detected signal from the output of the peak detection circuit 24 on line 48 is connected to the input of the algorithmic A/D converter 26.
  • the A/D converter senses the peak detected signal from the peak detector circuit and converts the same into digital data of three (3) bits from "000" to "111".
  • the digital data "000” represents a transmission line or cable length of zero meters
  • the digital data "111” represents a transmission line length of 100 meters or more.
  • the 3 -bits digital data signal defines a digital control signal from the A/D converter on line 50 which is applied to the second input of the equalizer circuit 28.
  • the equalizer circuit has a first output on line 52 which is a single-ended adaptive restored MLT-3 signal V E0P and has a second output on line 54 which is a single-ended adaptive restored MLT-3 signal V E0N .
  • the restored signal V E0P is fed to the non-inverting input of the first comparator 30 and to the inverting input of the second com- parator 32.
  • the second restored signal V E0N is applied to the inverting input of the comparator 30 and to the non- inverting input of the comparator 32.
  • a baseline control signal BC is applied to a hysteresis control input of the comparators 30 and 32 via respective lines 56 and 58.
  • the control signal BC will adjust the hysteresis of the comparators 30, 32 to a higher level so as to eliminate false triggering of the comparators when the restored MLT-3 signals switch to a zero value.
  • the output of the comparator 30 on line 60 is fed to a first input of the OR logic gate 34, and the output of the second comparator 32 on line 62 is fed to a second input of the OR logic gate 34.
  • the output of the OR logic gate provides the NRZ data output signal on the line 20 which corresponds to the input MLT-3 signals generated by the transmitter 14.
  • Figure 3 (a) shows the respective single- ended input voltage MLT-3 signals V IN1 and V IN0 ( Figure 1) applied to the input of the transmission line or cable 16 via the corresponding lines 36 and 38.
  • Figure 3(b) il- lustrates the respective single-ended distorted MLT-3 signals V p and V N (after being transmitted through 100 meters of the cable 16) on the corresponding lines 40 and 42.
  • the single-ended adaptive restored signals V E0P and V E0N on the respective lines 52 and 54 ( Figure 2) from the output of the equalizer circuit 28 are depicted in Figure 3(c) .
  • the converted NRZ data output signal V ⁇ on the line 20 from the output of the OR logic gate 34 is illustrated in Figure 3 (d) .
  • the converted signal V ⁇ of Figure 3 (d) will not be identical to the single-ended input voltage MLT-3 signals V IN1 and V IN2 of Figure 3(a) since the MLT-3 signals have not been only restored by the digitally-controlled equalizer 12, but also converted to the NRZ data output signal.
  • the present invention provides an improved digitally-controlled transmission line equalizer for receiving distorted signals transmitted through a transmission line and for adaptively compensating for the signal distortion.
  • the equalizer of the present invention is formed of a peak detection circuit, an algorithmic A/D converter, an equalizer circuit, a first comparator, a second comparator, and an OR logic gate. While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodi- ment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims .

Abstract

A digitally-controlled transmission line equalizer is provided for receiving distorted MLT-3 distorted signals transmitted through a transmission line and for adaptively compensating for the signal distortion. The digitally-controlled equalizer is formed of a peak detection circuit (24), an algorithmic A/D converter (26), an equalizer circuit (28), a first comparator (30), a second comparator (32), and an OR logic gate (34). The digitally-controlled equalizer is of a relatively simple construction and has a high speed of operation.

Description

DESCRIPTION
SYSTEM FOR ADAPTIVE TRANSMISSION
LINE EQUALIZATION AND MLT-3
TO NRZ DATA CONVERSION
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates generally to integrated circuit technology used in data communication systems.
More particularly, it relates to a digitally-controlled transmission line equalizer for adaptive compensation of a signal distorted by the transmission line.
2. Description of the Prior Art:
As is generally known in the art of data communication systems, when a transmitter sends analog/digital signals over a transmission medium such as a transmission line or cable to a receiver the received analog/digital signals may become distorted due to the signals being transmitted through a certain length of the transmission line. For example, a 100BaseT Ethernet receiver (follow- ing the Ethernet standard ANSI/IEEE Std. 802.3u) must be able to receive a three-level analog signal at the rate of 125 megabits per second, after such signal has passed through a transmission line having a length up to 100 meters. In order to compensate for the signal distortion due to the signals being transmitted through the transmission line, there is typically required some type of "equalizer circuit" to which the received signals are applied before they are passed on to the receiver.
Accordingly, it would therefore be desirable to pro- vide an improved digitally-controlled transmission line equalizer for adaptively compensating for signal distortions which operates more efficiently and effectively. It would also be expedient to provide a digitally- controlled equalizer whose characteristics are controlled by a peak detection circuit and an algorithmic A/D converter .
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a digitally-controlled transmission line equalizer for adaptively compensating for signal distortion caused by a transmission line.
It is an object of the present invention to provide a digitally-controlled transmission line equalizer which is of a relatively simple construction.
It is another object of the present invention to provide a digitally-controlled equalizer which has a high speed of operation compatible with CMOS technology.
It is still another object of the present invention to provide a digitally-controlled transmission line equalizer which is formed of a peak detection circuit, an algorithmic A/D converter, an equalizer circuit, first and second comparators, and an OR logic gate.
In accordance with the preferred embodiment of the present invention, there is provided a digitally- controlled transmission line equalizer for receiving MLT-3 distorted signals transmitted through a transmission line and for adaptively compensating for the signal distortion. The digitally-controlled equalizer includes an input terminal for receiving the distorted signals transmitted through the transmission line. A peak detection circuit is responsive to the distorted signals for determining the signal distortion and generating a peak detected signal . A/D converter is provided for converting the peak detected signal to a digital control signal. An equalizer circuit is responsive to the distorted signal and to the digital control signal for generating first and second adaptive restored MLT-3 signals. A converter circuit is responsive to the first and second adaptive restored signals for converting the same to a NRZ data output signal.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein:
Figure 1 is a simplified block diagram of a data communication system employing a digitally-controlled transmission line equalizer 12, constructed in accordance with the principles of the present invention;
Figure 2 is a detailed block diagram of the equalizer 12 of Figure 1; and
Figures 3 (a) through 3 (d) are waveforms at various points in Figures 1 and 2, useful in explaining the oper- ation of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now in detail to the drawings, there is illustrated in Figure 1 a simplified block diagram of a data communication system 10 utilizing a digitally- controlled transmission line equalizer 12, which is constructed in accordance with the principles of the present invention. The data communication system 10 is comprised of a MLT-3 transmitter 14, a transmission medium 16, the digitally-controlled equalizer 12 of the present inven- tion, and an Ethernet receiver 18.
The transmission medium 16 is preferably a transmission line or cable having a length up to 100 meters. Since the transmission line has a limited bandwidth, the signals being transmitted therethrough will have amplitude loss and phase shift, the amount being dependent upon the signal frequency. The higher frequency signals will have more loss in amplitude and more phase shift, which will thus cause signal distortion.
The digitally-controlled transmission line equalizer 12 is designed to enhance the high frequency components in a signal, after it has been transmitted through the transmission line, so as to adaptively compensate (equalize) the transmission line distortion. Accordingly, the digitally-controlled equalizer receives the distorted signals from the transmission line 16 on its input on lines 40, 42 and provides on its output on line 20 a NRZ data output signal, which is delivered to the receiver 18.
In Figure 2, there is shown a more detailed block diagram of the digitally-controlled equalizer 12 of Figure 1, according to the present invention. The equal- izer 12 has thus been designed to adaptively compensate for the signal distortion of the transmission line 16. The equalizer 12 is comprised of a peak detection circuit 24, an algorithmic A/D converter 26, an equalizer circuit 28, a first comparator 30, a second comparator 32, and an OR logic gate 34.
As can be seen from Figures 1 and 2, the single- ended input voltage signals VIN1 and VIN0 on the respective lines 36 and 38 connected to the output of the transmitter 14 are applied to the input of the transmission line 16. The corresponding single-ended distorted MLT-3 signals Vp and VN (after being transmitted through 100 meters of the transmission line 16), are applied via lines 40, 42 to the input of the digitally-controlled equalizer 12 of the present invention. The distorted signals Vp and VN are fed via line 44 to the input of the peak detector circuit 24 which serves to sense the distorted signals from the transmission line to determine signal distortion. The distorted signals are also fed via line 46 to the first input of the equalizer circuit 28. The peak detected signal from the output of the peak detection circuit 24 on line 48 is connected to the input of the algorithmic A/D converter 26. The A/D converter senses the peak detected signal from the peak detector circuit and converts the same into digital data of three (3) bits from "000" to "111". The digital data "000" represents a transmission line or cable length of zero meters, and the digital data "111" represents a transmission line length of 100 meters or more.
The 3 -bits digital data signal defines a digital control signal from the A/D converter on line 50 which is applied to the second input of the equalizer circuit 28. The equalizer circuit has a first output on line 52 which is a single-ended adaptive restored MLT-3 signal VE0P and has a second output on line 54 which is a single-ended adaptive restored MLT-3 signal VE0N. The restored signal VE0P is fed to the non-inverting input of the first comparator 30 and to the inverting input of the second com- parator 32. The second restored signal VE0N is applied to the inverting input of the comparator 30 and to the non- inverting input of the comparator 32.
A baseline control signal BC is applied to a hysteresis control input of the comparators 30 and 32 via respective lines 56 and 58. When there is a long pulse without a transition, the control signal BC will adjust the hysteresis of the comparators 30, 32 to a higher level so as to eliminate false triggering of the comparators when the restored MLT-3 signals switch to a zero value. The output of the comparator 30 on line 60 is fed to a first input of the OR logic gate 34, and the output of the second comparator 32 on line 62 is fed to a second input of the OR logic gate 34. The output of the OR logic gate provides the NRZ data output signal on the line 20 which corresponds to the input MLT-3 signals generated by the transmitter 14.
With reference to Figures 1 and 2 again, the operation of the digitally-controlled equalizer 12 can now be observed in connection with the waveforms of Figures 3 (a) through 3 (d) . Figure 3 (a) shows the respective single- ended input voltage MLT-3 signals VIN1 and VIN0 (Figure 1) applied to the input of the transmission line or cable 16 via the corresponding lines 36 and 38. Figure 3(b) il- lustrates the respective single-ended distorted MLT-3 signals Vp and VN (after being transmitted through 100 meters of the cable 16) on the corresponding lines 40 and 42. The single-ended adaptive restored signals VE0P and VE0N on the respective lines 52 and 54 (Figure 2) from the output of the equalizer circuit 28 are depicted in Figure 3(c) . Finally, the converted NRZ data output signal V^ on the line 20 from the output of the OR logic gate 34 is illustrated in Figure 3 (d) . As will be noted, the converted signal V^ of Figure 3 (d) will not be identical to the single-ended input voltage MLT-3 signals VIN1 and VIN2 of Figure 3(a) since the MLT-3 signals have not been only restored by the digitally-controlled equalizer 12, but also converted to the NRZ data output signal.
From the foregoing detailed description, it can thus be seen that the present invention provides an improved digitally-controlled transmission line equalizer for receiving distorted signals transmitted through a transmission line and for adaptively compensating for the signal distortion. The equalizer of the present invention is formed of a peak detection circuit, an algorithmic A/D converter, an equalizer circuit, a first comparator, a second comparator, and an OR logic gate. While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodi- ment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims .

Claims

1. A digitally-controlled transmission line equalizer for receiving distorted MLT-3 signals transmitted through a transmission line and for adaptively compensating for the signal distortion, said digitally- controlled equalizer comprising: input means for receiving the distorted signals transmitted through the transmission line; peak detection means responsive to the distorted signals for detecting the signal distortion and generating a peak detected signal;
A/D converter means for converting said peak detected signal to a digital control signal; equalizer means responsive to the distorted signals and said digital control signal for generating first and second adaptive restored MLT-3 signals; and comparator means responsive to said first and second restored signals for converting the same to a NRZ data output signal . 2. A digitally-controlled transmission line equalizer as claimed in Claim 1, wherein said peak detection means is comprised of a peak detector circuit (24) .
3. A digitally-controlled transmission line equalizer as claimed in Claim 2, wherein said A/D converter means is comprised of an algorithmic A/D converter (26) .
4. A digitally-controlled transmission line equalizer as claimed in Claim 3, wherein said digital control signal is a 3-bit control signal.
5. A digitally-controlled transmission line equal- izer as claimed in Claim 4, wherein said equalizer means is comprised of an equalizer circuit (28) .
6. A digitally-controlled transmission line equalizer as claimed in Claim 5, wherein said comparator means includes first and second comparators (30, 32) , said first comparator having its non-inverting input connected to receive said first restored signal and its inverting input connected to receive said second restored signal, said second comparator having its non-inverting input connected to receive said second restored signal and its inverting input connected to receive said first restored signal .
7. A digitally-controlled transmission line equal- izer as claimed in Claim 6, wherein said comparator means further includes logic means having a first input connected to the output of said first comparator, a second input connected to the output of said second comparator, and an output for generating said NRZ data output signal. 8. A digitally-controlled transmission line equalizer as claimed in Claim 6, wherein said comparator means are responsive to a baseline control signal for adjusting its hysteresis so as to eliminate false triggering.
9. A digitally-controlled transmission line equal- izer as claimed in Claim 7, wherein said logic means is comprised of an OR logic gate (34) .
10. A communication system comprising in combination: transmitter means (14) for generating original MLT-3 signals ; transmission medium means (16) for causing distortion in said original MLT-3 signals as they are transmitted therethrough; digitally-controlled equalizer means (12) for receiving distorted MLT-3 signals transmitted through said transmission medium means and for adaptively compensating for the signal distortion; receiver means (18) for receiving a NRZ data output signal from said digitally-controlled equalizer means; and said digitally-controlled equalizer means including input means for receiving the distorted signals transmitted through the transmission line, peak detection means responsive to the distorted signals for detecting the signal distortion and generating a peak detected signal, A/D converter means for converting said peak detected signal to a digital control signal, equalizer means responsive to the distorted signals and said digital control signal for generating first and second adaptive restored MLT-3 signals, and comparator means responsive to said first and second restored signals for converting the same to a NRZ data output signal.
11. A digitally-controlled transmission line equalizer as claimed in Claim 10, wherein said peak detection means is comprised of a peak detector circuit (24) . 12. A digitally-controlled transmission line equalizer as claimed in Claim 11, wherein said A/D converter means is comprised of an algorithmic A/D converter (26) . - ll - lS. A digitally-controlled transmission line equalizer as claimed in Claim 12, wherein said digital control signal is a 3-bit control signal.
14. A digitally-controlled transmission line equal- izer as claimed in Claim 13, wherein said equalizer means is comprised of an equalizer circuit (28) .
15. A digitally-controlled transmission line equalizer as claimed in Claim 14, wherein said comparator means includes first and second comparators (30, 32), said first comparator having its non-inverting input connected to receive said first restored signal and its inverting input connected to receive said second restored signal, said second comparator having its non-inverting input connected to receive said second restored signal and its inverting input connected to receive said first restored signal.
16. A digitally-controlled transmission line equalizer as claimed in Claim 15, wherein said comparator means further includes logic means having a first input connected to the output of said first comparator, a second input connected to the output of said second comparator, and an output for generating said NRZ data output signal .
17. A digitally-controlled transmission line equal- izer as claimed in Claim 16, wherein said comparator means are responsive to a baseline control signal for adjusting its hysteresis so as to eliminate false triggering.
18. A digitally-controlled transmission line equal- izer as claimed in Claim 17, wherein said logic means is comprised of an OR logic gate (34) .
PCT/US1997/010864 1996-11-04 1997-07-02 System for adaptive transmission line equalization and mlt-3 to nrz data conversion WO1998020654A1 (en)

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US74308296A 1996-11-04 1996-11-04
US08/743,082 1996-11-04

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Cited By (2)

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US6466626B1 (en) 1999-02-23 2002-10-15 International Business Machines Corporation Driver with in-situ variable compensation for cable attenuation
WO2003009551A2 (en) * 2001-07-18 2003-01-30 Vrije Universiteit Brussel (Vub) Line equalizer with differentiating circuit and hysteresis decoder

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US4707840A (en) * 1985-11-05 1987-11-17 Nec Corporation Line equalizer having pulse-width deviation detector for compensating long-term level variations
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US3578914A (en) * 1969-04-09 1971-05-18 Lynch Communication Systems Equalizer with automatic line build-out
EP0163482A2 (en) * 1984-05-24 1985-12-04 Nec Corporation Equalizer for frequency independent and dependent transmission loss components with a pilot used for the frequency independent component
US4707840A (en) * 1985-11-05 1987-11-17 Nec Corporation Line equalizer having pulse-width deviation detector for compensating long-term level variations
US5293405A (en) * 1991-10-31 1994-03-08 International Business Machines Corp. Adaptive equalization and regeneration system
WO1995027358A1 (en) * 1994-03-31 1995-10-12 Apple Computer, Inc. Method and apparatus for implementing a common mode level shift

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6466626B1 (en) 1999-02-23 2002-10-15 International Business Machines Corporation Driver with in-situ variable compensation for cable attenuation
WO2003009551A2 (en) * 2001-07-18 2003-01-30 Vrije Universiteit Brussel (Vub) Line equalizer with differentiating circuit and hysteresis decoder
WO2003009551A3 (en) * 2001-07-18 2004-03-18 Vrije Universiteit Brussel Vub Line equalizer with differentiating circuit and hysteresis decoder
US7274756B2 (en) 2001-07-18 2007-09-25 Vrije Universteit Brussel Digital signal receiver operating beyond the -3dB frequency

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