WO1998025206A1 - Dispositif de controle pour ordinateur - Google Patents
Dispositif de controle pour ordinateur Download PDFInfo
- Publication number
- WO1998025206A1 WO1998025206A1 PCT/JP1997/004382 JP9704382W WO9825206A1 WO 1998025206 A1 WO1998025206 A1 WO 1998025206A1 JP 9704382 W JP9704382 W JP 9704382W WO 9825206 A1 WO9825206 A1 WO 9825206A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- output
- circuit
- microcomputer
- standby
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Definitions
- the present invention relates to a computer monitoring device that monitors whether a computer provided in a power window system or the like of a vehicle is operating normally.
- a microcomputer that uses a battery as a power source
- the microcomputer when the microcomputer is not used, the microcomputer is set to a standby mode in order to reduce the power consumption of the battery, and the program execution is stopped.
- the microcomputer determines whether or not a predetermined signal (for example, a signal generated based on a clock signal, hereinafter referred to as a “cook signal”) is output from the microcomputer.
- a predetermined signal for example, a signal generated based on a clock signal, hereinafter referred to as a “cook signal”
- a microcomputer monitoring circuit that monitors the status, determines that the microcomputer is not in a normal state when the clock signal is no longer detected, and outputs a signal to restart the microcomputer (hereinafter referred to as “restart signal”). Watchdog circuit) is provided.
- the microcomputer monitoring circuit In order to prevent such a restart of the microcomputer that shifts to the standby mode, when the microcomputer detects a signal that is output when the microcomputer shifts to the standby mode (hereinafter referred to as “standby signal J”), the microcomputer monitoring circuit is also activated. When the standby signal is detected, the microcomputer monitoring circuit shifts to the standby mode and stops the monitoring function of the microcomputer.
- standby signal J a signal that is output when the microcomputer shifts to the standby mode
- An example of a system including such a microcomputer and a microcomputer monitoring circuit is a vehicle power window system.
- the microcomputer controls the relay and operates the motor for raising and lowering the door glass.
- the microcomputer monitoring circuit monitors the operating state of the microcomputer, and if it is determined that the microcomputer is not operating properly, Outputs restart signal to.
- the power window system has a microcomputer control system and a SW control system (direct control by a switch) to control the motor in accordance with the switch operation.
- the power that the motor is controlled by the microcomputer control system.
- the microcomputer shifts to the standby mode, or when it is judged from the operating state of the microcomputer monitoring circuit that the operation of the microcomputer has been hindered, it is controlled by the SW control system. This makes it possible to control the motor even if the microcomputer is not operating normally.
- a standby signal may be erroneously input to the microcomputer monitoring circuit.
- the microcomputer monitoring circuit detects the standby signal even when an error occurs in the microcomputer and outputs the restart signal, so it shifts to the standby mode and is the original function. Stop monitoring the microcomputer.
- a microcomputer monitoring circuit has been proposed that prevents the transition to the standby mode even when the standby signal is detected when the restart signal is output.
- This microcomputer monitoring circuit shifts to standby mode when it detects a signal to shift to standby mode before outputting a signal to restart the microcomputer after the predetermined signal output from the microcomputer is no longer output and before outputting a signal to restart the microcomputer. I am trying to do it.
- the microcomputer monitoring circuit when an abnormality occurs in the microcomputer and the predetermined signal is no longer detected, even if the signal to shift to the standby mode is detected, the microcomputer monitoring circuit is restarted without stopping the monitoring function. It can output a signal prompting startup.
- the microcomputer is restarted while detecting an erroneous standby signal, and is output once when the microcomputer is operating normally.
- a predetermined signal is detected, it is determined that the microcomputer is operating normally, and that the standby signal is detected at this time. Then, it shifts to the standby mode, and the problem of stopping the microcomputer monitoring occurs.
- the present invention has been made in view of the above-described circumstances, and has as its object to propose a convenience monitoring device that prevents a transition to a standby mode even when a standby signal is erroneously input.
- the present invention for solving the above-mentioned problem is to output a start signal prior to the S operation of the computer, and to stop the first signal output from the started computer at a predetermined cycle for a predetermined period of time.
- Starting means for outputting a starting signal to the computer; starting / stopping means for stopping the operation of the starting means when a second signal output by the computer at a predetermined timing is input; and inputting the starting signal.
- the start signal is output by the starter S, but the computer shifts to the standby mode.
- the start-stop unit stops the operation of the start unit. Therefore, by outputting the second signal when the computer shifts to the standby mode, even if the computer shifted to the standby mode stops outputting the first signal, the computer is started by the start signal. I won't.
- the start-up operation determining means outputs the third signal when the start-up signal is input. However, when the first signal is detected when the second signal is not detected, the third signal is output. Stop output of The operation monitoring means outputs the second signal to the start / stop means by detecting the second signal. However, when the third signal is detected, the operation monitoring means outputs the second signal to the S operation stop means. Stop outputting the second signal.
- the activation means can be activated based on the first signal, and if the output of the first signal from the computer is stopped, the activation signal is output. Therefore
- the computer can be monitored. If the first signal is not input, a start signal for operating the computer normally can be output.
- the starting operation determining means detects the first signal in a state where the second signal is not detected, the output of the third signal is stopped. From the output of the operation monitoring means, it is possible to monitor whether or not the microcomputer is operating.
- the computer when the computer is operating normally, the second and third signals are not detected, and when only the second signal output from the operation monitoring means is detected, the computer is in standby key mode.
- the third signal output from the activation operation determination means it can be determined that the computer is in a restarted state.
- the present invention when the present invention is applied for monitoring a computer of a power window system, it is determined that the computer is operating normally only when the second signal or the third signal is not detected. It is sufficient to switch between the microcomputer control system and the SW control system based on this determination result.
- FIG. 2 is a schematic perspective view showing an internal structure of a driver's seat side door of the present embodiment.
- FIG. 4 (A) is a logic circuit diagram showing an example of the judgment circuit, and (B) to (D) are timing charts based on the logic circuit diagram shown in FIG. 3 (A). [Fig. 4]
- FIG. 3 is a block diagram illustrating an example of a relay control circuit.
- FIG. 1 shows the internal structure of a door 12 on the driver's seat side of the vehicle.
- a motor 14 used in the power window system 10 applied to the present embodiment is provided inside the door 12 on the driver's seat side.
- the motor 14 is connected to a wind regi yule section 16.
- a so-called wire type is used as the wind regulator section 16, and an intermediate portion of a wire (not shown) is wound around a rotating plate 14 A attached to a drive shaft of the motor 14.
- Each end of the wire is connected to a holding channel 20 that supports the lower end of the door glass 18, and the holding channel 20 is attached to the main guide 22 so as to be vertically movable. .
- the holding channel 20 moves along the main guide 22, and moves up and down (up and down) along the door glass 18 force glass guide 24.
- the configuration of the wind regulator section 16 is not limited to the wire type, but may be an X-arm type, a so-called motor self-propelled type in which the motor itself moves along the rack, or the like.
- FIG. 2 shows a control system for driving the motor 14 of the power window system 10.
- This control system includes a microcomputer (hereinafter referred to as a “microcomputer”) 30 and a control circuit 32, which are configured by connecting a CPU (not shown), a ROM, a RAM, and various interfaces through a bus.
- the control circuit 32 includes a watchdog circuit 34, a judgment circuit 36, an AND circuit 38, and a relay control circuit 40.
- the watchdog circuit 34, the judgment circuit 36, and the AND circuit 38 Constitutes a microcomputer monitoring device 28 to which the present invention is applied.
- the microcomputer 30 and the relay control circuit 40 are used to raise the door glass 18
- the SWUP signal and the SWDOWN signal are input via A and 44B, respectively.
- the microcomputer 30 controls a signal of a predetermined cycle such as a signal generated in synchronization with a click signal or the like as a first signal (hereinafter referred to as a “clock signal CKj”).
- the clock signal CK is output to the circuit 32.
- the clock signal CK is input to each of the watchdog circuit 3 and the determination circuit 36 of the control circuit 32. It comprises a start-up means, for example, a timer circuit that is reset-notched when a clog signal CK is input, and starts when the time measured by the timer circuit reaches a predetermined time and the time-up occurs.
- the reset signal RS is output from the control circuit 32 to the microcomputer 30.
- the microcomputer 30 outputs the reset signal RS
- the watchdog circuit 34 does not output the reset signal RS, but the watchdog circuit 34 starts or restarts.
- a reset signal RS is output to restart the microcomputer 30.
- the reset signal RS is a signal that switches from H level to L level.
- the microcomputer 30 outputs a standby signal st to the control circuit 32 as a second signal.
- the standby signal st is input to the determination circuit 36 and the AND circuit 38, and a signal (hereinafter referred to as a standby signal ST) corresponding to the standby signal st is output from the AND circuit 38. ', Input to the watchdog circuit 34.
- the microcomputer 30 outputs a standby signal st when shifting to the standby mode for power saving or the like, and the watchdog circuit 34 outputs a standby signal corresponding to the standby signal st from the AND circuit 38. Transition to standby mode occurs when signal ST is input.
- the watchdog circuit 34 stops the operation of the timer by shifting to the standby mode. Thus, even if the microcomputer 30 shifts to the standby mode and stops outputting the clock signal CK, the watchdog circuit 34 does not output the reset signal R S. That is, when the watchdog circuit 34 receives the standby signal ST corresponding to the standby signal st output from the microcomputer 30, the watchdog circuit 34 shifts to the standby mode and stops monitoring the microcomputer 30. It's swelling. The watchdog circuit 34 that has shifted to the standby mode resumes monitoring of the microcomputer 30 when the standby signal S corresponding to the standby signal st is stopped.
- the judgment circuit 36 provided as the starting operation judgment means of the present investigation is composed of an inverter circuit 46, an AND circuit 47, and an RS flip-flop circuit (RS-FF, Bottom "FF circuit 4 8")
- the standby signal st and the clock signal CK are input to the AND circuit 47 via the inverter circuit 46. This allows
- the AND circuit 47 outputs a set signal S to the FF circuit 48 in accordance with the clock signal CK and the standby signal st input via the inverter circuit 46.
- the reset signal R output from the watchdog circuit 34 and the reset signal R are input to the FF circuit 48. ? ?
- the circuit 48 is configured to reset the output signal Q by receiving the reset signal R.
- the reset output signal Q is the third signal. That is, as shown in FIG. 3 (B), when the set signal S is input, the determination circuit 36 holds the determination signal Q at the H level and receives the reset signal R. As a result, the determination signal Q is reset and held until the next input of the set signal S, and is output as the third signal. Further, as shown in FIG. 3 (C), the output signal Q of the FF circuit 48 is reset by the reset signal R being input again in the determination circuit 36.
- the decision circuit 36 receives the standby signal st so that the set signal S is supplied even when the clock signal CK is supplied. It is not output. At this time, when the reset signal R is input, the output signal Q is reset. For example, when the ignition switch of the vehicle (not shown) is turned on and the power supply voltage Vcc is applied, the reset signal!? Outputs S and starts microcomputer 30.
- the determination circuit 36 is reset by the reset signal R output from the watchdog circuit 34 when the supply of the power supply voltage Vcc is started. At this time, if the standby signal st is detected, the set signal S is not output even if the clock signal CK is input. As a result, the output signal Q of the determination circuit 36 is kept in the reset state.
- the AND circuit 38 provided as the operation monitoring means of the present invention includes the standby signal st output from the microcomputer 30 and the output signal of the judgment circuit 36. Q is entered.
- the microcomputer 30 when the microcomputer 30 outputs the standby signal st, the standby signal st is sent to the watchdog circuit 34 and the relay control circuit 40 in accordance with the output signal Q of the determination circuit 36. It is designed to be output as a by-signal ST.
- FIG. 3 shows an example of the relay control circuit 40.
- the relay control circuit 40 is provided with four AND circuits 50, 52, 54, and 56.
- One input terminal of each AND circuit 50-56 is provided with a microcomputer 4 UP signal output from the 0, SWUP signal UP switch SWu, the SWDOWN signal DOWN signal and D OWN Suitsuchi SW D of the microcomputer 4 0 are inputted.
- the relay control circuit 40 receives the standby signal ST output from the AND circuit 38 and the output signal Q output from the determination circuit 3 ⁇ . It is being forced.
- the standby signal ST and the output signal Q are input to the OR circuit 74.
- the output signal Q is input to the OR circuit 74 as an inverted signal via the inverter circuit 76.
- the signals output from the OR circuit 74 are input to the other input terminals of the AND circuits 52 and 56, and the output signals of the OR circuit 74 are input to the AND circuits 50 and 54.
- the signal is inverted and input by the member overnight circuit 56.
- the output terminals of the AND circuits 50 and 52 are connected to the input terminals of the OR circuit 60, respectively, and the output terminal of the OR circuit 60 is connected to the base of the transistor 62.
- the output terminals of the AND circuits 54 and 56 are connected to the input terminals of the OR circuit 64, and the output terminal of the OR circuit 6 is not connected to the base of the transistor 66.
- the signals output from the R circuits 60 and 64 drive the transistors 62 and 66.
- the standby signal ST or the signal CT obtained by inverting the output signal Q is at the H level
- the signals output from the OR circuits 60 and 64 by the outputs of the AND circuits 52 and 56 are applied to the transistor 6. 2, 66 are driven.
- Each of the transistors 62 and 66 outputs a motor UP signal and a motor DOWN signal when driven.
- the motor UP signal output from the transistor 62 is input to the relay coil 68 A of the relay 68, and the motor D ⁇ WN signal of the transistor 66 is relayed to the relay 70. It is input to the racing coil 70 A.
- the motor 14 is connected between the common terminals 68 C and 70 C of the relays 68 and 70.
- the contacts 68 B and 70 B connected to the common terminals 68 C and 70 C in the operation state of the relays 68 and 70 are connected to a battery for supplying electric power for driving the motor 14. 2 is connected to the positive terminal 72 A, and the other contact 68 D, 70 D is grounded in the same manner as the negative terminal 72 B of the notch 72.
- the relay coil 68 A of the relay 68 is excited by the motor UP signal output from the relay control circuit 40, so that the common terminal 68 (: is connected.
- the motor 14 is driven in the direction to raise the window glass 18.
- the relay coil 70A of the relay 70 is excited by the motor DOWN signal output from the relay control circuit 40
- the common terminal 70C is connected to the contact 70B, and the motor 14 Is driven down the window glass 18.
- the window system 10 can be driven when the ignition switch (not shown) of the vehicle is turned on and the power supply Vcc is supplied as the drive power.
- the watchdog circuit 34 outputs a reset signal RS when the power supply voltage Vcc is supplied.
- the microcomputer 30 is started by the reset signal RS.
- the microcomputer 30 outputs a clock signal CK at a predetermined cycle when starting to start. As a result, the watchdog circuit 34 starts monitoring the microcomputer 30.
- the decision circuit 36 when the clock signal CK is input, the decision circuit 36 outputs the set signal S, sets the reset output signal Q, and holds it at the H level.
- the output signal Q is output to the AND circuit 38 as a determination signal of the operation state of the microcomputer 30 by the determination circuit 36. That is, when the microcomputer 30 is operating normally, a predetermined determination signal is output from the determination circuit 36.
- the AND circuit 38 In the AND circuit 38, the output signal Q from the determination circuit 36 and the standby signal st from the microcomputer 30 are input.
- the AND circuit 38 outputs an L-level signal when the microcomputer 30 is not outputting the standby signal st.
- the relay control circuit 40 when the standby signal ST is being output, the relay control circuit 40 outputs the UP signal and the UP signal output from the microcomputer 30 in response to the operation of the UP switch SW U and the DOWN switch SW D. In response to the DOWN signal, AND circuits 50 and 54 switch the output. As a result, the transistors 62 and 66 are driven, and the window glass 18 is raised and lowered.
- the AND circuit 38 together with the output signal Q of the determination circuit 36 And outputs a standby signal ST corresponding to the standby signal st.
- This standby signal ST is input to the watchdog circuit 34 together with the relay control circuit 40.
- Watchdog circuit 3 4 by the standby signal ST in response to the scan evening Mumbai signal s t outputted from the microcomputer 3 0 is input, to migrate to the standby mode. As a result, power consumption can be reduced.
- the relay control circuit 40 when the standby signal ST is input, the UF signal and the DOWN signal are input from the microcomputer 30 and the outputs of the AND circuits 50 and 54 are input. Becomes L level, and the transistors 62 and 66 are driven based on the outputs of the AND circuits 52 and 56.
- the watchdog circuit 34 when the clock signal CK is not input from the microcomputer 30, the watchdog circuit 34 outputs the microcomputer 30 helicopter signal RS and outputs the clock signal from the microcomputer 30. Prompt for restart.
- the reset signal RS output from the watchdog circuit 34 is input to the determination circuit 36 as a reset signal R, and the reset signal R is input to the determination circuit 36. As a result, the output signal Q is switched to the L level and held.
- the AND circuit 38 does not output the standby signal ST irrespective of the standby signal st. That is, as shown by the two-dot chain line in FIG. 6B, even when the standby signal st is input, the clock signal CK is not input, and the output signal Q is in the reset state (L level). Will be retained.
- the reset output signal Q is also output to the relay control circuit 40, and as shown in FIG. 5, the reset output signal Q is input to the relay control circuit 40.
- the transistors 62 and 66 are driven by the outputs from the AND circuits 52 and 56 in the same manner as when the standby signal ST is input. Become so.
- the reset signal for restarting the microcomputer 30 without the watchdog circuit 34 shifting to the standby mode. It can output RS to urge the microcomputer 30 to restart.
- the relay control circuit 4 on the basis of the output signal Q of the determination circuit 3 6 inputted from the microcomputer monitoring unit 2 8, controls the direct motor 1 4 in response to the operation of the UP switch SWu and DOWN Suitsuchi SW D Switching so that no malfunction occurs.
- FIGS. 6 (C) and 6 (D) show an example in which the microcomputer monitoring device 28 detects the standby signal st when the power supply Vcc is turned on.
- the watchdog circuit 34 outputs a reset signal RS when the power supply voltage Vcc is applied, and urges the microcomputer 30 to operate. As a result, the output signal Q of the judgment circuit 36 is reset. After that, as shown in FIG.
- the watchdog circuit 34 continues resetting even if the reset signal RS is output, unless the clock signal CK is input from the microcomputer 30.
- the signal RS will be output.
- the microcomputer 30 when the microcomputer starts 30, the microcomputer 30 does not shift to the standby mode even if the standby signal st is input. Monitoring can be continued.
- the microcomputer monitoring device 28 accepts the standby signal st and shifts to the standby mode only when the microcomputer 30 is operating normally, so that the microcomputer 30 operates normally.
- the standby signal st that is erroneously input causes the watchdog circuit 34 to shift to the standby mode, preventing the microcomputer 30 from being disabled for monitoring (restarting). can do.
- the present embodiment described above shows one application example of the present invention, and does not limit the configuration and application of the present invention.
- the power window system 10 provided in the vehicle has been described by taking the driver side door I2 as an example.However, the present invention is not limited to this, and in various control systems using a computer, A computer that monitors and stops monitoring based on the first signal i output from the computer at a fixed cycle in response to a clock signal, etc., and the second signal output from the computer at a predetermined timing. It can be applied to monitoring equipment.
- the present invention even if the second signal is erroneously input, it is possible to prevent the start / stop unit from operating and the computer from being disabled from being monitored. This has an excellent effect that the computer can be reliably monitored even when the computer is started while the second signal is being input.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/308,654 US6490699B2 (en) | 1996-12-02 | 1997-12-01 | Computer monitor device |
EP97946066A EP1014269B1 (en) | 1996-12-02 | 1997-12-01 | Computer monitoring device |
DE69716489T DE69716489T2 (de) | 1996-12-02 | 1997-12-01 | Rechnermonitor-vorrichtung |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8/322017 | 1996-12-02 | ||
JP32201796A JP3234787B2 (ja) | 1996-12-02 | 1996-12-02 | コンピュータ監視装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998025206A1 true WO1998025206A1 (fr) | 1998-06-11 |
Family
ID=18139001
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1997/004382 WO1998025206A1 (fr) | 1996-12-02 | 1997-12-01 | Dispositif de controle pour ordinateur |
Country Status (6)
Country | Link |
---|---|
US (1) | US6490699B2 (ja) |
EP (1) | EP1014269B1 (ja) |
JP (1) | JP3234787B2 (ja) |
KR (1) | KR100438687B1 (ja) |
DE (1) | DE69716489T2 (ja) |
WO (1) | WO1998025206A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10049441B4 (de) * | 2000-10-06 | 2008-07-10 | Conti Temic Microelectronic Gmbh | Verfahren zum Betrieb eines von einem Prozessor gesteuerten Systems |
US6892332B1 (en) * | 2001-11-01 | 2005-05-10 | Advanced Micro Devices, Inc. | Hardware interlock mechanism using a watchdog timer |
DE10255430A1 (de) * | 2002-11-28 | 2004-06-09 | Conti Temic Microelectronic Gmbh | Verfahren zur Reduzierung des Stromverbrauchs eines Mikroprozessors mit Watchdog-Schaltung |
CN1293474C (zh) * | 2003-04-30 | 2007-01-03 | 松下电器产业株式会社 | 微计算机 |
US7321213B2 (en) * | 2005-07-20 | 2008-01-22 | Asmo Co., Ltd. | Motor controller |
JP4818847B2 (ja) * | 2005-11-07 | 2011-11-16 | アスモ株式会社 | モータ制御装置 |
KR20210143535A (ko) * | 2020-05-20 | 2021-11-29 | 주식회사 엘지에너지솔루션 | 릴레이 제어 장치 및 방법 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0561726A (ja) * | 1991-03-07 | 1993-03-12 | Mazda Motor Corp | 故障検出装置 |
JPH05189272A (ja) * | 1992-01-16 | 1993-07-30 | Honda Motor Co Ltd | コントローラ |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS5775335A (en) * | 1980-10-27 | 1982-05-11 | Hitachi Ltd | Data processor |
US4698748A (en) * | 1983-10-07 | 1987-10-06 | Essex Group, Inc. | Power-conserving control system for turning-off the power and the clocking for data transactions upon certain system inactivity |
JPS61296443A (ja) | 1985-06-24 | 1986-12-27 | Mitsubishi Electric Corp | ウオツチドツグ・タイマ |
US5175845A (en) * | 1988-12-09 | 1992-12-29 | Dallas Semiconductor Corp. | Integrated circuit with watchdog timer and sleep control logic which places IC and watchdog timer into sleep mode |
US5278976A (en) * | 1990-04-16 | 1994-01-11 | Rolm Company | Method for detecting infinite loops by setting a flag indicating execution of an idle task having lower priority than executing application tasks |
US5237698A (en) * | 1991-12-03 | 1993-08-17 | Rohm Co., Ltd. | Microcomputer |
US5416726A (en) * | 1992-10-06 | 1995-05-16 | Microsoft Corporation | Method and system for placing a computer in a reduced power state |
US5704038A (en) * | 1994-09-30 | 1997-12-30 | Itt Automotive Electrical Systems, Inc. | Power-on-reset and watchdog circuit and method |
US5649098A (en) * | 1995-11-14 | 1997-07-15 | Maxim Integrated Products | Methods and apparatus for disabling a watchdog function |
JPH09160807A (ja) * | 1995-12-06 | 1997-06-20 | Mitsuba Corp | マイクロプロセッサの誤動作検出方法 |
JP3462048B2 (ja) * | 1996-08-30 | 2003-11-05 | 株式会社東海理化電機製作所 | コンピュータ監視装置及びパワーウィンドウシステム |
-
1996
- 1996-12-02 JP JP32201796A patent/JP3234787B2/ja not_active Expired - Fee Related
-
1997
- 1997-12-01 DE DE69716489T patent/DE69716489T2/de not_active Expired - Lifetime
- 1997-12-01 US US09/308,654 patent/US6490699B2/en not_active Expired - Lifetime
- 1997-12-01 WO PCT/JP1997/004382 patent/WO1998025206A1/ja active IP Right Grant
- 1997-12-01 KR KR10-1999-7004383A patent/KR100438687B1/ko active IP Right Grant
- 1997-12-01 EP EP97946066A patent/EP1014269B1/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0561726A (ja) * | 1991-03-07 | 1993-03-12 | Mazda Motor Corp | 故障検出装置 |
JPH05189272A (ja) * | 1992-01-16 | 1993-07-30 | Honda Motor Co Ltd | コントローラ |
Non-Patent Citations (1)
Title |
---|
See also references of EP1014269A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPH10161910A (ja) | 1998-06-19 |
DE69716489D1 (de) | 2002-11-21 |
US20020152433A1 (en) | 2002-10-17 |
EP1014269A1 (en) | 2000-06-28 |
EP1014269B1 (en) | 2002-10-16 |
EP1014269A4 (en) | 2000-10-18 |
US6490699B2 (en) | 2002-12-03 |
KR20000053356A (ko) | 2000-08-25 |
JP3234787B2 (ja) | 2001-12-04 |
KR100438687B1 (ko) | 2004-07-02 |
DE69716489T2 (de) | 2003-07-17 |
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