WO1998027798A1 - Carte a circuit imprime et procede de fabrication - Google Patents
Carte a circuit imprime et procede de fabrication Download PDFInfo
- Publication number
- WO1998027798A1 WO1998027798A1 PCT/JP1997/004684 JP9704684W WO9827798A1 WO 1998027798 A1 WO1998027798 A1 WO 1998027798A1 JP 9704684 W JP9704684 W JP 9704684W WO 9827798 A1 WO9827798 A1 WO 9827798A1
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- WO
- WIPO (PCT)
- Prior art keywords
- layer
- printed wiring
- wiring board
- conductor
- film
- Prior art date
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/10—Methods of surface bonding and/or assembly therefor
- Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
- Y10T156/1056—Perforating lamina
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
- Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- the present invention relates to a printed wiring board and a method for manufacturing the same, and more particularly to a method for suppressing the occurrence of cracks during a heat cycle and roughening an interlayer insulating layer without reducing the peel strength.
- the present invention relates to a printed wiring board capable of preventing the dissolution of a generated conductor circuit and a method for manufacturing the same. Background technology
- This build-up multilayer wiring board is manufactured, for example, by the method disclosed in Japanese Patent Publication No. 55555/1992. That is, an insulating material made of a photosensitive electroless plating adhesive is applied on a core substrate, and dried and exposed and developed to form a layer having an opening for a bi-directional hole. After the surface of the interlayer insulating material layer is roughened by treatment with an oxidizing agent or the like, a plating resist is provided on the roughened surface, and then electroless plating is applied to a portion where no resist is formed. By forming a via hole and a conductor circuit by performing the above steps, and repeating such a process a plurality of times, a multilayered build-up wiring board can be obtained.
- the conductor circuit is provided in the portion where the resist is not formed, and the plating resist remains in the inner layer.
- 6-283860 discloses that a plating resist of an inner layer is removed, a roughened layer made of copper-nickel-phosphorus is provided on the surface of a conductor circuit made of an electroless plating film, and the layer R 1 is separated. Prevention techniques are disclosed.
- a method of removing a plating resist by using a so-called semi-additive method can be considered.
- the semi-additive method since the conductor circuit is composed of an electroless plating film and an electrolytic plating film, when the interlayer resin insulating layer surface is roughened, the surface portion of the conductor circuit composed of the electrolytic plating film is roughened. There was a problem that it was dissolved by a local battery reaction. On the other hand, in order to mount an IC chip on a printed wiring board, it is necessary to form a solder bump on the wiring board.
- a printing mask such as a metal mask or a plastic mask and a printed wiring board are respectively provided with a conductive layer for positioning the printing mask and the printed wiring board.
- a method is to form an alignment mark in advance, align the two alignment marks so that the printing mask and the printed wiring board are laminated at a predetermined position, and then print the cream solder.
- the printed wiring board is coated with a solder resist layer having openings for alignment marks or pads for forming solder bumps.
- the substrate warps due to the difference in the coefficient of thermal expansion between the IC chip and the resin insulating layer during a heat cycle, and the solder resist layer and the conductive layer (alignment mark) are warped. And solder bump formation pads), there is no close contact, stress is concentrated on these interfaces, and cracks originating from these interfaces are generated in the solder-resist layer, There was a problem of separation.
- the present invention has been made to solve the above-mentioned problems of the prior art. Its main purpose is to reduce other properties, especially the peel strength of the conductor (adhesion between the conductor circuit and the interlayer insulating layer, adhesion between the via hole and the lower conductor circuit, or adhesion between the conductor layer and the solder resist layer).
- An object of the present invention is to provide a printed wiring board that can effectively prevent insulation between layers, cracks in an edge layer, and separation between layers without occurring during a heat cycle.
- Another object of the present invention is to provide a printed wiring board in which the surface of the conductive circuit is prevented from being melted by the local battery reaction at the same time.
- Still another object of the present invention is to provide a method for advantageously producing such a printed wiring board. Disclosure of the invention
- the inventors of the present invention have intensively studied for realizing the above object, and as a result, have conceived an invention having the following content as a gist.
- a printed wiring board according to the present invention is a multilayer printed wiring board in which an interlayer insulating layer is formed on a conductive circuit of a substrate, wherein the conductive circuit includes an electroless plating film. It is made of an electrolytic plating film, and has a roughened layer provided on at least a part of its surface.
- the printed wiring board of the present invention is a multilayer printed wiring board in which an interlayer insulating layer is formed on a conductive circuit of a substrate, wherein the conductive circuit includes an electroless plating film.
- a roughened layer is provided on at least a part of the surface of the electroplated film, and the surface of the roughened layer is covered with a layer of a metal or a noble metal having a higher ionization tendency than titanium and not more than titanium.
- the conductor circuit may be provided with a roughening layer on at least a part of a surface including a side surface, or at least a part of the side surface.
- a roughened layer is provided, and the roughened layer is preferably made of an alloy of copper, nickel, and phosphorus.
- the method of manufacturing a printed wiring board according to the present invention comprises the steps of: providing an electroless plating on a substrate; providing a plating resist; performing an electrolytic plating; removing the plating resist; The electroless plating film is removed by etching to form a conductor circuit consisting of an electroless plating film and an electroplating film, and a roughened layer is formed on at least a part of the surface of the conductor circuit, and then an interlayer insulating layer is provided. It is characterized by having multiple layers.
- the electroless plating is performed on the substrate, the plating resist is provided, the electrolytic plating is performed, and then, the plating resist is removed.
- the electroless plating film under the resist is removed by etching to form a conductor circuit composed of the electroless plating film and the electrolytic plating film.
- a roughened layer is formed on at least a part of the conductor circuit surface, and the roughened layer is formed. It is characterized in that the surface of the oxide layer is covered with a layer of a metal or a noble metal whose ionization tendency is larger than that of copper and is equal to or less than titanium, and then a multi-layer structure is provided by providing an interlayer insulating layer.
- the roughened layer is preferably formed by copper-nickel-lin alloy plating.
- the printed wiring board of the present invention comprises an interlayer insulating layer formed on a substrate provided with a lower conductive circuit, and an upper conductive circuit formed on the interlayer insulating layer.
- the via hole includes an electroless plating film and an electrolytic plating film, and the lower conductor circuit is connected to at least the via hole. It is characterized in that a roughened layer is formed on the surface of the portion to be changed.
- the roughening layer is made of an alloy of copper and copper alloy.
- the method for manufacturing a printed wiring board according to the present invention includes the steps of: forming a lower conductive circuit on a substrate; providing a roughened layer on at least a portion of the surface of the lower conductive circuit that is connected to the via hole; After forming an insulating layer, an opening for a via hole is formed in the interlayer insulating layer, and electroless plating is performed on the interlayer insulating layer. Then, a plating resist is provided and electrolytic plating is performed. After the resist is removed, the electroless plating film under the resist is removed by etching to form an upper conductor circuit composed of the electroless plating film and the electrolytic plating film and a via hole to form a multilayer structure.
- the roughened layer is preferably formed by copper-nickel-phosphorus alloy plating.
- the conductor layer in the printed wiring board provided with a conductor layer used as an alignment mark, is provided with a roughened layer on at least a part of its surface. It is characterized by. .
- the conductor layer preferably comprises an electroless plating film and an electrolytic plating film.
- a printed wiring board according to the present invention is a printed wiring board provided with a conductive layer used as an alignment mark, wherein the conductive layer comprises an electroless plating film and an electrolytic plating film. .
- the conductor layer is preferably provided with a roughened layer on at least a part of the surface.
- the alignment mark is formed by an opening exposing only the surface of the conductor layer from a solder resist layer formed on the conductor layer.
- a metal layer made of nickel-gold is formed on the conductor layer exposed from the opening.
- the alignment mark is used for positioning a print mask, mounting an IC chip, or replacing a printed wiring board on which a semiconductor element is mounted with another printed wiring board. It is preferred that it be used for alignment when mounting on a device.
- FIGS. 21 to 40 are views showing each manufacturing process of the printed wiring board in the fifth embodiment.
- FIG. 41 is a partial cross-sectional view showing an alignment mark formed of a conductor layer used for positioning with a print mask and mounting an IC chip.
- FIG. 42 is a partial cross-sectional view showing an alignment mark composed of a conductor layer used for alignment when mounting a printed wiring board on which a semiconductor element is mounted on another printed wiring board.
- FIG. 43 is a plan view of the printed wiring board.
- reference numeral 1 in the figure is a substrate
- 2 is an interlayer resin insulating layer (adhesive layer for electroless plating)
- 2a is an insulating layer
- 2b is an adhesive layer
- 3 is a plating resist
- 4 is an inner conductor.
- Circuit inner layer copper pattern
- 5 outer layer conductor circuit outer layer copper pattern
- 6 is via hole opening
- 7 is via hole (BVH)
- 8 is copper foil
- 9 is through hole
- 10 is filled resin (resin filled)
- 11 is a roughened layer
- 12 is an electroless copper plating film
- 13 is an electrolytic copper plating film
- 14 is a solder resist layer
- 15 is a nickel plating layer
- 16 is a gold plating layer
- 17 is a gold plating layer.
- Solder bumps, 18 are alignment marks (rank with printing masks) 19 is an alignment mark (used for positioning of IC chip mounting), 20 is an alignment mark (for mounting a printed circuit board on which a semiconductor element is mounted on another printed circuit board). 21 is a pad for forming solder bumps, and A is a product part.
- the conductor circuit is composed of an electrolytic plating film and an electroless plating film, an electroless plating film is formed on the inner layer side, and an electrolytic plating film is formed on the outer layer side. (See the enlarged figures in Figures 18 and 19). With this configuration, the conductor circuit has a softer and more malleable electroplating film than an electroless plating film, so even if the substrate warps during a heat cycle, the size of the upper interlayer resin insulation layer can be reduced. Be able to follow changes.
- the conductor circuit is firmly adhered to the upper interlayer resin insulation layer, and the dimensions of the interlayer resin insulation layer are increased. The change has made it easier to follow.
- providing a roughened layer on at least the side surface of the conductor circuit is advantageous in that cracks generated in the interlayer resin insulation layer from the interface between the side surface of the conductor circuit and the interlayer resin in contact therewith can be suppressed during a heat cycle. It is.
- the via hole is composed of an electrolytic plating film and an electroless plating film, and an electroless plating film is formed on the inner layer side and an electrolytic plating film is formed on the outer layer side.
- the via hole is softer and more malleable than the electroless plated film, so even if the substrate is warped during a heat cycle, the via hole is formed due to the dimensional change of the interlayer resin insulating layer. Be able to follow.
- the via hole in the printed wiring board of the present invention has a harder inner layer side. It is composed of an electroless plating film, and since this electroless plating film is in close contact with the lower conductive circuit via the roughened layer, there is no separation from the lower conductive circuit during a heat cycle. The reason for this is that the metal layer to which the roughening layer bites is a harder electroless plating film, so that the metal layer is less likely to be broken when a force of shear is applied.
- the via hole is composed only of the electrolytic plating film
- the electrolytic plating film itself is soft and detaches due to the heat cycle even if it is in close contact with the lower conductive circuit via the roughening layer.
- the via hole is formed only of the electroless plating film, it cannot respond to the dimensional change of the interlayer resin insulating layer, and cracks occur in the interlayer resin insulating layer on the via hole.
- the via hole is formed by an electrolytic plating film and an electroless plating film, and the via hole is connected to the lower conductive circuit via the roughened layer, so At the time of cycling, cracks generated in the interlayer resin insulation layer on the via hole and separation between the via hole and the lower conductor circuit can be prevented at the same time.
- the interlayer resin insulating layer is roughened, the harder the film to be embedded into the roughened layer, the better. The reason for this is that when a force is applied, destruction is less likely to occur at the plating film.
- a roughened layer may be provided on the via hole surface.
- the reason is that the via hole adheres firmly to the upper interlayer resin insulation layer, and the via hole more easily follows the dimensional change of the interlayer resin insulation layer.
- the roughened layer of the lower conductor circuit may be formed not only at the portion connected to the via hole, but also over the entire lower conductor circuit. The reason is that the adhesion to the interlayer insulating layer is improved in the same manner as in the configuration (1).
- the lower conductive circuit to which the via hole connects is composed of an electrolytic plating film and an electroless plating film, and an electroless plating film is formed on the inner layer side and on the outer layer side. It is desirable that an electrolytic plating film is formed. For this reason Because the inner layer side of the lower conductor circuit comes into close contact with the interlayer resin insulation layer, a harder electroless plating film is desirable to secure the peel strength, and the other side is connected to the via hole. It is desirable to have an electroplating film that is excellent in following up dimensional changes.
- the printed wiring board of the present invention can be used for positioning a print mask or for mounting a semiconductor chip on a package board. It is characterized in that a roughened layer is formed on at least a part of the surface of a conductor layer that serves as an alignment mark used for mounting on a board (see an enlarged view of FIG. 41).
- the solder resist layer When the periphery of the conductive layer is covered with the solder resist layer (that is, when only the conductive layer is exposed from the opening of the solder resist layer), the solder resist layer does not separate, and is used as an alignment mark. Function does not decrease.
- the printed wiring board of the present invention can be used as an alignment mark to be used for positioning with a print mask or mounting an IC chip.
- the conductor layer that serves as the alignment mark used for mounting on the board is composed of an electroless plating film and an electrolytic plating film, with the electroless plating film formed on the inner layer side and the electrolytic layer on the outer layer side.
- the feature is that a plating film is formed (see the enlarged view of FIG. 41).
- the conductor layer has a softer and more malleable electroless plating film than an electroless plating film. Therefore, even if the substrate is warped during a heat cycle, the upper solder-resist layer is formed. It becomes possible to follow a dimensional change. Moreover, when a roughened layer is provided on the surface of the conductor layer, the conductor layer is firmly adhered to the upper solder resist layer, and is easily followed by a dimensional change of the solder resist layer. Also, since the conductor on the side in contact with the interlayer insulating layer is an electroless plating film, its hardness is high and the peel strength can be increased.
- providing a roughened layer on at least the side surface of the conductor layer is not suitable for heat-sizing. This is advantageous in that cracks generated in the solder resist layer and the like starting from the interface between the side surface of the conductor layer and the solder-resist layer in contact therewith can be suppressed.
- a metal layer made of nickel gold is further formed on the conductor layer exposed from the opening serving as the alignment mark.
- the reason for this is that gold has a high reflectivity and thus functions as an alignment mark.
- Nickel The metal layer made of gold can be formed by electroless plating.
- the nickel layer is formed by a nickel plating film with a thickness of 5 m
- the gold layer is a flash plating film with a thickness of 0.1 lm.
- it is formed by a metal plating film having a thickness of 0.5 ⁇ m.
- the printed wiring board is composed of a first-layer conductor circuit 4 and an interlayer insulating material (adhesive layer for electroless plating) 2 on an insulating substrate 1 as shown in FIG. 41, for example.
- a semi-additive method is used to form a solder bump forming pad (conductor pattern) 21 which is a part of the second-layer conductive circuit and an alignment pattern for positioning with the printing mask. Solder for protecting parts other than the alignment marks 18 and 19 and the pad 21 for forming solder bumps.
- the resist layer 14 is formed.
- the alignment mark 18 for positioning with the printing mask is formed in a portion near the outer periphery of the printed wiring board and where no conductor pattern is formed.
- the alignment mark 19 used for mounting the IC chip can be mounted on the IC chip without being affected by the effect.
- the portion near the outer periphery means the outer portion of the product part A as described above.
- the alignment mark 19 used for mounting the IC chip is formed for each product piece of the printed wiring board in order to mount the IC chip on each product piece.
- package semiconductor devices When a substrate is used, an alignment mark 20 used to mount this package substrate on another printed wiring board is formed on the innermost side as shown in FIG.
- the alignment mark 20 is desirably a cross as shown in FIG. When the cross shape is adopted, the opening of the solder resist layer is provided so as to cover the periphery of the cross. This license mark is also provided for each product.
- the alignment marks 18 and 19 are preferably formed by openings that expose only the surface of the conductor layer from the solder resist layer formed on the conductor layer (including via holes). The reason is that, as shown in FIG. 41, the periphery of the conductor layer overlaps with the solder-resist layer, so that the conductor can be suppressed by the solder-resist and the separation of the conductor can be prevented. In addition, cracks generated due to a difference in coefficient of thermal expansion during a heat cycle can be suppressed from the contact boundary between the conductor layer and the interlayer resin insulation layer.
- the alignment mark 18 for positioning with the print mask has the following effects.
- the opening in the solder resist layer is formed by exposing and developing a photomask placed thereon, but if the photomask is displaced, the opening position will also be displaced. If the conductor layer of the alignment mark is completely exposed, the camera recognizes the center of the conductor as the center position of the alignment mark and cannot recognize the displacement of the opening of the solder-resist layer. For this reason, since the opening of the printing mask and the opening of the solder resist layer do not coincide with each other, the opening area of the printing mask is reduced by the solder resist layer, and the height of the solder bump is reduced.
- the camera recognizes the center of the conductor layer exposed from the opening as the center of the alignment mark. Open one resist layer Even if the photomask is shifted and the opening position of the solder resist layer is shifted, the alignment mark is also shifted by the same amount in the same direction as the shift amount. The openings in the resist layer match, and the solder-resist layer does not reduce the opening area and does not reduce the height of the solder bumps.
- solder bump forming pad (conductor pattern) 21 may be covered with the periphery of the opening of the solder resist layer, or may be completely exposed from the opening.
- the inner layer side of the conductor is made of an electroless plating film that is harder than the electrolytic plating film. It does not lower the peel strength. The reason for this is that the peel strength is measured on the side that comes into contact with the interlayer insulating layer located on the inner layer side of the conductor circuit. (If an adhesive for electroless plating is used as the interlayer insulating agent, This is because the greater the hardness of the part to be formed, the greater the hardness.
- the printed wiring board of the present invention even when an IC chip is mounted thereon and subjected to a heat cycle test of 55 to 125 t, does not cause cracks in the interlayer resin insulation layer starting from the conductor circuit or via hole.
- the printed wiring board having the above configuration (1) to (4) can be easily manufactured according to the manufacturing method (semi-dative method) of the present invention described later.
- the roughened layer on the conductor circuit surface, via hole surface, or conductor layer surface serving as an alignment mark is a roughened surface of copper formed by etching, polishing, oxidation, oxidation-reduction, or plating. It is desirable that the roughened surface of the plating film formed by this method be used.
- this roughened layer is desirably an alloy layer made of copper-nickel-phosphorus. Good. The reason for this is that this alloy layer is a needle-like crystal layer and has excellent adhesion to the solder resist layer. Further, since this alloy layer is electrically conductive, it does not need to be removed even if a solder body is formed on the pad surface.
- composition of this alloy layer is desirably 90 to 96 wt%, 1 to 5 wt%, and 0.5 to 2 wt% in terms of copper, nickel, and phosphorus, respectively. This is because these compositions have a needle-like structure.
- a solution of an oxidizing agent composed of sodium chlorite, sodium hydroxide, and sodium phosphate it is preferable to use a solution of an oxidizing agent composed of sodium chlorite, sodium hydroxide, and sodium phosphate.
- the roughened layer is immersed in a solution of a reducing agent composed of sodium hydroxide and sodium borohydride.
- the roughened layer on the surface of the conductor circuit formed in this way has a thickness of 0.5 to 10 m, more preferably 0.5 to 7 m. The reason for this is that if it is too thick, the roughened layer itself will be damaged, and if it is too thin, the adhesion will decrease.
- the electroless plating film constituting the conductor circuit has a thickness of 0.1 to 5 mm, more preferably 0.5 to 3 mm.
- the reason for this is that if the thickness is too thick, the ability to follow the interlayer resin insulation layer will be reduced, while if it is too thin, the peel strength will be reduced, and the electrical resistance will increase when electroplating is performed. This is because the thickness of the film varies.
- the thickness of the electrolytic plating film constituting the conductor circuit is preferably 5 to 30 / m, more preferably 10 to 20 m. The reason for this is that if it is too thick, the peel strength will be reduced, and if it is too thin, the ability to follow the green layer of the interlayer resin will decrease. It is. .
- the conductor circuit is composed of the electroless plating film and the electrolytic plating film, and the roughened layer formed on the surface of the conductor circuit mainly contacts the electrolytic plating film.
- This electroplating film is more easily dissolved by the local battery reaction than the electroless plating film, so that when the roughened layer and the local battery are formed, they are rapidly dissolved, and as a result, a large surface Holes are easier to open. Therefore, in the present invention, it is particularly desirable to coat the surface of the roughened layer with a layer of a metal or a noble metal having an ionization tendency larger than that of copper and not more than titanium, and the present invention has another feature in this point.
- Metals whose ionization tendency is greater than copper and less than titanium are selected from titanium, aluminum, aluminum, iron, aluminum, aluminum, titanium, nickel, tin, lead, and bismuth. There is at least one of them.
- the noble metal includes at least one selected from gold, silver, platinum, and palladium.
- These metal or noble metal layers cover the roughening layer and can prevent dissolution of the conductor circuit due to local battery reactions that occur when roughening the interlayer insulating layer.
- these metal or noble metal layers have a thickness of 0.1 to 2 im.
- tin is preferred. This tin is advantageous because it can form a thin layer by electroless displacement plating and can follow the roughened layer.
- a roughened layer is formed on at least a side surface of the conductor circuit.
- the reason for this is that the cracks that occur in the interlayer resin insulation layer due to the heat cycle are caused by poor adhesion between the side surfaces of the conductor circuit and the resin insulation layer. This is because cracks that occur in the interlayer resin insulation layer starting from the interface between the side surface and the resin insulation layer can be prevented.
- This adhesive for electroless plating is composed of heat-resistant resin particles soluble in a cured acid or oxidizing agent dispersed in an uncured heat-resistant resin that becomes hardly soluble in an acid or oxidizing agent by the curing treatment. What is done is the best.
- the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus pot-shaped anchor can be formed on the surface.
- the heat-resistant resin particles which have been cured include: 1) a heat-resistant resin powder having an average particle diameter of 10 m or less, and 2) a heat-resistant resin powder having an average particle diameter of 2 ⁇ m or less.
- Heat resistance of 1 to 0.8 um It is preferable to use at least one selected from the group consisting of a heat-resistant resin powder and a heat-resistant resin powder having an average particle diameter of more than 0.8 ⁇ and an average particle diameter of less than 2 m. These can form more complex anchors.
- a wiring board having an inner copper pattern formed on the surface of a core board is manufactured.
- the copper pattern of this wiring board can be obtained by etching a copper-clad laminate or by bonding it to a board such as a glass epoxy board, polyimide board, ceramic board, or metal board for electroless plating.
- a method of forming a body circuit A method of forming a body circuit).
- a roughened layer made of copper nickel lin is formed on the surface of the copper pattern of the wiring board.
- This roughened layer is formed by electroless plating.
- the crystal structure of the film deposited in this range-1 structure becomes a needle-like structure, so
- a complexing agent or an additive may be added to the electroless plating solution in addition to the above compounds.
- Other methods for forming the roughened layer include the above-described oxidation-reduction treatment and a method of forming a roughened surface by etching the copper surface along grain boundaries.
- a through hole is formed in the core substrate, and the wiring layer on the front surface and the back surface can be electrically connected via the through hole.
- resin may be filled between the through-holes and the conductor circuits of the core substrate to ensure smoothness (see FIGS. 1 to 4).
- an interlayer resin insulating layer is formed on the wiring board manufactured in (1).
- the adhesive layer is exposed and developed and then heat-cured, and in the case of a thermosetting resin, the adhesive layer is heat-cured and then laser-processed.
- An opening for forming a by-pass hole is provided at the end (see Fig. 6).
- the epoxy resin particles present on the surface of the cured adhesive layer are dissolved and removed with an acid or an oxidizing agent, and the surface of the adhesive layer is roughened (see FIG. 7).
- the acid include phosphoric acid, hydrochloric acid, sulfuric acid, and organic acids such as formic acid and acetic acid. It is particularly preferable to use an organic acid. This is because the metal conductor layer exposed from the via hole is hardly corroded when the roughening treatment is performed. On the other hand, it is desirable to use chromic acid or permanganate (such as potassium permanganate) as the oxidizing agent.
- a noble metal ion or a noble metal colloid for providing the catalyst nucleus.
- a noble metal ion or a noble metal colloid is used. It is desirable to perform a heat treatment to fix the catalyst core. Such touch
- the thickness of the electroless plating film is 0.1 to 5 ⁇ m, more preferably 0.5 to 3 0 ⁇ .
- a plating resist is formed on the electroless plating film (see FIG. 9).
- the plating resist composition it is particularly desirable to use a composition comprising an acrylate of a cresol novolac phenol novolac type epoxy resin and an imidazole curing agent, but other commercially available products can also be used.
- the thickness of the electrolytic plating film is preferably 5 to 30.
- the electroless plating film under the resist is dissolved and removed with a mixture of sulfuric acid and hydrogen peroxide or an etching solution such as sodium persulfate and ammonium persulfate. Use an independent conductor circuit (see Fig. 11).
- a roughened layer is formed on the surface of the conductor circuit (see FIG. 12).
- the method of forming the roughened layer includes an etching process, a polishing process, a redox process, There is a plating process.
- Oxidation reduction treatment among these treatments NaOH (10g / 1), aC10 2 (40 g / 1), a 3 P0 4 (6 g / 1) the oxidation bath (blackening bath), aDH (lOgZ l) , ABH 4 (5 g / 1) was used as the reducing bath.
- the roughened layer made of the copper-nickel-phosphorus alloy layer is formed by deposition by electroless plating.
- the electroless plating solution for this alloy includes copper sulfate 1-40 gZ1, nickel sulfate 0.1-6.0 g / 1. citric acid 10-20 gZl, hypophosphite 10-100 gZl, boric acid 10- It is desirable to use a plating bath having a liquid composition of 40 g Z 1 and a surfactant of 0.01 to 1 g g Z 1.
- the surface of the roughened layer with a layer of a metal or a noble metal having an ionization tendency larger than that of copper and equal to or less than titanium, if necessary.
- tin use tin borofluoride or tin thiourea liquid. At this time, a Sn layer of about 0.1 to 2 m is formed by the substitution reaction of Cu—Sn.
- a method such as sputtering and vapor deposition can be adopted.
- an adhesive layer for electroless plating is formed on the substrate as an interlayer resin insulating layer (see FIG. 13).
- steps (3) to (8) are repeated to provide a further upper layer conductor circuit (see FIGS. 14 to 17).
- a roughened layer may be formed on the surface of the conductor circuit in the same manner as in the above (9), and particularly, the roughened layer is formed on the surface of the conductor layer serving as an alignment mark or a pad for forming a solder bump.
- a layer is formed.
- a solder resist composition is applied to the surface of the wiring board thus obtained, and after drying the coating film, a photomask film having an opening drawn thereon is placed on the coating film. Exposure and development processing, the solder in the conductor circuit An opening is formed by exposing a conductor layer serving as a bump portion, a head portion, and an alignment mark.
- the opening diameter of the opening of the solder bump forming pad portion may be larger than the pad diameter to completely expose the pad, or conversely, smaller than the pad diameter. Then, the periphery of the pad may be covered with a solder resist.
- the conductor layer which is to be the alignment mark, covers the peripheral green portion with the solder resist without completely exposing it from the opening of the solder resist layer.
- solder transfer method a solder foil is bonded to a pre-preda and the solder foil is etched leaving only a portion corresponding to the opening to form a solder pattern to form a solder carrier film.
- a rear film is coated with flux at the solder-resist opening of the substrate, then laminated so that the solder pattern contacts the pad, and heated to transfer it.
- the printing method is a method in which a metal mask provided with a through hole at a position corresponding to a pad is placed on a substrate, and a solder paste is printed and heated.
- An inner layer copper pattern 4 and through holes 9 were formed on both sides of the substrate (see Fig. 2). Further, the space between the conductor circuits 4 and the inside of the through holes 9 were filled with bisphenol F-type epoxy resin (see FIG. 3).
- Via holes are drawn on both sides of the substrate on which the adhesive layer 2 is formed in (4).
- the photomask film thus obtained was placed and exposed to ultraviolet light.
- the exposed substrate was spray-developed with a DMTG (triethylene glycol dimethyl ether) solution to form openings in the adhesive layer that would be 100 ⁇ 0 via holes. Furthermore, exposed with 3000MJZcm 2 the substrate at ultra-high pressure mercury lamp, for 1 hour at 100 ° C, then more to heat treatment at 5 hours at 0.99 ° C, excellent dimensional accuracy corresponding to the Photo mask film opening to form an adhesive layer 2 having a thickness of 50 ⁇ m with (Baiaho one Le forming opening 6) (see FIG. 6) c Note that the opening 6 serving as Baiahoru is partially exposed Arakaso 1.1 Let it.
- DMTG triethylene glycol dimethyl ether
- the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide.
- a 18 m-thick conductor circuit (including via hole 7) 5 composed of an electrolytic copper plating film 12 and an electrolytic copper plating film 13 was formed (see FIG. 11).
- the viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL B-type) with rotor No. 4 at 60 rpm and rotor No. 3 at 6 rpm.
- the solder resist composition was applied to the wiring board obtained in the above (14) in a thickness of 20 m.
- a photomask film was placed, exposed to ultraviolet light of 100 mJZcm 2 and subjected to DMTG development processing.
- the solder resist was heat treated under the conditions of 8 (1 hour at TC, 1 hour at 100 ° C, 1 hour at 120 ° C, and 3 hours at 150 ° C, and the pad was opened (opening diameter 200 m).
- a layer (thickness: 20 m) 14 was formed.
- the substrate on which the solder-resist layer 14 was formed was placed on an electroless nickel plating solution having a pH of 5 consisting of 30 g of nickel chloride, 10 g of sodium hypophosphite, and 10 g of sodium citrate. Then, the nickel plating layer 15 having a thickness of 5 ⁇ m was formed in the opening. In addition, the substrate was cleaned with 2 gZ1 of potassium gold chloride, 75 gZ1 of ammonium chloride, 50 gZ1 of sodium citrate, A gold plating layer 16 having a thickness of 0.03 m was formed on the nickel plating layer 15 by immersion in an electroless plating solution composed of sodium phosphate 10gZ1 at 93 ° C for 23 seconds. (18) Then, a solder paste was printed in the opening of the solder resist layer and reflowed at 200 ° C. to form a solder bump 17, thereby producing a multilayer printed wiring board having the solder bump 17.
- a multilayer printed wiring board having solder bumps was manufactured in the same manner as in Example 1, except that the roughening of the conductor circuit was performed by etching. At this time, an etching solution having a trade name of “Durabond” manufactured by MEC was used.
- a multilayer printed wiring board having solder bumps was manufactured in the same manner as in Example 1 except that the roughening of the conductor circuit was performed by etching. At this time, an etching solution having a trade name of "Durabond" manufactured by Mec was used. Also, a 0.5 ⁇ m thick Au layer was sputtered on the roughened layer surface.
- Imidazole curing agent Shikoku Chemicals, 2B4MZ-CN 2 parts by weight, photoinitiator (Ciba Geigy, Irgacure I 907) 2 parts by weight, photosensitizer (Nippon Kayaku, DBT) (S) 0.2 parts by weight and 1.5 parts by weight of NMP were mixed with stirring.
- Midazole curing agent manufactured by Shikoku Chemicals, CN
- photoinitiator manufactured by Ciba Geigy, Irgacure I 907
- photosensitizer manufactured by Nippon Kayaku, DBTX S
- 2Imidazole curing agent (Shikoku Chemicals, 2B4MZ CN) 6.5 parts by weight.
- Na 3 P0 4 (6 g / 1) as a reducing bath, NaOH (10g / 1), by a redox treatment using NaBl (6 g / 1), roughening the surface of the inner layer copper pattern 4 and the through-hole 9 Layer 11 was provided (see Figure 22).
- the resin filler 10 is applied to both sides of the substrate using a roll coater to fill the space between the conductor circuits 4 or in the through holes 9 and is dried at 70 ° C for 20 minutes. Similarly, the other surface was filled with the resin filler 10 between the conductor circuits 4 or in the through holes 9 and dried by heating at 70 ° C. for 20 minutes (see FIG. 23).
- the surface layer of the resin filler 10 filled in the through holes 9 and the like and the roughened layer 11 on the upper surface of the inner conductor circuit 4 are removed to smooth both surfaces of the substrate, and the resin filler 10 and the A wiring board is obtained in which the side surface of the inner conductor circuit 4 is firmly adhered through the roughened layer 11, and the inner wall surface of the through hole 9 and the resin filler 10 are firmly adhered through the roughened layer 11.
- the surface of the resin filler 10 and the surface of the inner layer copper pattern 4 are flush with each other.
- the Tg point of the cured resin was Takashi ⁇ is 155.6 ° C ⁇ linear thermal expansion coefficient of 44.5x10- 6 / ° C.
- an electroless plating adhesive (viscosity: 7 Pa ⁇ s) on the greening agent layer 2a using a mouth coater, leave it in a horizontal state for 20 minutes, and then After drying for 30 minutes (prebaking), an adhesive layer 2b was formed (see Fig. 26 ').
- a photomask film on which a black circle of 85 m0 is printed is brought into close contact with both surfaces of the substrate on which the insulating layer 2a and the adhesive layer 2b are formed in the above (6), and is 500 mJ / cm 2 by an ultra-high pressure mercury lamp. Exposure. This is spray-developed with a DMTG solution, and the substrate is exposed to 3000 mJZcm 2 using an ultra-high pressure mercury lamp, and heat-treated at 100 ° C for 1 hour and then at 150 ° C for 5 hours (postbaking).
- the substrate with openings is immersed in 800 g / l of chromic acid at 70 ° C for 19 minutes to dissolve and remove epoxy resin particles present on the surface of the adhesive layer 2b of the interlayer resin insulation layer 2.
- the surface of the interlayer resin insulating layer 2 was made rough (3 ⁇ m in depth), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water (see FIG. 28).
- a palladium catalyst manufactured by Ryotec Co., Ltd. was applied to the surface of the surface-roughened substrate, so that catalyst nuclei were attached to the surface of the interlayer resin insulating layer 2 and the inner wall surface of the via hole 6.
- a commercially available photosensitive dry film is stuck on the electroless copper plating film 12 formed in the above (9), a mask is placed, and exposure is performed at 100 mJ / cm 2 , and 0.8% sodium carbonate is applied.
- the film was developed with a film to provide a plating resist 3 having a thickness of 15 / m (see FIG. 30).
- electrolytic copper plating was performed on the non-resist forming portion under the following conditions to form an electrolytic copper plating film 13 having a thickness of 151 (see FIG. 31).
- the electroless plating film 12 under the plating resist 3 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide.
- a conductor circuit (including via holes) 5 having a thickness of 18 ⁇ m and comprising an electrolytic copper plating film 12 and an electrolytic copper plating film 13 was formed.
- the surface of the adhesive layer for electroless plating between the conductor circuits located in the part where no conductor circuits are formed is immersed in 1-2 ⁇ m at 70 ° C for 3 minutes in 800 g / l humic acid. Then, the palladium catalyst remaining on the surface was removed (see Fig. 32).
- the viscosity was measured with a B-type viscometer (Tokyo Keiki, DVL-B type) using a mouthpiece No. 4 for rpm and a mouthpiece No. 3 for 6 rpm.
- soldering paste is printed on the opening of the solder resist layer 14 and a riff is made at 200 ° C to form a solder bump (solder body) 17.
- a multilayer printed wiring board having the following characteristics was manufactured (see Fig. 40).
- Example 5 Basically, it is the same as Example 5, but a metal film was formed under the following conditions instead of tin substitution.
- T1 (6-1) T1 was attached to the substrate at a pressure of 0.6 Pa, a temperature of 100 ° C, a power of 200 W, and a time of 2 minutes. Next, the T1 film between the conductor circuits was etched together with the resin using cupric acid.
- A1 was attached to the substrate at a pressure of 0.5Fa, a temperature of 100 ° C, a power of 200W, and a time of 1 minute. Next, the A1 film between the conductor circuits was etched together with the resin using cupric acid.
- (6-4) -6 was adhered to the substrate at an atmospheric pressure of 0.6-3 at a temperature of 10 (TC, power of 200W, for 2 minutes. Then, the Fe film between the conductor circuits was etched with chromic acid together with the resin.
- Ni was attached to the substrate at an atmospheric pressure of 0.6 Pa, a temperature of 100 ° C, a power of 200 W, and a time of 2 minutes.
- the N 1 film between the conductor circuits was etched together with the resin with cupric acid.
- Example 2 After the processes (1) to (8) of Example 1, the dry film photoresist was laminated, exposed, and developed to form a plating resist. Then, after performing (9) of Example 1, the plating resist was separated and removed in the same manner as in the process of (12), and the process of 3) of Example 1 was performed to roughen the entire surface of the conductor circuit. . Furthermore, after forming an interlayer resin insulation layer, roughening treatment, forming a plating resist, and electroless copper plating treatment to separate and remove the plating resist, the first embodiment (15) to (19) As a result, a multilayer printed wiring board having solder bumps was manufactured.
- a multilayer printed wiring board having solder bumps was manufactured in the same manner as in Comparative Example 1, except that a 0.3 m thick Sn layer was provided on the surface of the roughened layer (the Sn layer was not shown).
- IC chips were mounted on the printed wiring boards manufactured in Examples and Comparative Examples, and the temperature was 55 ° C. for 15 minutes, the room temperature was 10 minutes, and 125. (: In 15 minutes, 1000 and 2000 heat heat tests were performed.)
- the present invention can prevent cracks in the interlayer resin insulation layer and a bridge between the via hole and the lower conductor circuit, which occur during the heat cycle, while ensuring practical peel strength.
- Table 1 shows the results together with the results of the heat cycle test. As is evident from the results shown in Table 1, in the examples in which the surface of the roughened layer was coated with a layer of a metal or a noble metal having a tendency to ionize greater than copper and equal to or less than titanium, the dissolution of the conductor circuit due to local battery reaction was observed. Can be suppressed. Table 1 Heat cycle test
- the present invention it is possible to prevent cracks in the interlayer insulating material layer and conductor separation occurring during a heat cycle while securing practical peel strength, and furthermore, the surface of the conductor circuit can be prevented by local battery reaction. Since the melting can be prevented, the connection reliability of the printed wiring board can be surely improved.
Description
Claims
Priority Applications (12)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/595,000 USRE43509E1 (en) | 1996-12-19 | 1997-12-18 | Printed wiring board and method for manufacturing the same |
EP97949144A EP0952762B1 (en) | 1996-12-19 | 1997-12-18 | Printed wiring board and method for manufacturing the same |
US09/319,258 US6835895B1 (en) | 1996-12-19 | 1997-12-18 | Printed wiring board and method for manufacturing the same |
US10/351,501 US6930255B2 (en) | 1996-12-19 | 2003-01-27 | Printed circuit boards and method of producing the same |
US11/203,427 US7449791B2 (en) | 1996-12-19 | 2005-08-15 | Printed circuit boards and method of producing the same |
US11/522,938 US7585541B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
US11/522,999 US7388159B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
US11/522,961 US7712212B2 (en) | 1996-12-19 | 2006-09-19 | Method for manufacturing printed wiring board |
US11/522,940 US7371976B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
US11/522,956 US7361849B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
US11/522,960 US7615162B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
US11/523,000 US7385146B2 (en) | 1996-12-19 | 2006-09-19 | Printed wiring board and method for manufacturing the same |
Applications Claiming Priority (12)
Application Number | Priority Date | Filing Date | Title |
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JP8/354971 | 1996-12-19 | ||
JP35497196 | 1996-12-19 | ||
JP8/357959 | 1996-12-27 | ||
JP35795996A JPH10190224A (ja) | 1996-12-27 | 1996-12-27 | 多層プリント配線板およびその製造方法 |
JP35780196 | 1996-12-28 | ||
JP8/357801 | 1996-12-28 | ||
JP9/29587 | 1997-01-28 | ||
JP2958797A JPH10215060A (ja) | 1997-01-28 | 1997-01-28 | プリント配線板の半田バンプ形成方法、その形成方法において使用するプリント配線板および印刷用マスク |
JP19752697A JPH10242638A (ja) | 1996-12-19 | 1997-07-23 | 多層プリント配線板およびその製造方法 |
JP19752797A JPH10242639A (ja) | 1996-12-19 | 1997-07-23 | 多層プリント配線板およびその製造方法 |
JP9/197526 | 1997-07-23 | ||
JP9/197527 | 1997-07-23 |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
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US09/319,258 A-371-Of-International US6835895B1 (en) | 1996-12-19 | 1997-12-18 | Printed wiring board and method for manufacturing the same |
US09319258 A-371-Of-International | 1997-12-18 | ||
US10/351,501 Division US6930255B2 (en) | 1996-12-19 | 2003-01-27 | Printed circuit boards and method of producing the same |
Publications (1)
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WO1998027798A1 true WO1998027798A1 (fr) | 1998-06-25 |
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ID=27549470
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP1997/004684 WO1998027798A1 (fr) | 1996-12-19 | 1997-12-18 | Carte a circuit imprime et procede de fabrication |
Country Status (7)
Country | Link |
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US (11) | US6835895B1 (ja) |
EP (2) | EP1921902B1 (ja) |
KR (1) | KR20000057687A (ja) |
CN (2) | CN100435605C (ja) |
DE (1) | DE69740139D1 (ja) |
MY (2) | MY125599A (ja) |
WO (1) | WO1998027798A1 (ja) |
Cited By (3)
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EP1098558A4 (en) * | 1998-06-26 | 2006-03-15 | Ibiden Co Ltd | MULTILAYER PRINTED CARD AND METHOD FOR PRODUCING THE SAME |
US7235148B2 (en) * | 2002-04-09 | 2007-06-26 | International Business Machines Corporation | Selectively roughening conductors for high frequency printed wiring boards |
JP2011146477A (ja) * | 2010-01-13 | 2011-07-28 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法、並びに半導体パッケージ |
Families Citing this family (100)
Publication number | Priority date | Publication date | Assignee | Title |
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US6835895B1 (en) * | 1996-12-19 | 2004-12-28 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
US6141870A (en) | 1997-08-04 | 2000-11-07 | Peter K. Trzyna | Method for making electrical device |
DE69942279D1 (de) * | 1998-09-17 | 2010-06-02 | Ibiden Co Ltd | Vielschichtig aufgebaute leiterplatte |
KR100556818B1 (ko) * | 1999-05-13 | 2006-03-10 | 이비덴 가부시키가이샤 | 다층 프린트 배선판 및 그 제조방법 |
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- 1997-12-18 US US09/319,258 patent/US6835895B1/en not_active Ceased
- 1997-12-18 CN CNB2004101000753A patent/CN100435605C/zh not_active Expired - Lifetime
- 1997-12-18 MY MYPI97006160A patent/MY125599A/en unknown
- 1997-12-18 WO PCT/JP1997/004684 patent/WO1998027798A1/ja not_active Application Discontinuation
- 1997-12-18 MY MYPI20043243A patent/MY128039A/en unknown
- 1997-12-18 DE DE69740139T patent/DE69740139D1/de not_active Expired - Lifetime
- 1997-12-18 EP EP08002134A patent/EP1921902B1/en not_active Expired - Lifetime
- 1997-12-18 KR KR1019990705543A patent/KR20000057687A/ko active Search and Examination
- 1997-12-18 EP EP97949144A patent/EP0952762B1/en not_active Expired - Lifetime
- 1997-12-18 CN CNB971814473A patent/CN1265691C/zh not_active Expired - Lifetime
- 1997-12-18 US US11/595,000 patent/USRE43509E1/en not_active Expired - Lifetime
-
2003
- 2003-01-27 US US10/351,501 patent/US6930255B2/en not_active Expired - Lifetime
-
2005
- 2005-08-15 US US11/203,427 patent/US7449791B2/en not_active Expired - Fee Related
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2006
- 2006-09-19 US US11/522,999 patent/US7388159B2/en not_active Expired - Fee Related
- 2006-09-19 US US11/523,000 patent/US7385146B2/en not_active Expired - Fee Related
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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EP1098558A4 (en) * | 1998-06-26 | 2006-03-15 | Ibiden Co Ltd | MULTILAYER PRINTED CARD AND METHOD FOR PRODUCING THE SAME |
EP1903842A3 (en) * | 1998-06-26 | 2009-05-06 | Ibiden Co., Ltd. | Multilayer printed wiring board |
US7235148B2 (en) * | 2002-04-09 | 2007-06-26 | International Business Machines Corporation | Selectively roughening conductors for high frequency printed wiring boards |
JP2011146477A (ja) * | 2010-01-13 | 2011-07-28 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法、並びに半導体パッケージ |
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