WO1998037573A3 - Integrated circuit floor plan optimization system - Google Patents

Integrated circuit floor plan optimization system Download PDF

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Publication number
WO1998037573A3
WO1998037573A3 PCT/US1998/002542 US9802542W WO9837573A3 WO 1998037573 A3 WO1998037573 A3 WO 1998037573A3 US 9802542 W US9802542 W US 9802542W WO 9837573 A3 WO9837573 A3 WO 9837573A3
Authority
WO
WIPO (PCT)
Prior art keywords
functions
integrated circuit
core space
floor plan
pieces
Prior art date
Application number
PCT/US1998/002542
Other languages
French (fr)
Other versions
WO1998037573A2 (en
Inventor
Ranko Scepanovic
Alexander E Andreev
Ivan Pasivic
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Publication of WO1998037573A2 publication Critical patent/WO1998037573A2/en
Publication of WO1998037573A3 publication Critical patent/WO1998037573A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Abstract

A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space (30) to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions (50). Then, pieces of the core space (30) are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used to shift the allocated capacities of the functions as to shift excess capacity or core space (30) from the functions with excess capacity to the functions with a shortage of capacity.
PCT/US1998/002542 1997-02-11 1998-02-10 Integrated circuit floor plan optimization system WO1998037573A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/798,652 1997-02-11
US08/798,652 US5898597A (en) 1997-02-11 1997-02-11 Integrated circuit floor plan optimization system

Publications (2)

Publication Number Publication Date
WO1998037573A2 WO1998037573A2 (en) 1998-08-27
WO1998037573A3 true WO1998037573A3 (en) 1998-11-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/002542 WO1998037573A2 (en) 1997-02-11 1998-02-10 Integrated circuit floor plan optimization system

Country Status (2)

Country Link
US (1) US5898597A (en)
WO (1) WO1998037573A2 (en)

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Publication number Publication date
US5898597A (en) 1999-04-27
WO1998037573A2 (en) 1998-08-27

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