WO1998038682A1 - Semiconductor device with a programmable semiconductor element - Google Patents
Semiconductor device with a programmable semiconductor element Download PDFInfo
- Publication number
- WO1998038682A1 WO1998038682A1 PCT/IB1998/000189 IB9800189W WO9838682A1 WO 1998038682 A1 WO1998038682 A1 WO 1998038682A1 IB 9800189 W IB9800189 W IB 9800189W WO 9838682 A1 WO9838682 A1 WO 9838682A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- floating gate
- oxide
- gate
- type
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 32
- 239000000463 material Substances 0.000 claims description 4
- 230000015654 memory Effects 0.000 abstract description 15
- 230000014759 maintenance of location Effects 0.000 abstract description 7
- 230000005641 tunneling Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 239000003574 free electron Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000370 acceptor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Definitions
- the invention relates to a semiconductor device with a programmable semiconductor element formed by a transistor with a floating gate and comprising a semiconductor body with a p-type surface region adjoining a surface, which programmable semiconductor element comprises a source and a drain in the form of n-type surface zones which are provided in the surface region and are mutually separated by an interposed channel region above which the floating gate is provided, said gate being separated from the surface of the semiconductor body by an interposed electrically insulating layer and being formed by a layer of doped semiconductor material.
- the programmable semiconductor element together with a smaller or larger number of identical elements may form a programmable, non-volatile memory such as an EPROM or EEPROM or FLASH EPROM.
- the memory may then be a stand alone memory or may be integrated with a large number of other circuit elements into an integrated signal processing circuit such as, for example, a microcontroller.
- the floating gate in usual embodiments of an EPROM or EEPROM is formed by a layer of n-type doped polycrystalhne silicon.
- a device in which the floating gate comprises p-type doped polycrystalhne silicon is known inter alia from US-A 5,260,593.
- the usual n-type poly of the floating gate is replaced by p-type poly exclusively with the object of increasing the threshold voltage of the transistor.
- Electrons are applied to the floating gate electrode during programming or writing of memory elements having floating gates, for which purpose, for example, the tunneling effect or hot charge carriers are used, so that these electrodes are electrically negatively charged and the threshold voltage of the transistor is raised.
- the charge state of the floating gate represents the written information. To read this information, it is ascertained whether the transistor is or is not conducting, given a certain voltage at the control electrode.
- An important property of non-volatile memories is the data retention, which is defined as the time during which the written information is still present to a sufficient degree at the floating gate. In general, the leakage current which causes the electric charge to disappear from the floating gate should be so small that the memory can remain in use without re- writing during a period of several years (for example, ten years).
- the gate dielectric should have a thickness greater than 7 nm in conventional memories. This again implies that a high voltage is required for programming so as to obtain the required electrical field strength in the gate dielectric. This may cause problems in situations in which, for example, the supply voltage should be low, or in circuits where low breakdown voltages occur.
- the invention has for its object inter alia to provide a semiconductor device of the kind described in the opening paragraph in which a much thinner gate dielectric is used compared with usual devices, while the data retention is maintained.
- a semiconductor device is characterized in that, p-type semiconductor material being used for the floating gate, the minimum thickness of the insulating layer between the floating gate and the surface of the semiconductor body is no more than approximately 7 nm.
- the invention is based inter alia on the recognition that a programmed conventional cell with an n-type floating gate has free electrons in excess at its floating gate. Parts of these free electrons may be present adjacent the interface between poly and gate oxide in the form of an accumulation layer and may accordingly leave the floating gate by tunneling towards the substrate in the case of a sufficiently thin gate oxide.
- the gate oxide of a conventional cell it is necessary for the gate oxide of a conventional cell to have a thickness greater than 7 nm. If a p-type floating gate is used, however, as in a device according to the invention, the electrons arriving at the floating gate during programming will recombine with free holes. This results in a negative space charge formed by ionized acceptors. These are not movable and are largely present at a greater distance from the poly- gate oxide interface than the free electrons at an n-type floating gate. Furthermore, the electrons in the ionized acceptors have a binding energy of approximately 1 eV with respect to the conduction band of Si.
- the thinner gate oxide has the advantage inter alia that the cell can be programmed or erased with a lower voltage, so that it is easier to realize the device in low-voltage processes and/or to combine the memory with a low-voltage circuit in a common integrated circuit.
- the minimum thickness of the insulating layer between the surface of the semiconductor body and the floating gate is no more than 6 nm.
- a further embodiment of a device according to the invention in which the cell can be erased electrically, as in an EEPROM and FLASH EPROM, is characterized in that the doping concentration of the floating gate electrode is so low that a layer of electrons can be formed at the interface between the floating gate electrode and the insulating layer through the application of suitable voltages for erasing stored information.
- the doping concentration of the floating gate electrode is at most approximately 1.5 x 10 19 atoms per cm 3 .
- Fig. 1 is a cross-section of a first embodiment of a semiconductor device according to the invention
- Fig. 2 plots the threshold voltage gradient as a function of time for a cell having an n-type floating gate and for a cell having a p-type floating gate; and Fig. 3 is a cross-section of a second embodiment of a semiconductor device according to the invention.
- Fig. 1 is a cross-section of a first embodiment of a semiconductor device according to the invention with a programmable semiconductor element in the form of a transistor with floating gate.
- the transistor only is shown in the drawing, but it will be obvious to those skilled in the art that the device may comprise a large number of other circuit elements in addition to the transistor.
- the device comprises a semiconductor body of silicon with a p-type surface region 2 adjoining the surface 1.
- the transistor comprises a source and a drain in the form of n-type surface zones 3 and 4, respectively, separated from one another by an interposed channel region 5.
- the zones 3 and 4 are provided with respective connections 6 and 7 which are shown in the drawing diagrammatically only.
- a floating gate 8 in the form of doped polycrystalline silicon (poly) is provided above the channel region 5 and is electrically insulated from the subjacent surface 1 by an electrically insulating silicon oxide layer 9.
- the thickness of the oxide layer is approximately 6.0 nm.
- the transistor in this example is in addition provided with a control electrode 10 above the floating gate 8, electrically insulated therefrom by a dielectric layer 11.
- the layer 11 may comprise a single silicon oxide layer or may be composed of a multiple layer of, for example, silicon oxide and silicon nitride, or may comprise a layer of oxynitride.
- the control electrode 10, which may be made of poly or of a metal, is provided with a connection 12 which is diagrammatically depicted.
- Fig. 2 shows the retention at a temperature of approximately 250 °C of a conventional memory cell with an n-type floating gate and of a memory cell with a p-type floating gate, whose oxide thicknesses are the same.
- the threshold voltage is plotted on the vertical axis, and time t in hours on the horizontal axis.
- the threshold voltage V t ⁇ practically does not change both in a conventional cell as in a cell having a p-type floating gate (curve A) when the cell is not programmed, i.e. contains information H 0".
- the situation is different for the two cells when they are programmed, i.e. have information "1".
- the loss of charge in the conventional cell (curve B) is much greater than in the cell having a p-type floating gate (curve C).
- the thickness of the gate oxide should be chosen such that the difference between V ⁇ in the "1" state and V ⁇ in the "0" state remains sufficiently great for a sufficiently long period, for example a few years, at the normal operating temperature. Since the loss of charge in a cell with a p-type floating gate is much smaller than in one with an n-type gate, it is possible to reduce the thickness of the gate dielectric when a p-type gate is used and yet achieve the same retention as in a cell having an n-type gate. The electrons necessary for (electrical) erasing can be obtained by means of electric fields of higher values specific for erasing.
- the doping concentration in the p-type floating gate is preferably chosen to be not higher than 1.5 x 10 19 atoms per cm 3 .
- the gate dielectric has a uniform thickness.
- Fig. 3 shows a modification where the gate dielectric 9 has a greater thickness for the major part, for example 8 nm, than the gate oxide 9 in Fig. 1, and is locally provided with very thin tunneling oxide 13 having a thickness of at most 6 nm. Electrons can be applied to the p-type floating gate by means of the tunneling mechanism through this oxide 13 during programming.
- the gate oxide 9 between the source and drain zones 3 and 4 may have a uniform thickness of, for example, 8 nm in a modification of the embodiment of Fig. 3, while the floating gate 8 and the control electrode 10 extend outside the channel region above an injector region of the substrate which is separated from the p- type floating gate by a thin-tunneling oxide of 6 nm.
- the electrons necessary for erasing may alternatively be generated by optical means, for example by irradiation with UV.
- the invention may also be advantageously applied to so-called OTP devices (One Time Programmable), i.e. those which need not be erased anymore after being programmed.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10529249A JP2000509911A (en) | 1997-02-27 | 1998-02-16 | Semiconductor device having writable semiconductor element |
KR1019980708628A KR20000065063A (en) | 1997-02-27 | 1998-02-16 | Semiconductor devices with programmable semiconductor elements |
EP98901453A EP0897598A1 (en) | 1997-02-27 | 1998-02-16 | Semiconductor device with a programmable semiconductor element |
PCT/IB1998/000189 WO1998038682A1 (en) | 1997-02-27 | 1998-02-16 | Semiconductor device with a programmable semiconductor element |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97200577.1 | 1997-02-27 | ||
PCT/IB1998/000189 WO1998038682A1 (en) | 1997-02-27 | 1998-02-16 | Semiconductor device with a programmable semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998038682A1 true WO1998038682A1 (en) | 1998-09-03 |
Family
ID=11004680
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1998/000189 WO1998038682A1 (en) | 1997-02-27 | 1998-02-16 | Semiconductor device with a programmable semiconductor element |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1998038682A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4608585A (en) * | 1982-07-30 | 1986-08-26 | Signetics Corporation | Electrically erasable PROM cell |
EP0436156A1 (en) * | 1989-12-11 | 1991-07-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having tunnel insulating film structure |
US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
US5260593A (en) * | 1991-12-10 | 1993-11-09 | Micron Technology, Inc. | Semiconductor floating gate device having improved channel-floating gate interaction |
-
1998
- 1998-02-16 WO PCT/IB1998/000189 patent/WO1998038682A1/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4608585A (en) * | 1982-07-30 | 1986-08-26 | Signetics Corporation | Electrically erasable PROM cell |
US5066992A (en) * | 1989-06-23 | 1991-11-19 | Atmel Corporation | Programmable and erasable MOS memory device |
EP0436156A1 (en) * | 1989-12-11 | 1991-07-10 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having tunnel insulating film structure |
US5260593A (en) * | 1991-12-10 | 1993-11-09 | Micron Technology, Inc. | Semiconductor floating gate device having improved channel-floating gate interaction |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN, Vol. 1, No. 143; & JP,A,52 079 883 (NIPPON ELECTRIC CO) 5 July 1977. * |
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