WO1998055950A1

WO1998055950A1 - Integrated circuit layout synthesis tool

Info

Publication number: WO1998055950A1
Application number: PCT/US1998/010276
Authority: WO
Inventors: David C. Chapman
Original assignee: Chapman David C
Priority date: 1997-06-06
Filing date: 1998-05-20
Publication date: 1998-12-10
Also published as: TW396379B

Abstract

A design-rule driven IC layout synthesis tool which generates IC layouts using non-orthogonal geometry is provided. First, a physical ordering of a set of IC devices to be included in the IC layout is determined based upon predetermined electrical connections between the IC devices. Then, one or more IC device groups are established based upon the physical ordering of the set of IC devices. An IC device group layout is generated for each of the one or more IC device groups based upon predetermined design criteria. Generating a device group layout involves evaluating a series of layout solutions for the device group and then determining an optimal layout solution based upon a cost function. Then, a relative physical arrangement of the IC device group layouts is determined based upon predetermined routing criteria. Finally, connections are determined between the IC device group layouts based upon the predetermined electrical connections between the devices.

Description

INTEGRATED CIRCUIT LAYOUT SYNTHESIS TOOL

FIELD OF THE INVENTION

The invention relates to the design of integrated circuits, and more specifically, to a method and apparatus for generating integrated circuit layouts.

BACKGROUND OF THE INVENTION In the context of integrated circuit (IC) design, a " layout" is a set of geometric patterns, typically in the form of polygons, which specify the size and location of different types of material used to create semiconductor devices and electrical connections between the devices during the fabrication of an IC. For example, a diffusion window on an IC may be represented in a layout by one or more polygons which are interpreted by a fabrication facility to mean " diffusion layer geometry." Other layers of material and features, such as contacts and vias, may also be similarly represented in an IC layout. The polygons in an IC layout must meet a set of design rules which define minimum sizes for certain types of material as well as minimum spacing requirements between different types of material. The design rules also specify size and spacing requirements for other layout features such as contacts. Consider the example IC layout illustrated in Figure 1. Layout 100 is comprised of a number of polygons which represent different layers of material and other features. Specifically, layout 100 includes polygons representing a diffusion layer 102, which are sometimes referred to as "diffusion islands." Layout 100 also includes polygons representing a polysilicon layer 104, which intersects diffusion layer 102 to form transistors, and also polygons representing a metal layer 106. Finally, contacts 108 provide electrical connections between metal layer 106 and diffusion layer 102. For simplicity, layout 100 does not illustrate all of the features which are typically included in an IC layout such as implant selection layers or well ties, but is nevertheless representative of a conventional layout style.

Layout 100 illustrates a conventional CMOS layout which includes a top row of transistors 109, arranged adjacent to a positive supply voltage V_DD, and above a bottom row of transistors 110, which are arranged adjacent to a negative supply voltage GND. Output Z, is a function of inputs (I,-I₈). This approach for arranging transistors can be a very efficient way of organizing a layout, especially when the top row of transistors 109 have the same gate connections (vertical polygons of polysilicon layer 104) as the bottom row of transistors 110, because the transistors can be connected without layer changes or crossovers since all of the gate connections are arranged vertically. The only remaining routing is to connect the transistor source and drain nodes together and perhaps to connect the transistor source and drain nodes to gate nodes. It should be noted that typically the 'P' type transistors in the top row of transistors 109 would be much larger (have larger areas of polysilicon layer 104 developing diffusion layer 102) than the 'N' type transistors in the bottom row of transistors 110 since 'P' type devices are not as strong as 'N' type devices. However, for simplicity, all of the transistors are depicted as being the same size.

Traditionally, IC layouts such as layout 100 have been drawn by hand using a computer aided design (CAD) system. A designer typically starts by designing leaf cell layouts for the desired circuit where each leaf cell layout often contains from two to several hundred transistors and performs a specific function such as a NAND logical operation or storing a bit of information. The leaf cells are then assembled and interconnected to complete an IC layout. Designers try to make IC layouts as compact as possible while still meeting the design rules because wire length has a direct effect on IC performance and total IC size affects fabrication cost per IC. Generally, the more compact an IC layout is, the faster an IC built from the layout is. To reduce the size of IC layouts, designers adjust the shape and location of the polygons to reduce the amount of free space between different polygons. For example, a designer may replace several straight transistors with jogged transistors to reduce the width of a leaf cell. In addition, a designer may trim any excess material from diffusion islands. Using these types of customized design "tricks," a designer is able to create a reasonably compact IC layout.

Although compact IC layouts are very desirable, drawing IC layouts by hand has certain drawbacks. First, creating an IC layout by hand is very labor intensive and can take a long time, even when libraries of standard cells are used. Moreover, any changes in the design, or even worse, in the design constraints, can require that large portions of an IC layout be redrawn. This problem is exacerbated by modern fabrication technology which allows several million transistors to be placed on a single silicon substrate. As a result of the sheer size and complexity of contemporary integrated circuits, various computer-based IC layout design tools have been developed. Two types of layout design tools include leaf cell compaction tools and leaf cell synthesis tools. Leaf cell compaction tools are used to reduce the size of an existing IC layout. Most leaf cell compaction tools compact a layout in either the vertical or horizontal direction by eliminating extra space between polygons. "Full" compaction is sometimes provided by first compressing a layout in the horizontal direction and then compressing the layout in the vertical direction. Also, some leaf cell compaction tools adjust the coordinates of the polygon points in an IC layout until they meet the design rules for a particular fabrication process, making them helpful for porting an existing layout from a current set of design rules to a new set of design rules. However, compaction often results in a layout which is larger than comparable hand- drawn cells because compaction is generally a one-dimensional process. Despite the advantages provided by leaf cell compactors, they have some significant limitations. Most importantly, leaf cell compactors generally cannot change the topology of a layout and consequently are limited as to how much they can reduce the size of a layout. For example, leaf cell compactors do not add extra polygons to form a jog in a wire. Also, if the desired height of a leaf cell is increased for a new process, most compactors do not take advantage of the extra space by stacking transistors in multiple rows to reduce the size of a layout. Conversely, if the desired height of the standard cell is reduced, compactors can't redesign the cell to accommodate the tightened requirement by splitting wide devices or arranging tie down contacts so that they are in line with the transistors. Some leaf cell compactors allow users to manually insert jog points to assist in compaction, but most compactors do not add them automatically because they result in more equations to be solved. Finally, compacted layouts sometimes contain design rule violations which must be fixed by hand.

In contrast to leaf cell compaction tools, leaf cell synthesis tools have the capability to generate a new leaf cell layout based upon a transistor-level netlist which specifies the size of transistors and the electrical connections between transistors. Consequently, some leaf cell synthesis tools can generate more compact layouts than their compaction tool counterparts. However, most synthesis tools only use orthogonal geometry, meaning that all of the polygons are placed only at 90° angles with respect to each other. Layout 100 of Figure 1 is an example of an orthogonal layout. Orthogonal geometry can work well for some types of standard cells, such as memory cells. Moreover, pure orthogonal geometry has fewer polygons than a layout which uses non-orthogonal geometry. A lower polygon count is preferable to a higher polygon count because a layout with a higher polygon count takes longer to be processed by the layout fabrication equipment and also makes the IC more susceptible to wafer processing defects. However, a pure orthogonal implementation often results in a layout which is larger that a layout using non-orthogonal geometry since all of the transistors and connecting wires are either straight or have 90° bends. Moreover, many layouts generated by synthesis tools are not very compact and often must be compacted with a compaction tool. One adverse consequence of using only orthogonal geometry is the space which is wasted between adjacent portions of polysilicon layer rows in order to align adjacent transistor rows. For example, in Figure 1, diffusion abutment 112 between gate I, and gate I₂ does not contain a contact, but space is provided for one because of a contact 114 located between gate I, and gate I₂ in the bottom row of transitions 110. Similarly, there is no contact in diffusion abutment 116 between gate I₅ and gate I₆ in the bottom row of transaction 110, although room is provided for one because of contact 118 between gate I₅ and gate I₆ in the upper row of transistors 109.

In contrast to layout 100 of Figure 1, consider the layout 200 illustrated in Figure 2 which is identical to layout 100 of Figure 1 except for a layout change illustrated by dashed box 202. Specifically, layout 200 includes a jog 204 in gate I„ between the upper row of transistors 206 and the bottom row of transistors 208, which allows gate I, and gate I₂ to be closer together in the upper row of transistors 206, reducing the size of diffusion abutment 210, which in turn makes layout 200 smaller than layout 100 of Figure 1. In the context of an IC layout, a "jogged" gate is a transistor gate having two bends such that the portions of the gate above and below are parallel. Although this change does not necessarily change the path length of gate I,, it may allow layout 200 to be located closer to another layout (not illustrated) or may also allow routing wires closer to layout 200 than otherwise would be possible. Unfortunately, current layout synthesis tools do not support the use of non-orthogonal geometry.

In view of the time required to generate IC layouts by hand and the limitations in existing leaf cell compaction and synthesis tools, a design rule driven cell layout synthesis tool which supports the use of non-orthogonal geometry is highly desirable.

SUMMARY OF THE INVENTION

According to one aspect of the invention, a method is provided for generating a data representation of an IC layout. The first in a series of computer-implemented steps includes determining an ordering of a set of IC devices to be included in the IC layout based upon predetermined electrical connections between the IC devices. Then, one or more IC device groups are established based upon the determined ordering of the set of IC devices. A data representation of an IC device group layout is generated for each of the one or more established IC device groups based upon predetermined design criteria. Then a relative physical arrangement of the IC device group layouts is determined based upon predetermined routing criteria. Electrical connections between the IC device group layouts are determined based upon the predetermined electrical connections between the devices and the relative physical arrangement of the IC device group layouts. Finally, the data representation of the IC layout reflecting both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts is generated.

According to another aspect of the invention, a method is provided for generating a data representation of an IC device layout. First and second data representations of the IC device layout are generated based upon a set of design criteria. Then, either the first data representation or the second data representation is selected as the data representation for the IC device layout based upon a second set of cost function criteria which includes the overall size of an IC device layout. According to other aspects of the invention, other cost function criteria include the polygon count and the proximity of supply contacts to power supply lines.

According to another aspect of the invention, a computer system is provided for automatically generating a data representation of an IC layout containing non-orthogonal geometry. The computer system includes a memory comprising a set of IC device data which specifies electrical connections between IC devices to be included in the IC layout. The computer system also includes a set of design criteria indicative of a desired data representation of an IC device group layout for one or more IC device groups contained in the IC layout. Finally, the computer system includes a set of routing criteria indicative of a desired physical arrangement of layouts for the one or more IC device groups. BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which: Figure 1 illustrates an orthogonal IC layout;

Figure 2 illustrates an orthogonal IC layout which includes a jogged transistor configuration;

Figures 3 A and 3B comprise is a flow chart illustrating a method for generating an IC layout according to an embodiment of the invention; Figure 4 is a flow chart illustrating a method for determining an optimal layout solution according to an embodiment of the invention;

Figure 5 illustrates a diffusion island layout according to an embodiment of the invention;

Figure 6 is a table illustrating factors considered in selecting a transistor configuration according to an embodiment of the invention; Figure 7 illustrates the layout for two adjacent diffusion islands according to an embodiment of the invention;

Figure 8 A illustrates a diffusion island layout according to an embodiment of the invention;

Figure 8B illustrates the diffusion island layout of Figure 8 A redrawn with a different under supply limit according to an embodiment of the invention; and

Figure 9 is a block diagram of a computer system on which the invention may be implemented.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A design-rule driven IC layout synthesis tool which generates IC layouts using non- orthogonal geometry is described. In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In other instances, well-known structures and devices are depicted in block diagram form in order to avoid unnecessarily obscuring the invention.

FUNCTIONAL OVERVIEW The top level approach for generating an IC cell layout according to an embodiment of the invention is illustrated by the flow chart of Figures 3A and 3B. After starting in step 300, in step 302 a transistor connection list, a set of design rules, and a set of design constraints are received by the IC layout synthesis tool of the invention. In step 304, the relative physical ordering of transistors in the transistor connection list is determined based upon predetermined connections between the transistors. Then, in step 306 the transistors are grouped into diffusion islands. In step 308, the first diffusion island is constructed based upon the design rules and design constraints. In step 310, a determination is made as to whether any more diffusion islands need to be constructed. If so, then the next diffusion island is constructed in step 308. Steps 308 and 310 are repeated until all of the diffusion islands have been constructed. Once a determination has been made in step 310 that all of the diffusion islands have been constructed, then in step 312 an initial diffusion island placement is determined. In step

314, the diffusion island placement is adjusted based upon the spacing required for routing between the diffusion islands.

In step 316, electrical connections are routed between the diffusion islands. In step 318, a determination is made as to whether any of the diffusion islands need to be reconstructed based upon the routing performed in step 316. If so, then in step 320 the design constraints are adjusted and in step 322 one or more of the diffusion islands are reconstructed based upon the adjusted design constraints. Steps 312-316 are repeated to reestablish the diffusion island placement and reroute the diffusion islands. This process continues until a determination is made in step 318 that none of the diffusion islands need to be reconstructed. Then the process is completed in step 324. The steps in the flow chart of Figure 3 are now described in the detailed description section which follows.

DETAILED DESCRIPTION

I. RECEIVING THE TRANSISTOR CONNECTION LIST, THE DESIGN RULES AND

THE DESIGN CONSTRAINTS

According to one embodiment of the invention, the transistor connection list identifies the transistors to be included in the layout, the size of each transistor and the electrical connections between the transistors. The design rules specify minimum and maximum sizes and spacing between the polygons in the layout. For example, the design rules typically specify a mimmu width for polyinterconnect as well as a minimum spacing between polyinterconnect and diffusion. In the context of IC layout design, the term "polyinterconnect" refers to a portion of a polysilicon layer which is not used to form a transistor and instead is used to form an electrical connection between two points in a layout. Another example is a diffusion extension rule which specifies a minimum amount of diffusion which must extend beyond the gate of a transistor, perpendicular to the gate. With regard to contacts, the design rules specify the contact enclosure rules, which include the minimum amount of diffusion which must surround a contact as well as the minimum spacing between a contact and other layout geometry, such as transistors. Finally, the design constraints specify certain criteria which must be considered during the construction of the layout. According to one embodiment of the invention, the design constraints include the following criteria:

1. Device widths within a diffusion island may not be changed

2. Contacts may be required between some or all of the gates 3. Under Supply Limit: Specifies how far underneath a power supply wire that a polysilicon gates (and diffusion) may be drawn

4. Whether some contacts are to be positioned a predetermined distance away from the power supply wire, for example, to allow horizontal routing between the contacts. This forces the contacts to the top or bottom to accommodate routing. This may force contacts to alternate between the top and bottom of the diffusion island, forcing the contacts at the top closer to the supply rail and forcing the contacts at the bottom of the diffusion island towards the ground rail.

5. A minimum spacing, larger than the design rules require, may be requested between two or more transistor gates to allow vertical routing between the gates. 6. Specified Straight Configuration: Some transistors may be forced to be drawn in the straight configuration so that the contacts can be shifted up or down between a pair of transistors during the routing of the diffusion islands..

7. Whether the position of the first contact in a diffusion island is to be alternated with respect to the last contact in the previous diffusion island to optimize overall cell width. 8. Diffusion Routing Limit: Specifies a maximum distance between any point in a transistor source/drain region and the nearest contact. For layouts having polysilicon gated oriented vertically, this limits the vertical spacing between contacts for large devices. The diffusion routing limit is typically determined by the fabrication facility to ensure that the transistors operate properly. 9. To what extent the number of polygon points, indicative of the geometric complexity, should be minimized where possible. This constraint is directed towards a preference for using a straight transistor configuration unless a specific area advantage is provided by using a jogged or single bend transistor configuration.

II. ORDERING AND GROUPING THE TRANSISTORS

After the transistor connection list, the design rules and the design constraints have been received, the transistor connection list is evaluated to determine an ordering of the transistors based upon the connections between the transistors identified in the transistor connection list. Once an ordering for the transistors has been determined, the transistors are divided into transistor groups based upon the electrical connections. Ideally, the electrical connections allow all of the transistors to be arranged in a single diffusion island, since overall cell width and the length of connection wires is minimized by reducing the number of interruptions in diffusion geometry.

For example, if the drain of a first transistor Q, is electrically connected to the source of a second transistor Q₂, such as in a totem pole arrangement, then Q, and Q₂ are ordered sequentially so that they are placed on the same diffusion island. However, typically the transistor connections and transistor types (P, N) dictate that a more compact layout can be generated by separating the transistors into two or more transistor groups (diffusion islands) which are arranged in two rows in the cell. Many approaches for ordering transistors are known in the art and are suitable for the layout synthesis tool of the invention.

III. CONSTRUCTING A DIFFUSION ISLAND In the context of the invention, constructing a diffusion island refers to a process for generating an IC layout for one or more transistors which share a common polygon of diffusion. In general, the process for constructing a diffusion island according to an embodiment of the invention involves selecting an initial layout solution and then performing an exhaustive search and comparison of other layout solutions to the initial selected solution to identify an optimal solution. The optimal layout solution provides the most compact layout which satisfies both the design rules and the design constraints. It is important to note that since the design constraints may require that space be reserved in a diffusion island for routing within and through a diffusion island, the optimal layout solution does not necessarily provide the most compact layout in absolute terms. Rather, the optimal layout solution provides the most compact layout which satisfies both the design constraints and the design rules. This approach provides a compact integrated cell when the diffusion islands are arranged and routed.

A. DETERMINING AN OPTIMAL LAYOUT SOLUTION

The top-level approach for determining an optimal layout solution according to an embodiment of the invention is illustrated by the flow chart of Figure 4. After starting in step 400, in step 402 an initial layout solution is selected from the available layout solutions. In step 404, the initial layout solution is constructed and then designated as the known best layout solution.

In step 406, a new layout solution is selected based upon the known best layout solution. According to an embodiment of the invention, a new layout solution is selected based upon a depth first search which does not assume an optimal solution to the left of a given transistor and which is described in more detail hereinafter. Generally the configuration of the last transistor (the rightmost) in the diffusion island is changed to one of the other possible configurations for that transistor and the layout is reconstructed. Once all of the possible configurations for the last transistor have been tried, then the configuration of the next to last transistor is the diffusing island is changed to one of the other possible configurations for that transistor.

Then, in step 408, the new layout solution is constructed. The construction of a layout solution is described in more detail below.

In step 410, the new layout solution is compared to the known best layout solution and in step 412, a determination is made as to whether the new layout solution is "better" than the known best layout solution based upon a cost function which considers various characteristics of each layout solution such as overall layout area, polygon count within each layout solution and the use of metal routing within each layout solution. According to one embodiment of the invention, the cost function takes into consideration one or more of the following factors: 1. Overall horizontal width. Given that the cell height is generally fixed, a smaller - diffusion island width usually reduces the overall size of the cell, making a layout solution with less horizontal width preferable to a layout solution with greater horizontal width. If the final contact location of the diffusion island to the left of the present diffusion island (the previous diffusion island) is known, then a layout solution which has a first contact which alternates contact placement with the previous island may be given a preference.

2. Overall vertical height. A layout solution with less vertical height is preferred over a layout solution with greater vertical height because a smaller diffusion island usually reduces the overall size of the cell.

3. The number of supply contacts adjacent to the supply wire. If supply contacts are positioned immediately adjacent to the supply rail, the " effective height" is reduced because a diffusion island can be positioned underneath the supply rail. Thus having supply contact close to the supply rail is advantageous. Supply contacts positioned away from the supply rail can block horizontal routing area, which in most layouts, is an important resource.

4. Total number of contacts of any kind adjacent to the supply wire. Positioning any type of contact close to the supply rail can also be beneficial by allowing a diffusion island to be moved under the supply rail, although not to the same degree.

5. Complexity of geometry. Simpler geometry is preferred over more complex geometry because simpler geometry has fewer polygons. Other factors may also be considered in evaluating two layout solutions without departing from the scope of the invention.

If, in step 412, a determination is made that the new layout solution is better than the known best layout solution, then in step 414 the new layout solution is designated as the known best layout solution. In step 416, a determination is made as to whether there are more layout solutions to try. If so, then the process continues in step 46 with the selection of a new layout solution based upon the known best solution. On the other hand, if in step 416 a determination is made that there are no more layout solutions to try, then the process is completed in step 418.

According to one embodiment of the invention, partial diffusion island solutions are built and then reused to reduce the time required to construct a diffusion island.

B. CONSTRUCTING A LAYOUT SOLUTION

According to an embodiment of the invention, a layout solution is constructed left to right across the diffusion island, starting with the leftmost (first) transistor and ending with the rightmost (last) transistor. Generally, a configuration is selected for each transistor and then the transistor is sized based upon the specified size, the design rules and the design constraints. This discussion includes: 1) the types of transistor configurations; 2) selecting a transistor configuration; 3) contact placement; and 4) other considerations.

1. TYPES OF TRANSISTOR CONFIGURATIONS

Figure 5 depicts an example diffusion island layout 500 which includes a diffusion layer 502, a polysilicon layer 504 and contacts 506, represented as polygons on a grid 507. Grid 507 includes grid units which are hereinafter referred to as " lambda," and which are used in this application as a dimensionless unit of measure for describing sizing and spacing of polygons on the various layouts. The actual value of lambda is based upon the design rules applied to a layout which vary from process to process and foundry to foundry.

Polysilicon layer 504 overlaps diffusion layer 502 to form four different transistor configurations according to an embodiment of the invention. These include the a) straight configuration; b) large jogged configuration; c) small jogged configuration; and d) single bend configuration, which are each described herein after in more detail.

a. Straight Configuration

The straight configuration is exemplified by a straight transistor 508, which is six lambda wide, making it particularly suitable for applications which require narrow transistors. The width (W) is defined as the path length where polysilicon crosses diffusion and, for straight transistor 508, is measured as six vertical grid units or lambda on grid 507 where polysilicon layer 504 overlaps diffusion layer 502.

A straight configuration transistor has a minimum gate to gate pitch (hereinafter referred to as "pitch") of eight lambda. In the context of IC layout design, the term pitch refers to an amount of horizontal lambda required from contact to contact, which is measured from the right edge of a contact on the left side of the transistor to the left edge of the gate to the right edge of a contact to the right of the transistor. Referring to straight transistor 508 in Figure 5, the pitch (P) of eight lambda includes two lambda for contact to polysilicon spacing, two lambda for the width of the polysilicon gate, two lambda for polysilicon to contact spacing and two lambda for contact width.

b. Large Jogged Configuration

In contrast to the straight configuration, the large jogged configuration is exemplified by a large jogged left transistor 510 and a large jogged right transistor 512. The large jogged configuration requires a minimum transistor width of 13.5 lambda, including the bent portion of the gate, to allow room for two offset contacts and two bends. Because of their larger size requirements, the large jogged configuration can only be used when the design constraints allow transistors in the layout to be 13.5 lambda wide or wider. However, despite their larger width, -lithe large jogged configuration has a pitch of only six lambda, which provides a more compact horizontal layout than the straight configuration.

c. Small Jogged Configuration The small jogged configuration is exemplified by a small left jogged transistor 514 and a small right jogged transistor 516. The small jogged configuration requires a minimum transistor width of seven lambda and has a pitch of seven lambda. Compared to the large jogged configuration, the small jogged configuration is relatively compact and does not require as much diffusion width. In addition, the small jogged configuration requires only a slightly larger gate size than the straight configuration and is more compact than the straight configuration.

d. Single Bend Configuration

The single bend configuration is exemplified by single bend transistor 518. Because of the difficulty in connecting wiring from other diffusion islands to a single bend transistor, single bend transistors are only used at the ends (first or last transistor) of a diffusion island where the off-angle polysilicon gate segment can be directed away from other transistors on the diffusion island. The single bend configuration requires at least 8.5 lambda of gate width, which is slightly larger than the minimum width required for a small jogged transistors and is considerably smaller than the minimum width required for a large jogged transistor. However, contact placement for this configuration meshes very well with that for the large jogged configuration.

2. SELECTING A TRANSISTOR CONFIGURATION

As previously described, a diffusion island layout is constructed left to right, starting with the first transistor located at the leftmost edge of the diffusion island and proceeding left to right across the diffusion island. The selection of a configuration is based upon the configuration of the transistor immediately to the left of the current transistor as well as a number of selection criteria. Selecting the configuration for the first (leftmost) transistor also involves considering addition selection criteria which are not applicable to the other transistors on a diffusion island.

The following objectives are considered during the selection of a transistor configuration: a. The large and small jogged configurations are generally preferred over the straight configuration because of the reduced diffusion island width obtained through using the jogged configurations. b. Simpler geometry is preferred over more complex geometry unless more complex geometry provides a more compact layout. This means that whenever a configuration other than the straight configuration is selected, a straight configuration is always considered to determine whether the straight configuration yields an equivalent or more compact layout. If so, then a straight configuration is used instead.

A table 600 in Figure 6 illustrates the effect of a prior transistor configuration and various selection criteria on the selection of a transistor configuration. The prior transistor refers to the transistor to the immediate left of the starting from the upper left hand corner of the table 600, the selection criteria one considered top to bottom for a particular prior transistor configuration. When a large or small jogged transistor configuration is selected, whether a left or right jog is used depends upon the vertical placement of the contact to the left of the present transistor. As illustrated in Figure 5, if the contact is placed near the bottom of the diffusion island, then a left jogged configuration is used. On the other hand, if the contact is placed closer to the top of the diffusion island, then a right jogged configuration is used.

Each of the criteria listed in table 600 are now discussed separately.

i. Design Constraints Require Straight Configuration

If the design constraints specify that a straight configuration is to be used for a particular transistor, then regardless of the configuration of the transistor to the left or the other selection criteria, a straight configuration is selected. The design constraints may require that a straight configuration be used for a particular transistor so that a contact can be positioned vertically to accommodate routing. This may occur for example, when after a layout solution has been constructed and during the routing of the diffusion islands a determination was made that additional space was required in this diffusion island for routing. Hence, routing between diffusion islands may require that a particular transistor be constructed with a straight configuration so that adjacent contacts can be moved up and down to accommodate routing. On the other hand, the design constraints may also specify that a straight configuration is to be used for a particular transistor because the desired transistor size specifies that only the straight configuration can be used. As discussed above, the straight configuration is the smallest, in terms of gate width, of the four configurations.

ii. No Contact to the Left

If there is no contact to the left of the present transistor, then the straight configuration is generally preferred because a jogged or single bend configuration does not provide a space savings.

iii. Desired Transistor Size

Assuming that the design constraints don't require that a straight configuration be used and there is a contact to the left of the present transistor, then the selection of a configuration depends upon both the desired transistor size, as specified by the design constraints, and the configuration of the prior transistor. If there is no prior transistor configuration, then the present transistor is the first transistor in the diffusion island and the order of configuration preference is large jogged, single bend, small jogged and straight, depending upon the desired transistor size. The large jogged configuration is preferred because it provides the most compact layout. If the configuration of prior transistor is straight, then the order of configuration preference is large jogged, single bend(last transistor only), small jogged and straight, depending upon the desired fransistor size. Again, a large jogged configuration is preferred because it provides the most compact layout. Also, as previously discussed, the single bend configuration is only used with the first and last transistors in the diffusion island.

If the configuration of the prior transistor is large jogged, then the order of configuration preference is large jogged, small jogged, single bend (last transistor only) and straight, depending upon the desired transistor size.

If the configuration of the prior transistor is small jogged, then the order of configuration preference is large jogged, small jogged and straight, depending upon the desires transistor size. The and single bend configuration is not used next to a small jogged transistor because the single bend configuration does not fit well with a small jogged configuration. Consequently, if the configuration of the last transistor in a diffusion island is being selected and the configuration of the prior transistor is small jogged, then the single bend configuration is not used for the last transistor because a single bend transistor would not provide the smallest layout. Instead, the small jogged or straight configuration is used depending upon whether a smaller diffusion island is provided by using the small jogged configuration instead of the straight configuration. Finally, if the configuration of the prior transistor is single bend, then the order of configuration preference is large jogged, single bend(last transistor only), and straight, depending upon the desired transistor size. Since the prior transistor configuration is a single bend and the single bend configuration may only be used with the first and last transistors in a diffusion island, selecting the single bend configuration for a transistor when the configuration of the prior transistor is single bend requires that the diffusion island have only two transistors.

Although in the various figures the jogs are generally illustrated in the same vertical location, embodiments of the invention also provide the capability to adjust the vertical position of the jogs on a transistor by transistor basis. Also, embodiments of the invention described herein are also applicable to orthogonal geometry.

3. CONTACT PLACEMENT In general, contact placement starts with the first or leftmost contact on the diffusion island and proceeds left to right across the diffusion island. According to one embodiment of the invention, the default location for the first contact is towards the top of the diffusion island.

However, there are several factors which affect the placement of a contact.

First, contacts which are to be connected to the supply rail are preferably placed either at the top or bottom of the diffusion island based upon the proximity to the supply rail. Similarly, contacts which are to be connected to the ground rail are preferably placed closest to the ground rail.

Another factor which affects the placement of contacts is the position of the last contact in the diffusion island to the left of the current diffusion island. Specifically, if the last contact in the diffusion island to the left of the current diffusion island is at the top of the diffusion island, then the " effective width" of the island may be reduced if first contact is placed at the bottom of the diffusion island. As illustrated in Figure 7, a first diffusion island 702 includes a large left jogged fransistor 704 and a last contact 706, which allows a right edge 708 of diffusion island 702 to be shaped to meet the design rules. During the construction of diffusion island 710, a first contact 712 is forced to the bottom of diffusion island 710 so that a left edge 714 of diffusion island 710 can be shaped to conform to right edge 708. This allows diffusion island 710 to be placed closer to diffusion island 702, reducing the overall size of a cell containing diffusion islands 702 and 710. According to an embodiment of the invention, the contacts do not actually have to be placed during the construction of a layout solution. Instead, they can simply be accounted for in the layout and then placed during a later phase of layout construction. Also, although contacts are depicted as square in shape, contacts of any shape may be used, for example, octagon shaped contacts.

4. OTHER CONSIDERATIONS

In constructing a diffusion island, several other considerations also affect the layout and size of a diffusion island. One consideration is whether additional gate length is to be added at the top or bottom of the diffusion island, if at all. This is affected by the under supply limit design constraint which specifies a maximum distance above the top contact and the top edge of the diffusion island when the supply is at the top; below the bottom when the supply is at the bottom. The under supply limit directly affects how far underneath the power supply wire that polysilicon gates and diffusion may be drawn. Since according to one embodiment of the invention the height of a diffusion island is under only that portion of the diffusion island not under a supply rail, then if only supply contacts are adjacent to the supply rail, then a portion of the diffusion island can be positioned under the supply rail, subject to the under supply limits.

Consider the example diffusion island 800 illustrated in Figure 8A. Diffusion island 800 illustrates the use of a minimum under supply limit which requires that the top edge 802 of diffusion island 800 be no more than two lambda from the top of the contact located closest to top edge 802. In Figure 8A, contacts 804, 806, 808 are closest to top edge 802. Since top edge 802 is straight, the routing space provided above diffusion island 800 is maximized, which allows polysilicon to be routed above the diffusion island and under the supply wire if it is not too close to another diffusion island or a gate extension. Since transistors 810, 812, 814, 816 do not have the same lower endpoint, the lower ends of transistors 810, 812, 814, 816 must be separated at the bottom by at least four lambda to meet the diffusion extension and diffusion/polysilicon spacing rules. Consequently, transistor 812 is not be jogged since there is no advantage provided by using a jogged configuration.

In Figure 8B, the under supply limit has been increased to three lambda and diffusion island 800 has been reconstructed. Increasing the under supply limit provides more flexibility in shaping diffusion island 800. Specifically, an extra end segment 818 has been added to the bottom of diffusion island 800 while another extra end segment 820 has been added to the top of diffusion island 800, which changes the shape of top edge 802.

The new shape of diffusion island 800 allows transistors 810, 812, 814, 816 to be jogged and the original length maintained since transistors 812 and 814 have the same lower vertical coordinate. Another consideration is whether the design constraint, or a user parameter specifies that space is to be reserved in a diffusion island for other features, such as a well tie, to be added at a later time.

According to one embodiment of the invention, the selection of a transistor configuration and placements are considered in the order described herein. However, a particular order is not required by the invention.

IV. INITIAL DIFFUSION ISLAND PLACEMENT

According to one embodiment of the invention, a heuristic approach is used to determine an initial diffusion island placement based upon a set of criteria, which includes the total wire length for connecting the diffusion islands. If the cell height allows for it, diffusion islands are stacked on top of each other to minimize the length of connection wires during the routing phase.

Various island diffusion placement approaches are known in the art and may be used here.

V. ADJUSTING DIFFUSION ISLAND PLACEMENT AND ROUTING THE DIFFUSION ISLANDS

The IC layout synthesis tool of the invention does not depend upon a particular routing approach. Accordingly, routing approaches employing horizontal, vertical or diagonal metal routing may be employed without departing from the scope of the invention. For example, channel routing may be used in which the polysilicon layers usually run vertically between the top and bottom of a cell and the metal wires run horizontally. With channel routing, routing conflicts are usually resolved by increasing the height of a layout so that the metal can be routed around the conflict. During the routing of the diffusion islands, the diffusion islands may need to be realigned to allow room for polyinterconnect or metal wires. Sometimes this involves stacking diffusion islands vertically if the design constraints allow a taller cell. This typically occurs with data paths which tend to increase the width of the layout region containing the cell. In some situations, cell width can be significantly reduced by stacking diffusion islands. However, according to one embodiment of the invention, if the router successfully routes one or more diffusion islands, then the arrangement/placement of those diffusion islands is not changed when the island placement phase is repeated. VI. RECONSTRUCTION OF THE DIFFUSION ISLANDS

For example, referring to Figure 5, the routing software may wish to run a horizontal metal wire between the contacts immediately to the left and right of large jogged transistor 510 and therefore may update the design constraints to specify that large jogged transistor 570 be changed to a straight configuration to allow the left and right contacts to be adjusted vertically.

As previously discussed, the straight configuration allows more adjustment capability for a given devise width.

Once the process is completed, the IC layout synthesis tool provides layout information which can be used by a simulation tool to evaluate the performance of the layout or can be used by a fabrication facility to fabricate the layout on an IC. According to one embodiment of the invention, the IC layout synthesis tool provides an output file which contains information which specifies all of the polygons which comprise the requested layout. However, the output of the layout synthesis tool of the invention is not limited to any specific output format or content.

Accordingly, various output formats and contents may be used without departing from the scope of the invention.

HARDWARE OVERVIEW Figure 9 is a block diagram of a computer system 900 upon which an embodiment of the invention may be implemented. Computer system 900 includes a bus 902 or other communication mechanism for communicating information, and a processor 904 coupled with bus 902 for processing information. Computer system 900 also includes a main memory 906, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 902 for storing information and instructions to be executed by processor 904. Main memory 906 also may be used for storing temporary variables or other intermediate information during execution of instructions by processor 904. Computer system 900 also includes a read only memory (ROM) 908 or other static storage device coupled to bus 902 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic disk or optical disk, is also provide and coupled to bus 902 for storing information and instructions.

Computer system 900 may also be coupled via bus 902 to a display 912, such as a cathode ray tube (CRT), for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is also provided and coupled to bus 902 for communicating information and command selections to processor 904. Another type of user input device is cursor control 916, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 904 and for controlling cursor movement on display 912. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), which allows the device to specify positions in a plane.

The invention is related to the use of computer system 900 to provide for the synthesis of IC layouts using non-orthogonal geometry. According to one embodiment of the invention, the synthesis of IC layouts using non-orthogonal geometry is provided by computer system 900 in response to processor 904 executing sequences of instructions contained in main memory 906. Such instructions may be read into main memory 906 from another computer-readable medium, such as storage device 910. Execution of the sequences of instructions contained in main memory 906 causes processor 904 to perform the process steps previously described. In alternative embodiments, hard- ired circuitry may be used in place of or in combination with software instructions to implement the invention. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.

Although embodiments of the invention have been described in the context of IC layouts including transistors, the invention is applicable to IC layouts including any type of integrated circuit components or devices, such as resistors, capacitors, logic gates, or any other type of IC devices. Consequently, in the context of IC devices, the IC devices are ordered and divided into IC device groups.

Another consideration is whether the design constraint, or a user parameter specifies that space is to be reserved in a diffusion island for other features, such as a well tie, to be added at a later time.

The invention provides several advantages over prior approaches for generating IC layouts. First, the IC layout synthesis tool of the invention generates compact, design-rule correct layouts using non-orthogonal geometry, which do not require separate compaction to either compress the layout or to ensure that the layout meets the design rules. More importantly, the layouts are automatically generated on a computer-based system, a leaf cell library can be generated much more quickly than by hand, and yet provide more compact layouts than is possible with existing layout synthesis tools. This allows a designer to quickly generate different versions of a leaf cell library by making small changes to the design rules and routing criteria. The different versions can then be used to determine both an optimal layout as well as to judge the effects (costs) of design rule tradeoffs more efficiently.

In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

For example, faster cell generation allows more cell configurations to be created (alternate logic gates, drive strength variants), aiding logic synthesis. Also the ability to selectively vary cell height allows many layout possibilities to be tried, allowing a height that the standard cell place and route software can take advantage of (e.g. using routing space inside the cell), yielding an overall smaller IC (currently the "best" height is estimated).

Claims

What is claimed is:

1. A method for generating a data representation of an integrated circuit (IC) layout, the method comprising the computer-implemented steps of: a) determining an ordering of a set of IC devices to be included in the IC layout based upon predetermined electrical connections between the IC devices; b) establishing one or more IC device groups based upon the determined ordering of the set of IC devices; c) generating a data representation of an IC device group layout for each of the one or more established IC device groups based upon predetermined design criteria; d) determining a relative physical arrangement of the IC device group layouts based upon predetermined routing criteria; e) determining electrical connections between the IC device group layouts based upon the predetermined electrical connections between the devices and the relative physical arrangement of the IC device group layouts; and f) generating the data representation of the IC layout to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts.

2. The method of Claim 1 , wherein the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon predetermined design criteria further comprises the step of for each of the one or more IC device groups, performing the steps of a) generating a first layout solution based upon the predetermined design criteria, b) generating a second layout solution based upon the predetermined design criteria, and c) designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria which includes the overall size of the first and second layout solutions.

3. The method of Claim 2, wherein: the set of cost function criteria further includes the overall size of a layout solution and the polygon count of a layout solution, and the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria further comprises the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon both the overall size of the first and second layout solutions and the polygon count of the first and second layout solutions.

The method of Claim 3, wherein: the set of cost function criteria further includes the proximity of supply contacts contained in a layout solution to power supply lines contained in the layout solution, and the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria further comprises the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon both the overall size of the first and second layout solutions, the polygon count of the first and second layout solutions and the proximity of supply contacts to power supply lines contained in the first and second layout solutions.

The method of Claim 3, wherein: the set of cost function criteria further includes the proximity of all contacts contained in a layout solution to power supply lines contained in the layout solution, and the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria further comprises the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon both the overall size of the first and second layout solutions, the polygon count of the first and second layout solutions and the proximity of all contacts to power supply lines contained in the first and second layout solutions.

The method of Claim 1, wherein: the IC layout includes non-orthogonal geometry, and the step of generating the data representation of the IC layout to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts further comprises the step of generating the data representation of the IC layout including non-orthogonal geometry to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts.

The method of Claim 1, wherein the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon predetermined design criteria further comprises for each IC device group performing the step of selecting a configuration from a set of configurations for each IC device in the device group based upon a set of selection criteria, and wherein the set of configurations includes at least a straight configuration, a large jogged configuration, a small jogged configuration and a single bend configuration.

8. The method of Claim 7, wherein: the selection criteria includes whether a straight configuration is required, the proximity of contacts to the IC device, the desired IC device size and the configuration of adjacent IC devices in the IC device group, and the step of selecting a configuration for each IC device in the device group based upon a set of selection criteria further comprises the step of selecting a configuration for each device contained in the device group based upon whether a straight configuration is required, the proximity of contacts the IC device, the desired IC device size and the configuration of adjacent IC devices in the IC device group.

9. The method of Claim 1, further including the steps of a) updating the predetermined design criteria, and b) regenerating a data representation of an IC device group layout for at least one of the one or more IC device groups based upon predetermined design criteria.

10. The method of Claim 1 , wherein: the method further comprises the step of receiving IC device data which specifies the predetermined electrical connections between the IC devices, design criteria data and routing criteria data, the step of determining an ordering of a set of IC devices to be included in the IC layout based upon predetermined electrical connections between the IC devices further comprises the step of determining an ordering of a set of IC devices to be included in the IC layout based upon the IC device data, the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon predetermined design criteria further comprises the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon the design criteria data, and the step of determining a relative physical arrangement of the IC device group layouts based upon predetermined routing criteria further comprises the step of determining a relative physical arrangement of the IC device group layouts based upon the routing criteria data.

11. A method for generating a data representation of an integrated circuit (IC) layout, the method comprising the computer-implemented steps of: a) generating a first data representation of the IC layout based upon a set of design criteria, b) generating a second data representation of the IC layout based upon the set of design criteria, c) selecting either the first data representation or the second data representation as the data representation for the IC layout based upon a set of cost function criteria which includes the overall size of an IC device layout.

12. The method of Claim 11 , wherein the set of cost function criteria further includes the number of polygons contained in an IC device layout, and wherein the step of selecting either the first data representation or the second data representation as the data representation for the IC device based upon a set of cost function criteria further comprises the step of selecting either the first data representation or the second data representation as the data representation for the IC device layout based upon both the overall size and the polygon count of an IC device layout.

13. The method of Claim 12, wherein the set of cost function criteria further includes the proximity of supply contacts to power supply lines contained in an IC device layout, and wherein the step of selecting either the first data representation or the second data representation as the data representation for the IC device layout based upon a set of cost function criteria further comprises the step of selecting either the first data representation or the second data representation as the data representation for the IC device layout based upon the overall size, the polygon count and the proximity of supply contacts to power supply lines of an IC device layout.

14. The method of Claim 11 , wherein: the IC layout includes non-orthogonal geometry, the step of generating a first data representation of the IC layout based upon a set of design criteria further comprises the step of generating a first data representation of the IC layout including non-orthogonal geometry based upon a set of design criteria, and the step of generating a second data representation of the IC layout based upon the set of design criteria further comprises the step of generating a second data representation of the IC layout including non-orthogonal geometry based upon the set of design criteria.

15. A computer-readable medium having stored thereon a plurality of sequences of instructions for generating a data representation of an integrated circuit (IC) layout, the plurality of sequences of instructions including sequences of instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of: a) determining an ordering of a set of IC devices to be included in the IC layout based upon predetermined electrical connections between the IC devices; b) establishing one or more IC device groups based upon the determined ordering of the set of IC devices; c) generating a data representation of an IC device group layout for each of the one or more established IC device groups based upon predetermined design criteria; d) determining a relative physical arrangement of the IC device group layouts based upon predetermined routing criteria; e) determining electrical connections between the IC device group layouts based upon the predetermined electrical connections between the devices and the relative physical arrangement of the IC device group layouts; and f) generating the data representation of the IC layout to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts.

16. The computer-readable medium of Claim 15, wherein the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon predetermined design criteria further comprises the step of for each of the one or more IC device groups, performing the steps of a) generating a first layout solution based upon the predetermined design criteria, b) generating a second layout solution based upon the predetermined design criteria, and c) designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria which includes the overall size of the first and second layout solutions.

17. The computer-readable medium of Claim 16, wherein: the set of cost function criteria further includes the overall size of a layout solution and the polygon count of a layout solution, and the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon a set of cost function criteria further comprises the step of designating either the first layout solution or the second layout solution as the IC device group layout for the IC device group based upon both the overall size of the first and second layout solutions and the polygon count of the first and second layout solutions.

18. The computer-readable medium of Claim 15, wherein: the IC layout includes non-orthogonal geometry, and the step of generating the data representation of the IC layout to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts further comprises the step of generating the data representation of the IC layout including non-orthogonal geometry to reflect both the relative physical arrangement of the IC device group layouts and the determined electrical connections between the IC device group layouts.

19. The computer-readable medium of Claim 15, wherein: the step of generating a data representation of an IC device group layout for each of the one or more IC device groups based upon predetermined design criteria further comprises for each IC device group performing the step of selecting a configuration from a set of configurations for each IC device in the device group based upon a set of selection criteria, and the set of configurations includes at least a straight configuration, a large jogged configuration, a small jogged configuration and a single bend configuration.

20. The computer-readable medium of Claim 15, further including the steps of a) updating the predetermined design criteria, and b) regenerating a data representation of an IC device group layout for at least one of the one or more IC device groups based upon predetermined design criteria.

21. A computer system for automatically generating a data representation of an integrated circuit (IC) layout containing non-orthogonal geometry, the computer system including one or more processors and a memory comprising: a) a set of IC device data which specifies electrical connections between IC devices to be included in the IC layout; b) a set of design criteria indicative of a desired data representation of an IC device group layout for one or more IC device groups contained in the IC layout; c) a set of routing criteria indicative of a desired physical arrangement of layouts for the one or more IC device groups, and d) a set of computer-readable instructions which when executed by the one or more processors cause the one or more processors to perform the step of generating the data representation of the IC layout containing non-orthogonal geometry.

22. The computer system of Claim 21 , wherein the set of computer readable instructions further includes instructions for performing the steps of: a) determining an ordering of a set of IC devices to be included in the IC layout based upon the set of IC device data; b) establishing one or more IC device groups based upon the determined ordering of the set of IC devices; c) generating a data representation of an IC device group layout for each of the one or more established IC device groups based upon the set of design criteria; d) determining a relative physical arrangement of the IC device group layouts based upon the set of routing criteria; and e) determining electrical connections between the IC device group layouts based upon both the set of IC device data and the relative physical arrangement of the IC device group layouts.