WO1999017371A1

WO1999017371A1 - Metal gate fermi-threshold field effect transistors

Info

Publication number: WO1999017371A1
Application number: PCT/US1998/019761
Authority: WO
Inventors: Michael W. Dennen; William R. Richards, Jr.
Original assignee: Thunderbird Technologies, Inc.
Priority date: 1997-09-26
Filing date: 1998-09-22
Publication date: 1999-04-08
Also published as: AU9499698A; JP2002527882A; TW432636B

Abstract

A Fermi-threshold field effect transistor includes a metal gate (28') rather than a contra-doped polysilicon gate. The metal gate can lower the threshold voltage of the Fermi-FET without degrading other desirable characteristics of the Fermi-FET. The metal gate may be a pure metal gate or a metal alloy gate such as a metal silicide gate. The metal gate preferably includes metal having a work function between that of P-type polysilicon and N-type polysilicon.

Description

METAL GATEFERMI-THRESHOLDFIELD EFFECTTRANSISTORS

Field of the Invention

This invention relates to field effect transistor devices and more particularly to integrated circuit field effect transistors.

Background of the Invention

Field effect transistors (FET) have become the dominant active device for very large scale integration (VLSI) and ultra large scale integration (ULSI) applications, such as logic devices, memory devices and microprocessors, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving the speed and integration density of FETs, and on lowering the power consumption thereof.

A high speed, high performance field effect transistor is described in U.S. Patents 4,984,043 and 4,990,974, both by Albert W. Vinal, both entitled Fermi Threshold Field Effect Transistor and both assigned to the assignee of the present invention. These patents describe a metal oxide semiconductor field effect transistor (MOSFET) which operates in the enhancement mode without requiring inversion, by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. As is well known to those having skill in the art, Fermi potential is defined as that potential for which an energy state in a semiconductor material has a probability of one-half of being occupied by an electron. As described in the above mentioned Ninal patents, when the threshold voltage is set to twice the Fermi potential, the dependence of the threshold voltage on oxide thickness, channel length, drain voltage and substrate doping is substantially eliminated. Moreover, when the threshold voltage is set to twice the Fermi potential, the vertical electric field at the substrate face between the oxide and channel is minimized, and is in fact substantially zero. Carrier mobility in the channel is thereby maximized, leading to a high speed device with greatly reduced hot electron effects. Device performance is substantially independent of device dimensions.

Notwithstanding the vast improvement of the Fermi-threshold FET compared to known FET devices, there was a need to lower the capacitance of the Fermi-FET device. Accordingly, in U.S. Patents 5,194,923 and 5,369,295, both by Albert W. Vinal, and both entitled Fermi Threshold Field Effect Transistor With Reduced Gate and Diffusion Capacitance, a Fermi-FET device is described which allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction. Accordingly, the average depth of the channel charge requires inclusion of the permittivity of the substrate as part of the gate capacitance. Gate capacitance is thereby substantially reduced.

As described in the aforesaid '295 and '923 patents, the low capacitance Fermi-FET is preferably implemented using a Fermi-tub region having a predetermined depth and a conductivity type opposite the substrate and the same conductivity type as the drain and source. The Fermi-tub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub within the tub boundaries. The Fermi-tub forms a unijunction transistor, in which the source, drain, channel and Fermi-tub are all doped the same conductivity type, but at different doping concentrations. A low capacitance Fermi-FET is thereby provided. The low capacitance Fermi-FET including the Fermi-tub will be referred to herein as a "low capacitance Fermi- FET" or a "Tub-FET".

Notwithstanding the vast improvement of the Fermi-FET and the low capacitance Fermi-FET compared to known FET devices, there was a continuing need to increase the current per unit channel width which is produced by the Fermi-FET. As is well known to those skilled in the art, higher current Fermi-FET devices will allow greater integration density, and or much higher speeds for logic devices, memory devices, microprocessors and other integrated circuit devices. Accordingly, U.S. Patent 5,374,836 to Albert W. Vinal and the present coinventor Michael W. Dennen entitled High Current Fermi-Threshold Field Effect Transistor, describes a Fermi-FET which includes an injector region of the same conductivity type as the Fermi-tub region and the source region, adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate to the relatively low doping concentration of the Fermi-tub and the relatively high doping concentration of the source. The injector region controls the depth of the carriers injected into the channel and enhances injection of carriers in the channel, at a predetermined depth below the gate. Transistors according to U.S. Patent 5,374,836 will be referred to herein as a "high current Fermi-FET".

Preferably, the source injector region is a source injector tub region which surrounds the source region. A drain injector tub region may also be provided. A gate sidewall spacer which extends from adjacent the source injector region to adjacent the gate electrode of the Fermi-FET may also be provided in order to lower the pinch-off voltage and increase saturation current for the Fermi- FET. A bottom leakage control region of the same conductivity type as the substrate may also be provided. Notwithstanding the vast improvement of the Fermi-FET, the low capacitance Fermi-FET and the high current Fermi-FET compared to known FET devices, there was a continuing need to improve operation of the Fermi-FET at low voltages. As is well known to those having skill in the art, there is currently much emphasis on low power portable and/or battery-powered devices which typically operate at power supply voltages of five volts, three volts, one volt or less.

For a given channel length, lowering of the operating voltage causes the lateral electric field to drop linearly. At very low operating voltages, the lateral electric field is so low that the carriers in the channel are prevented from reaching saturation velocity. This results in a precipitous drop in the available drain current. The drop in drain current effectively limits the decrease in operating voltage for obtaining usable circuit speeds for a given channel length.

In order to improve operation of the Tub-FET at low voltages, U.S. Patent 5,543,654 to the present coinventor Michael W. Dennen entitled Contoured- Tub Fermi-Threshold Field Effect Transistor and Method of Forming Same, describes a Fermi-FET which includes a contoured Fermi-tub region having nonuniform tub depth. In particular, the Fermi-tub is deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. Diffusion capacitance is thereby reduced compared to a Fermi-tub having a uniform tub depth, so that high saturation current is produced at low voltages.

In particular, a contoured-tub Fermi-threshold field effect transistor according to the '654 patent includes a semiconductor substrate of first conductivity type and spaced-apart source and drain regions of second conductivity type in the semiconductor substrate at a face thereof. A channel region of the second conductivity type is also formed in the semiconductor substrate at the substrate face between the spaced-apart source and drain regions. A tub region of the second conductivity type is also included in the semiconductor substrate at the substrate face. The tub region extends a first predetermined depth from the substrate face to below at least one of the spaced-apart source and drain regions, and extends a second predetermined depth from the substrate face to below the channel region. The second predetermined depth is less than the first predetermined depth. A gate insulating layer and source, drain and gate contacts are also included. A substrate contact may also be included.

Preferably, the second predetermined depth, i.e. the depth of the contoured-tub adjacent the channel, is selected to satisfy the Fermi-FET criteria as defined in the aforementioned U.S. Patents 5,194,923 and 5,369,295. In particular, the second predetermined depth is selected to produce zero static electric field perpendicular to the substrate face at the bottom of the channel with the gate electrode at ground potential. The second predetermined depth may also be selected to produce a threshold voltage for the field effect transistor which is twice the Fermi potential of the semiconductor substrate. The first predetermined depth, i.e. the depth of the contoured-tub region adjacent the source and/or drain is preferably selected to deplete the tub region under the source and/or drain regions upon application of zero bias to the source and/or drain contact. As the state of the art in microelectronic fabrication has progressed, fabrication linewidths have been reduced to substantially less than one micron. These decreased linewidths have given rise to the "short channel" FET wherein the channel length is substantially less than one micron and is generally less than one half micron with current processing technology .

The low capacitance Fermi-FET of Patents 5,194,923 and 5,369,295, the high current Fermi-FET of Patent 5,374,836 and the contoured tub Fermi-FET of U.S. Patent 5,543,654 may be used to provide a short channel FET with high performance capabilities at low voltages. However, it will be recognized by those having skill in the art that as linewidths decrease, processing limitations may limit the dimensions and conductivities which are attainable in fabricating an FET. Accordingly, for decreased linewidths, processing conditions may require reoptimization of the Fermi-FET transistor to accommodate these processing limitations. Reoptimization of the Fermi-FET transistor to accommodate processing limitations was provided in Application Serial No. 08/505,085 to the present coinventor Michael W. Dennen and entitled "Short Channel Fermi- Threshold Field Effect Transistors", assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. The Short Channel Fermi-FET of Application Serial No. 08/505,085, referred to herein as the "short channel Fermi-FET", includes spaced-apart source and drain regions which extend beyond the Fermi-tub in the depth direction and which may also extend beyond the Fermi-rub in the lateral direction. Since the source and drain regions extend beyond the tub, a junction with the substrate is formed which can lead to a charge-sharing condition. In order to compensate for this condition, the substrate doping is increased. The very small separation between the source and drain regions leads to a desirability to reduce the tub depth. This causes a change in the static electrical field perpendicular to the substrate at the oxide: substrate interface when the gate electrode is at threshold potential. In typical long channel Fermi-FET transistors, this field is essentially zero. In short channel devices the field is significantly lower than a MOSFET transistor, but somewhat higher than a long channel Fermi-FET. In particular, a short channel Fermi-FET includes a semiconductor substrate of first conductivity type and a tub region of second conductivity type in the substrate at a surface thereof which extends a first depth from the substrate surface. The short channel Fermi-FET also includes spaced-apart source and drain regions of the second conductivity type in the tub region. The spaced-apart source and drain regions extend from the substrate surface to beyond the first depth, and may also extend laterally away from one another to beyond the tub region.

A channel region of the second conductivity type is included in the tub region, between the spaced-apart source and drain regions and extending a second depth from the substrate surface such that the second depth is less than the first depth. At least one of the first and second depths are selected to minimize the static electric field peφendicular to the substrate surface, from the substrate surface to the second depth when the gate electrode is at threshold potential. For example, a static electric field of 10⁴ V/cm may be produced in a short channel Fermi-FET compared to a static electric field of more than 10⁵ V/cm in a conventional

MOSFET. In contrast, the Tub-FET of U.S. Patents 5,194,923 and 5,369,295 may produce a static electric field of less than (and often considerably less than) 10³ V/cm which is essentially zero when compared to a conventional MOSFET. The first and second depths may also be selected to produce a threshold voltage for the field effect transistor which is twice the Fermi-potential of the semiconductor substrate, and may also be selected to allow carriers of the second conductivity type to flow from the source region to the drain region in the channel region at the second depth upon application of the threshold voltage to the gate electrode, and extending from the second depth toward the substrate surface upon application of voltage to the gate electrode beyond the threshold voltage of the field effect transistor, without creating an inversion layer in the channel. The transistor further includes a gate insulating layer and source, drain and gate contacts. A substrate contact may also be included.

Continued miniaturization of integrated circuit field effect transistors has reduced the channel length to well below one micron. This continued miniaturization of the transistor has often required very high substrate doping levels. High doping levels and the decreased operating voltages which may be required by the smaller devices, may cause a large increase in the capacitance associated with the source and drain regions of both the Fermi-FET and conventional MOSFET devices.

In particular, as the Fermi-FET is scaled to below one micron, it is typically necessary to make the tub depth substantially shallower due to increased Drain Induced Barrier Lowering (DIBL) at the source. Unfortunately, even with the changes described above for the short channel Fermi-FET, the short channel Fermi-FET may reach a size where the depths and doping levels which are desired to control Drain Induced Barrier Lowering and transistor leakage become difficult to manufacture. Moreover, the high doping levels in the channel may reduce carrier mobility which also may reduce the high current advantage of the Fermi- FET technology. The ever higher substrate doping levels, together with the reduced drain voltage may also cause an increase in the junction capacitance. A short channel Fermi-FET that can overcome these potential problems was provided in Application Serial No. 08/597,711 to the present coinventor Michael W. Dennen and entitled "Short Channel Fermi-Threshold Field Effect Transistors Including Drain Field Termination Region and Methods of Fabricating Same " assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. This Fermi-FET includes drain field terminating means between the source and drain regions for reducing and preferably preventing injection of carriers from the source region into the channel as a result of drain bias. A short channel Fermi-FET including drain field terminating means, referred to herein as a "Vinal-FET" in memory of the now deceased inventor of the Fermi-FET, prevents excessive Drain Induced Barrier Lowering while still allowing low vertical field in the channel, similar to a Fermi- FET. In addition, the Vinal-FET permits much higher carrier mobility and simultaneously leads to a large reduction in source and drain junction capacitance.

The drain field terminating means is preferably embodied by a buried contra-doped layer between the source and drain regions and extending beneath the substrate surface from the source region to the drain region. In particular, a Vinal-FET includes a semiconductor substrate of first conductivity type and a tub region of second conductivity type in the substrate at a surface thereof. Spaced apart source and drain regions of the second conductivity type are included in the tub region at the substrate surface. A buried drain field terminating region of the first conductivity type is also included in the tub region. The buried drain field terminating region extends beneath the substrate surface from the source region to the drain region. A gate insulating layer and source, drain and gate electrodes are also included. Accordingly, the Vinal-FET may be regarded as a Fermi-FET with an added contra-doped buried drain field terminating region which prevents drain bias from causing carriers to be injected from the source region into the tub region. As the channel length and integration density of integrated circuit field effect transistors continues to increase, the operating voltages of the transistors has also continued to decrease. This decrease is further motivated by the increasing use of integrated circuits in portable electronic devices, such as laptop computers, cellular telephones, personal digital assistants and the like. As the operating voltage of the field effect transistors decrease, it is also generally desirable to lower the threshold voltage.

Accordingly, in order to provide short channel Fermi-FETs for low voltage operation, it is desirable to reduce the threshold voltage, for example to about half a volt or less. However, this reduction in threshold voltage should not produce performance degradation in other areas of the Fermi-FET. For example, a reduction in threshold voltage should not unduly increase the leakage current of the Fermi-FET, or unduly decrease the saturation current of the Fermi-FET.

Summary of the Invention It is therefore an object of the present invention to provide improved

Fermi-threshold field effect transistors (Fermi-FET).

It is another object of the present invention to provide improved Fermi-FETs which are adapted for short channel lengths.

It is still another object of the present invention to provide short channel Fermi-FETs which can use low operating voltages.

It is yet another object of the present invention to provide short channel low voltage Fermi-FETs that can have low threshold voltages. It is still another object of the present invention to provide short channel, low-voltage, low threshold voltage Fermi-FETs that can maintain high saturation currents and low leakage currents.

These and other objects are provided, according to the present invention, by a Fermi-threshold field effect transistor that includes a metal gate. A contra-doped polysilicon gate is not used directly on the gate insulating layer. The metal gate can lower the threshold voltage of the Fermi-FET without degrading other desirable characteristics of the Fermi-FET.

In particular, Fermi-threshold field effect transistors (Fermi-FETs) according to the present invention include spaced apart source and drain regions in an integrated circuit substrate and a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions. A gate insulating layer is included on the integrated circuit substrate between the spaced apart source and drain regions. A metal gate is included directly on the insulating layer. Stated differently, the Fermi-FET includes a doped polysilicon-free gate directly on the insulating layer.

The metal gate Fermi-FET may be embodied as an original Fermi- FET, a Tub-FET, a high current Fermi-FET, a contoured-Tub Fermi-FET, a short- channel Fermi-FET, a Vinal-FET or other embodiments of the Fermi-FET. The metal gate may be a pure metal gate or a metal alloy gate, such as a metal suicide gate. The metal suicide gate may be formed by reacting silicon, including doped or undoped polysilicon, with a metal or alloy.

The metal gate may include multiple layers, as long as the gate layer that is directly on the gate insulating layer comprises metal (including pure metal or metal alloy such as metal suicide). Doped polysilicon may be included in the gate, as long as the doped polysilicon is not directly on the gate insulating layer. Thus, the contact potential between the gate insulating layer and the gate is not determined by polysilicon doping.

Preferably, the metal gate comprises metal having a work function between that of P-type polysilicon and N-type polysilicon. More preferably, the metal gate comprises metal having a work function of about 4.85 volts, i.e. midway between the work function of P-type polysilicon and N-type polysilicon. Metal gate Fermi-FETs according to the present invention can produce a low threshold voltage while retaining low leakage current and high saturation current. Thus, they may be particularly suitable for low voltage operation.

Brief Description of the Drawings Figure 1 illustrates a cross-sectional view of an N-channel high current Fermi-FET according to U.S. Patent No. 5,374,836.

Figure 2 A illustrates a cross-sectional view of a first embodiment of a short channel low leakage current Fermi-FET according to U.S. Patent 5,374,836. Figure 2B illustrates a cross-sectional view of a second embodiment of a short channel low leakage current Fermi-FET according to U.S. Patent 5,374,836.

Figure 3 illustrates a cross-sectional view of an N-channel contoured-tub Fermi-FET according to U.S. Patent No. 5,543,654.

Figure 4 illustrates a cross-sectional view of an N-channel short channel Fermi-FET according to U.S. Patent No. 5,543,654.

Figure 5 illustrates a cross-sectional view of a second embodiment of an N-channel short channel Fermi-FET according to Application Serial No. 08/505,085.

Figure 6 illustrates a cross-sectional view of a first embodiment of a Vinal-FET according to Application Serial No. 08/597,711.

Figure 7 illustrates a cross-sectional view of a second embodiment of a Vinal-FET according to Application Serial No. 08/597,711. Figure 8 illustrates contributions to threshold voltage in a Fermi-

FET transistor.

Figure 9 graphically illustrates drain current as a function of applied gate bias for Fermi-FET transistors having varying Fermi-tub depths.

Figure 10 graphically illustrates drain current as a function of applied gate bias for various levels of Fermi-Tub doping.

Figure 11 illustrates a cross-sectional view of an embodiment of a metal gate Fermi-FET according to the present invention. Figure 12 graphically illustrates work functions for various materials.

Figure 13 graphically illustrates drain current as a function of applied gate bias for Fermi-FET transistors that include various gate materials. Figure 14 graphically illustrates drain current as a function of applied gate bias for various Fermi-FET transistors, on a logarithmic scale.

Figure 15 graphically illustrates drain current as a function of applied gate bias for various Fermi-FET transistors, on a linear scale.

Figure 16 is a schematic circuit diagram of an inverter. Figure 17 graphically illustrates output voltage as a function of time for inverters that include field effect transistors of various technologies.

Detailed Description of Preferred Embodiments

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

Before describing metal gate Fermi-threshold field effect transistors of the present invention, a Fermi-threshold field effect transistor with reduced gate and diffusion capacitance of U.S. Patents 5,194,923 and 5,369,295 (also referred to as the "low capacitance Fermi-FET" or the "Tub-FET") will be described as will a high current Fermi-Threshold field effect transistor of U.S. Patent 5,374,836. A contoured-tub Fermi-FET according to U.S. Patent 5,543,654 will also be described. Short channel Fermi-FETs of Application Serial No. 08/505,085 will also be described. Vinal-FETs of Application Serial No. 08/597,711 will also be described. A more complete description may be found in these patents and applications, the disclosures of which are hereby incorporated herein by reference. Metal gate Fermi-FETs according to the present invention will then be described.

Fermi-FET With Reduced Gate and Diffusion Capacitance

The following summarizes the low capacitance Fermi-FET including the Fermi-tub. Additional details may be found in U.S. Patents 5,194,923 and 5,369,295.

Conventional MOSFET devices require an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction.

The depth of the inversion layer is typically lOOA or less. Under these circumstances gate capacitance is essentially the permittivity of the gate insulator layer divided by its thickness. In other words, the channel charge is so close to the surface that effects of the dielectric properties of the substrate are insignificant in determining gate capacitance.

Gate capacitance can be lowered if conduction carriers are confined within a channel region below the gate, where the average depth of the channel charge requires inclusion of the permittivity of the substrate to calculate gate capacitance. In general, the gate capacitance of the low capacitance Fermi-FET is described by the following equation:

Where Y_f is the depth of the conduction channel called the Fermi channel, ε_s is the permittivity of the substrate, and β is the factor that determines the average depth of the charge flowing within the Fermi channel below the surface, β depends on the depth dependant profile of carriers injected from the source into the channel. For the low capacitance Fermi-FET, β≡2. T_ox is the thickness of the gate oxide layer and ε_j is its permittivity.

The low capacitance Fermi-FET includes a Fermi-tub region of predetermined depth, having conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source regions. The Fermi- rub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub region within the Fermi-tub boundaries. The preferred Fermi-tub depth is the sum of the Fermi channel depth Y_f and depletion depth Y₀. A Fermi channel region with predetermined depth Y_f and width Z, extends between the source and drain diffusions. The conductivity of the Fermi channel is controlled by the voltage applied to the gate electrode.

The gate capacitance is primarily determined by the depth of the Fermi channel and the carrier distribution in the Fermi channel, and is relatively independent of the thickness of the gate oxide layer. The diffusion capacitance is inversely dependant on the difference between [the sum of the depth of the Fermi- tub and the depletion depth Y₀ in the substrate] and the depth of the diffusions X_d. The diffusion depth is preferably less than the depth of the Fermi-tub, Y_τ. The dopant concentration for the Fermi-tub region is preferably chosen to allow the depth of the Fermi channel to be greater than three times the depth of an inversion layer within a MOSFET.

Accordingly, the low capacitance Fermi-FET includes a semiconductor substrate of first conductivity type having a first surface, a Fermi- tub region of second conductivity type in the substrate at the first surface, spaced apart source and drain regions of the second conductivity type in the Fermi-tub region at the first surface, and a channel of the second conductivity type in the Fermi-tub region at the first surface between the spaced apart source and drain regions. The channel extends a first predetermined depth (Y_f) from the first surface and the tub extends a second predetermined depth (Y₀) from the channel. A gate insulating layer is provided on the substrate at the first surface between the spaced apart source and drain regions. Source, drain and gate electrodes are provided for electrically contacting the source and drain regions and the gate insulating layer respectively.

At least the first and second predetermined depths are selected to produce zero static electric field perpendicular to the first surface at the first depth, upon application of the threshold voltage of the field effect transistor to the gate electrode. The first and second predetermined depths are also selected to allow carriers of the second conductivity type to flow from the source to the drain in the channel, extending from the first predetermined depth toward the first surface upon application of the voltage to the gate electrode beyond the threshold voltage of the field effect transistor. The carriers flow from the source to the drain region beneath the first surface without creating an inversion layer in the Fermi-tub region. The first and second predetermined depths are also selected to produce a voltage at the substrate surface, adjacent the gate insulating layer, which is equal and opposite to the sum of the voltages between the substrate contact and the substrate and between the polysilicon gate electrode and the gate electrode. When the substrate is doped at a doping density N_s, has an intrinsic carrier concentration rij at temperature T degrees Kelvin and a permittivity ε_s, and the field effect transistor includes a substrate contact for electrically contacting the substrate, and the channel extends a first predetermined depth Y_f from the surface of the substrate and the Fermi-tub region extends a second predetermined depth Y₀ from the channel, and the Fermi-tub region is doped at a doping density which is a factor α times N_s, and the gate electrode includes a polysilicon layer of the first conductivity type and which is doped at a doping density N_p, the first predetermined depth (Y_f) is equal to:

where q is 1.6xl0^'19 coulombs and K is 1.38xl0^"23 Joules/°Kelvin. The second predetermined depth (Y₀) is equal to:

where φ_s is equal to 2φ_f+kT/q Ln(α), and φ_f is the Fermi potential of the semiconductor substrate.

High Current Fermi-FET Structure

Referring now to Figure 1 , an N-channel high current Fermi-FET according to U.S. Patent 5,374,836 is illustrated. It will be understood by those having skill in the art that a P-channel Fermi-FET may be obtained by reversing the conductivities of the N and P regions.

As illustrated in Figure 1 , high current Fermi-FET 20 is fabricated in a semiconductor substrate 21 having first conductivity type, here P-type, and including a substrate surface 21a. A Fermi-tub region 22 of second conductivity type, here N-type, is formed in the substrate 21 at the surface 21a. Spaced apart source and drain regions 23 and 24, respectively, of the second conductivity type, here N-type, are formed in the Fermi-tub region 22 at the surface 21a. It will be understood by those having skill in the art that the source and drain regions may also be formed in a trench in the surface 21a.

A gate insulating layer 26 is formed on the substrate 21 at the surface 21a between the spaced apart source and drain regions 23 and 24, respectively. As is well known to those having skill in the art, the gate insulating layer is typically silicon dioxide. However, silicon nitride and other insulators may be used.

A gate electrode is formed on gate insulating layer 26, opposite the substrate 21. The gate electrode preferably includes a polycrystalline silicon (polysilicon) gate electrode layer 28 of first conductivity type, here P-type. A conductor gate electrode layer, typically a metal gate electrode layer 29, is formed on polysilicon gate electrode 28 opposite gate insulating layer 26. Source electrode 31 and drain electrode 32, typically metal, are also formed on source region 23 and drain region 24, respectively. A substrate contact 33 of first conductivity type, here P-type, is also formed in substrate 21, either inside Fermi-tub 22 as shown or outside tub 22. As shown, substrate contact 33 is doped first conductivity type, here P-type, and may include a relatively heavily doped region 33a and a relatively lightly doped region 33b. A substrate electrode 34 establishes electrical contact to the substrate. The structure heretofore described with respect to Figure 1 corresponds to the low capacitance Fermi-FET structure of U.S. Patents 5,194,923 and 5,369,295. As already described in these applications, a channel 36 is created between the source and drain regions 23 and 24. The depth of the channel from the surface 21a, designated at Y_f in Figure 1 , and the depth from the bottom of the channel to the bottom of the Fermi-tub 22, designated as Y₀ in Figure 1, along with the doping levels of the substrate 21, tub region 22, and polysilicon gate electrode 28 are selected to provide a high performance, low capacitance field effect transistor using the relationships of Equations (2) and (3) above. Still referring to Figure 1 , a source injector region 37a of second conductivity type, here N-type, is provided adjacent the source region 23 and facing the drain region. The source injector region provides a high current, Fermi- FET by controlling the depth at which carriers are injected into channel 36. The source injector region 37a may only extend between the source region 23 and the drain region 24. The source injector region preferably surrounds source region 23 to form a source injector tub region 37, as illustrated in Figure 1. Source region 23 may be fully surrounded by the source injector tub region 37, on the side and bottom surface. Alternatively, source region 23 may be surrounded by the source injector tub region 37 on the side, but may protrude through the source injector tub region 37 at the bottom. Still alternatively, source injector region 37a may extend into substrate 21, to the junction between Fermi-tub 22 and substrate 21. A drain injector region 38a, preferably a drain injector tub region 38 surrounding drain region 24, is also preferably provided.

Source injector region 37a and drain injector region 38a or source injector tub region 37 and drain injector tub region 38, are preferably doped the second conductivity type, here N-type, at a doping level which is intermediate the relatively low doping level of Fermi-tub 22 and the relatively high doping level of source 23 and drain 24. Accordingly, as illustrated in Figure 1, Fermi-tub 22 is designated as being N, source and drain injector tub regions 37, 38 are designated as N⁺ and source and drain regions 23, 24 are designated as N⁺⁺. A unijunction transistor is thereby formed. The high current Fermi-FET provides drive currents that are about four times that of state of the art FETs. Gate capacitance is about half that of a conventional FET device. The doping concentration of the source injector tub region 37 controls the depth of carriers injected into the channel region 36, typically to about lOOOA. The source injector tub region 37 doping concentration is typically 2E18, and preferably has a depth at least as great as the desired maximum depth of injected majority carriers. Alternatively, it may extend as deep as the Fermi-tub region 22 to minimize subthreshold leakage current, as will be described below. It will be shown that the carrier concentration injected into the channel 36 cannot exceed the doping concentration of the source injector region 37a facing the drain. The width of the portion of source injector region 37a facing the drain is typically in the range of 0.05-0.15μm. The doping concentration of the source and drain regions 23 and 24 respectively, is typically 1E19 or greater. The depth Y_T=(Y_f+Y₀) of the Fermi-tub 22 is approximately 2200 A with a doping concentration of approximately 1.8E16. As illustrated in Figure 1 , the high current Fermi-FET 20 also includes a gate sidewall spacer 41 on the substrate surface 21a, which extends from adjacent the source injector region 37a to adjacent the polysilicon gate electrode 28. Gate sidewall spacer 41 also preferably extends from adjacent the drain injector region 38a to adjacent the polysilicon gate electrode 28. In particular, as shown in Figure 1 , gate sidewall spacer 41 extends from the polysilicon gate electrode sidewall 28a and overlies the source and drain injector regions 37a and 38a respectively. Preferably the gate sidewall spacer 41 surrounds the polysilicon gate electrode 28. Also preferably, and as will be discussed in detail below, the gate insulating layer 26 extends onto the source injector region 37a and the drain injector region 38a at the substrate face 21a and the gate sidewall spacer 41 also extends onto the source injector region 37 and drain injector region 38.

The gate sidewall spacer 41 lowers the pinch-off voltage of the Fermi-FET 20 and increases its saturation current in a manner in which will be described in detail below. Preferably, the gate sidewall spacer is an insulator having a permittivity which is greater than the permittivity of the gate insulating layer 26. Thus, for example, if the gate insulating layer 26 is silicon dioxide, the gate sidewall spacer is preferably silicon nitride. If the gate insulating layer 26 is silicon nitride, the gate sidewall spacer is preferably an insulator which has permittivity greater than silicon nitride.

As shown in Figure 1, the gate sidewall spacer 41 may also extend onto source and drain regions 23 and 24 respectively, and the source and drain electrodes 31 and 32 respectively may be formed in the extension of the gate sidewall spacer region. Conventional field oxide or other insulator 42 regions separate the source, drain and substrate contacts. It will also be understood by those having skill in the art that although the outer surface 41a of gate sidewall spacer 41 is illustrated as being curved in cross section, other shapes may be used, such as a linear outer surface to produce a triangular cross section or orthogonal outer surfaces to produce a rectangular cross section.

Low Leakage Current Fermi-Threshold Field Effect Transistor

Referring now to Figures 2 A and 2B, Fermi-FETs which have short channels yet produce low leakage current, according to U.S. Patent 5,374,836 will now be described. These devices will hereinafter be referred to as "low leakage current Fermi-FETs". The low leakage current Fermi-FET 50 of Figure 2 A includes a bottom leakage current control region 51 of first conductivity type, here P conductivity type, and doped at a high concentration relative to the substrate 21. Accordingly, it is designated as P⁺ in Figure 2A. The low leakage current Fermi- FET 60 of Figure 2B includes extended source and drain injector regions 37a, 38a, which preferably extend to the depth of the Fermi-tub 22.

Referring now to Figure 2A, bottom leakage current control region 51 extends across the substrate 21 from between an extension of the facing ends of the source and drain regions 23 and 24, and extends into the substrate from above the depth of the Fermi-tub 22 to below the depth of the Fermi-tub. Preferably, it is located below, and in alignment with the Fermi-channel 36. For consistency with the equations previously described, the depth from the Fermi-channel 36 to the top of the bottom current leakage current control region 51 has been labeled Y₀. The remainder of the Fermi-FET transistor of Figure 2 A is identical with that described in Figure 1 , except that a shorter channel is illustrated. It will be understood by those having skill in the art that injector regions 37a and 38a and/or injector tubs 37 and 38 may be omitted, as may the gate sidewall spacer region 41, to provide a low leakage current low capacitance, short channel Fermi-FET without the high current properties of the device of Figure 2 A.

The bottom leakage current control region 51 minimizes drain induced injection in short channel Fermi field effect transistors, i.e. those field effect transistors having a channel length of approximately 0.5 μm or less, while maintaining low diffusion depletion capacitance. For example, at 5 volts, leakage current of 3E-13A or less may be maintained.

The bottom leakage current control region may be designed using Equations (2) and (3) where Y₀ is the depth from the channel to the top of the bottom leakage control region as shown in Figures 2 A and 2B. Factor α is the ratio between the P⁺ doping of the bottom leakage current control region 51 and the N doping of the Fermi-rub 22. Preferably α is set to about 0.15 within the bottom leakage control region, i.e. below the gate 28. Below the source and drain regions 23 and 24, α is set to about 1.0 to minimize diffusion depletion capacitance. In other words, the doping concentrations of substrate 21 and Fermi-tub 22 are about equal in the regions below the source and drain. Accordingly, for the design parameters described above, and for a channel width of 0.5 micron, the doping concentration in the bottom leakage control region 51 is approximately 5E17 and is deep enough to support partial depletion at the tub-junction region given 5 volt drain or source diffusion potential.

Referring now to Figure 2B, an alternate design for bottom leakage control extends the depth of source injector region 37a and drain injector region 38a, preferably to the depth of the Fermi-tub (Y_f + Y₀). As shown in Figure 2B, the depth of the entire source injector tub 37 and drain injector tub 38 may be extended, preferably to the depth of the Fermi-tub. The separation distance between the bottom of the injector tubs 37 and 38 and the bottom of the Fermi-tub 22 is preferably less than half the channel length and preferably approaches zero. Under these conditions, injector tubs 37 and 38 have doping concentration of about 1.5E18/cm\ The depth of substrate contact region 33b also preferably is extended to approach the Fermi-tub depth. The remainder of the Fermi-FET transistor 60 of Figure 2B is identical with that described in Figure 1 , except that a shorter channel is illustrated.

Contoured-Tub Fermi-Threshold Field Effect Transistor

Referring now to Figure 3, an N-channel contoured-tub Fermi-FET according to U.S. Patent 5,543,654 is illustrated. It will be understood by those having skill in the art that a P-channel Fermi-FET may be obtained by reversing the conductivities of the N and P regions. As illustrated in Figure 3, contoured-tub Fermi-FET 20' is similar to high current Fermi-FET 20 of Figure 1, except that a contoured-tub 22' is present rather than the tub 22 of Figure 1 which has a uniform tub depth. Injector tubs and injector regions are not shown, although they may be present.

Still referring to Figure 3, contoured-tub 22' has a first predetermined depth Y, from the substrate face 21a to below at least one of the spaced-apart source and drain regions 23, 24 respectively. The contoured-tub 22' has a second predetermined depth Y₂ from the substrate face 21a to below the channel region 36. According to the invention, Y₂ is different from, and preferably less than, Y, so as to create a contoured-tub 22'. Stated another way, the junction between tub 22' and substrate 21 is pushed downward, away from source and drain regions 23 and 24, relative to the position dictated by the tub-FET criteria under the channel, to reduce the source/drain diffusion capacitance and thereby allow the contoured-tub Fermi-FET to operate at low voltages. It will be understood by those having skill in the art that tub 22' may only be contoured under source region

23 or drain region 24 to produce an asymmetric device. However, symmetric devices in which the tub is contoured under source 23 and drain 24 are preferably formed.

The second predetermined depth Y₂ is selected based on the low capacitance Fermi-FET (Tub-FET) criteria of U.S. Patents 5,194,923 and 5,369,295. These criteria, which determine the depths Y_f and Y₀, and which together form the second predetermined depth Y₂, are described above.

The first predetermined depth (Y,) is selected to be greater than the second predetermined depth Y₂. Preferably, the first predetermined depth is also selected to deplete the tub region 22' between the first predetermined depth Y, and the source and/or drain regions when zero voltage is applied to the source contact 31 and drain contact 32 respectively. Thus, the entire region labelled Y_n is preferably totally depleted under zero source bias or drain bias respectively. Based on this criteria, Y, is determined by:

where Ν_sub is the doping concentration of the substrate 21 and N_tab is the doping concentration of the contoured-tub 22'.

Short Channel Fermi-FETs

Referring now to Figure 4, a short channel N-channel Fermi-FET 20" according to Application Serial No. 08/505,085 is illustrated. It will be understood by those having skill in the art that a P-channel short channel Fermi- FET may be obtained by reversing the conductivities of the N and P regions. As shown in Figure 4, Fermi-tub 22" extends a first depth (Y_f+Y₀) from the substrate surface 21a. The spaced-apart source and drain regions 23 and 24 respectively are located in the tub region, as shown by regions 23a and 24a. However, the source and drain regions 23 and 24 respectively also extend from the substrate surface 21a to beyond the tub depth. Source and drain regions 23 and 24 also extend laterally in a direction along substrate surface 21a, to beyond the tub region.

The channel depth Y_f and the tub depth from the channel Y₀ are selected to minimize the static electric field perpendicular to the substrate surface in the channel 36 from the substrate surface to the depth Y_f when the gate electrode is at threshold potential. As already described, these depths are also preferably selected to produce a threshold voltage for the field effect transistor which is twice the Fermi potential of the semiconductor substrate 21. These depths are also selected to allow carriers of the second conductivity type to flow from the source region to the drain region in the channel region, extending from the depth Y_f toward the substrate surface 21a upon application of voltage to the gate electrode beyond the threshold voltage of the field effect transistor. Carriers flow within the channel region from the source region to the drain region underneath the substrate surface without creating an inversion layer in the channel. Accordingly, while not optimum, the device of Figure 4 can still produce saturation currents far higher than traditional MOSFET transistors, with significant reductions in off-state gate capacitance. Drain capacitance becomes similar to standard MOSFET devices.

It will be understood that in Figure 4, the source and drain regions extend beyond the tub region in the depth direction orthogonal to substrate face 21a, and also in the lateral direction parallel to substrate face 21a. However, in order to decrease the parasitic sidewall capacitance, the tub 22" preferably extends laterally beyond the source and drain regions, so that the source and drain regions only project through the tub in the depth direction.

Referring now to Figure 5, a second embodiment of a short channel Fermi-FET according to Application Serial No. 08/505,085 the present invention is illustrated. Transistor 20'" is similar to transistor 20" of Figure 4 except that source and drain extension regions 23b and 24b respectively are provided in the substrate 21 at the substrate face 21a adjacent the source region and drain regions 23' and 24' respectively, extending into channel 36. As shown in Figure 5, source and drain extension regions 23b and

24b respectively are heavily doped (NT⁴), at approximately the same doping concentration as source and drain regions 23' and 24'. It will be understood that the extensions 23b and 24b are not lightly doped as are lightly doped drain structures of conventional MOSFET devices. Rather, they are doped at the same doping concentration as the source and drain region, and are preferably as highly doped as practical in order to reduce leakage and improve saturation current.

The source and drain extension regions 23b and 24b reduce drain voltage sensitivity due to the charge sharing described above. Unfortunately, the device of Figure 5 will generally not display as low a capacitance as the fully enclosed source and drain regions of Figures 1 and 2. It will be understood by those having skill in the art that in order to preserve the dimensions of the source/drain extension regions 23b and 24b, a heavy, slow moving dopant such as arsenic or indium is preferably used for the source and drain extension regions rather than a lighter, faster moving element which is typically used for the source and drain regions themselves.

Short Channel Fermi-FET Including Drain Field Termination

The architecture of short channel Fermi-threshold field effect transistors including drain field termination regions, also referred to herein as Vinal-FETs, according to Application Serial No. 08/597,711, will now be described. It will be understood by those having skill in the art that P-channel Vinal-FETs may be obtained by reversing the conductivity of the N- and P-regions. Figures 6 and 7 illustrate first and second embodiments of a Vinal- FET respectively. As shown in Figure 6, Vinal-FET 60 includes a semiconductor substrate 21 of first conductivity type, here P-type. It will be understood by those having skill in the art that semiconductor substrate 21 may also include one or more epitaxial layers formed on a bulk semiconductor material so that the substrate surface 21a may actually be the outer surface of an epitaxial layer rather than the outer surface of bulk semiconductor material.

Still referring to Figure 6, a first tub region 62 of second conductivity type (here N-type) is formed on the substrate 21 at surface 21a and extending into the substrate a first depth Y₃ from the substrate surface 21a. A second tub region 64 of the first conductivity type, here P-type, is included in the first tub region 62. Second tub region 64 extends into the substrate a second depth Y₂ from substrate surface 21a, with the second depth Y₂ being less than a first depth Y₃. The second tub region 64 in the first tub region 62 may also extend laterally beyond first tub region 62. Second tub region 64 forms a Drain Field

Terminating (DFT) region as will be described below. A third tub region 66 of the second conductivity type, here N-type, is included in the second tub region 64. The third tub 66 extends into the substrate 21 a third depth Y, from the substrate surface wherein the third depth Y, is less than the second depth. Third tub 66 is preferably formed in an epitaxial layer as will be described below.

Still referring to Figure 6, spaced apart source and drain regions 23 and 24 respectively, of the second conductivity type (here N+), are formed in the first tub region 62 and extend into the substrate a fourth depth Y₄ from the substrate surface 21a. As shown in Figure 6, the fourth depth Y₄ is greater than the third depth Y,. As shown in Figure 6, fourth depth Y₄ is also greater than the second depth Y₂, but is less than the first depth Y₃. Accordingly, the source and drain diffusions 23 and 24 respectively, extend through the third and second tubs 66 and 64 respectively, and into the first tub 62. In a second embodiment of a Vinal-FET 60' as shown in Figure 7, the fourth depth Y₄ is greater than the third depth Y_] but is less than the second depth Y₂, so that the source and drain regions extend through the third tub 66 and into the second tub 64, but do not extend into the first tub 62.

Vinal-FET transistors 60 and 60' of Figures 6 and 7 respectively, also include a gate insulating layer 26 and a gate electrode including polycrystalline silicon layer 28 of the first conductivity type, here P-type. Source, gate and drain contacts 31, 29 and 32 are also included as already described. A substrate contact 34 is also included. The substrate contact is shown opposite surface 21a but it may also be formed adjacent surface 21a as in previous embodiments.

The Vinal-FETs 60 and 60' of Figures 6 and 7 may also be described from the perspective of the layers in the substrate 21 which extend between the source and drain regions 24. When viewed in this regard, third tub 66 produces a first layer 66a of a second conductivity type in the substrate at the substrate surface which extends from the source region 23 to the drain region 24 and also extends into the substrate a first depth Y, from the substrate surface. Second tub 64 produces a second layer 64a of the first conductivity type in the substrate which extends from the source region 23 to the drain region 24 and extends into the substrate from the first depth Y, to a second depth Y₂ from the substrate surface. Second layer 64a acts as Drain Field Terminating means as described below. First tub 62 produces a third layer 62a of the second conductivity type in the substrate which extends from the source region to the drain region and extends into the substrate from the second depth Y₂ to a third depth Y₃ from the substrate surface. When viewed in this manner, in the embodiment of Figure 6, the third layer 62a also extends from the source bottom 23a to the drain bottom 24a as indicated by regions 62b. In the embodiment of Figure 7, the second and third layers 64a and 62a respectively, both extend from the source bottom 23a to the drain bottom 24a as shown at regions 64b and 62b respectively. The Vinal-FET of Figures 6 and 7 may also be regarded as a Tub-

FET which includes a contra-doped buried tub 64 within the original tub. Still alternatively, the Vinal-FET may be viewed as a Tub-FET which includes a buried layer of first conductivity type 64a beneath the channel region 66a. As will be described in detail below, second tub 64 including second layer 64a acts as Drain Field Terminating (DFT) means to shield the source region by preventing the applied drain bias from causing carriers to be injected from the source region into or below the channel region. Accordingly, second tub 64 and second layer 64a may also be referred to as a Drain Field Termination (DFT) region.

Operation of the Vinal-FET transistors 60 and 60' of Figures 6 and 7 are described in detail in application Serial No. 08/597,711 and will not be described again herein.

Low Voltage Operation of Fermi-FETs

Before describing metal gate Fermi-FETs of the present invention, general considerations for low voltage operation will be described.

Equation 5 reflects the maximum available saturation current from a field effect transistor. When the operating voltage V_d becomes small for low power applications or small transistor geometry, the quantity V_d-V, approaches zero, and may limit the current that can be produced.

V ' _dd_ss = V_d (5)

In short channel Fermi-FET devices, the threshold voltage may be higher than a MOSFET of comparable size. This may be intentional in order to overcome the two dimensional effects that may be more pronounced in a Fermi- FET than in a surface channel or traditional buried channel MOSFET device. As long as V_d is large compared to the threshold voltage V, (for example V_{d ≥} 3 V_t), the increased lateral carrier velocity in the channel of the Fermi-FET can produce a higher saturation current.

Equation 6 represents the terms behind the threshold voltage of the Fermi-FET transistor. The threshold voltage (neglecting the ΔV_t term which is the result of short channel effects) generally includes four distinct voltage components:

_{Vι =} V_{l +} V₂ + V₃ + V_A - AV,

The four components of Equation 6 are shown graphically in Figure 8. Figure 8 illustrates a short channel Fermi-FET similar to Figure 4. For ease of explanation, the tub depth Y_f+Y₀ is set to be the same as the source/drain depth X_j. Referring now to Figure 8, V, results from the difference in contact potential between the wiring and the P-type polysilicon gate and the wiring and the P-well region under the Fermi-tub structure. V₂ quantifies the voltage induced across the depletion region below the Fermi-tub:P-well junction. V₃ represents the voltage across the Fermi-tub itself. In long channel devices this includes the depletion region above the Fermi-tub:P-well junction and depletion between the junction induced region and the silicon surface due to the gate field. Finally, V₄ quantifies the voltage developed across the gate oxide due to the field from the polysilicon gate terminating on charge in the region defined by V₃.

The integration density of integrated circuit field effect transistors continues to increase. This trend may be expected to continue into the foreseeable future. As feature sizes reach well below one micron, it is generally desirable to also reduce the operating voltage of the transistors to maintain control in smaller channel lengths. A commensurate reduction in the transistor threshold voltage is also generally desirable.

One technique to reduce the Fermi-FET threshold voltage would be to lower the polysilicon gate doping density N_poly. This would lower the value of the V_! term without changing any of the substrate terms. Unfortunately, the net polysilicon doping level should generally be kept above 10²⁰cm^"3 levels to avoid Schottky barrier contacts and to minimize the poly depletion when the transistor turns off. Excessive poly depletion may lead to elevated leakage levels in short channel Fermi-FET devices. Solving V, at N^l.OxlO²⁰ and N_well at 3.0xl0¹⁶ leads to a voltage of about +0.210 volts. This may be a minimum value for V, when using polysilicon. Unfortunately, this may produce an insufficient reduction in the threshold voltage.

When short channel devices are operated at low drain voltages, the threshold voltage also should be reduced to produce significant saturation currents. Figure 9 shows I_dV_g curves as simulated by commercial two-dimensional process and device simulation programs.

The simulated transistors that produced the curves in Figure 9 illustrate an attempt to reduce the threshold voltage by increasing Y₀, the depth of the Fermi-tub structure. All of the transistors have a 4nm gate oxide and a drawn gate length of 0.25 μm. The electrical simulation utilized a drain voltage of 1.8 volts. For this purpose, V, is defined as the gate voltage at which the drain current reaches 5.0xl0^"7 A/μm. This value is shown as circles on each individual I_dV_g curve. The initial device (rightmost curve of Figure 9), with a threshold voltage of 0.95 volts has excellent short channel characteristics. Unfortunately, such a high V, produces a drive current of 225 μA per micron of transistor width. This may be no better than traditional MOSFET devices. The low current is primarily due to the V_d-N, term in Equation 5.

Reduction in threshold can also be accomplished by increasing the Fermi-tub depth. As shown in Figure 9, as the tub depth is increased, the subthreshold swing remains the same as the initial curve for the first two steps. However, once the V, has been lowered to approximately 0.80 volt, the subthreshold swing begins to drop with each successive step. This causes a rapid increase in leakage current with decreasing threshold. The shift in the subthreshold swing appears to occur because the deeper tub structure becomes increasingly sensitive to two-dimensional effects due to the proximity of the drain to the source relative to the depth of the tub structure.

Assuming a leakage requirement of less than l.OxlO'¹² A/μm, the minimum threshold with this technique is approximately 0.75 volts. The drive current produced at this leakage level was 315 μ A/μm, a 40% improvement, but more overdrive can dramatically increase the performance. Unfortunately, this threshold voltage may not be sufficiently low.

Another technique to reduce threshold is to increase the Fermi-tub doping density without increasing Y₀. The result of this technique is shown in Figure 10. As expected, increasing the Fermi-tub doping density can delay the onset of the 2D effects since the thinner tub provides some measure of protection Drain Induced Injection (DII). There is still a pronounced reduction in subthreshold swing as V, is reduced however, and the minimum threshold given I_dss less than l.OxlO^"12 A/μm is approximately 0.65 volts. A moderate increase in drive current may be obtained with another lOOmV reduction in threshold. The simulated current produced using this technique was 299 μA/μm, slightly lower than obtained by increasing the tub depth even though the threshold is 100 mV lower. This appears to be due to the reduction in free carrier mobility that accompanies the higher doping in the channel.

Accordingly, these techniques for reducing threshold voltage may occur at the expense of an increase in leakage current, a decrease in drive current and/or other effects such as production of undesired Schottky contacts. These tradeoffs may not be acceptable in producing a low voltage Fermi-FET transistor. Metal Gate Fermi-FET Transistors

According to the invention, the threshold voltage of Fermi-FET transistors may be decreased without unduly increasing leakage current and/or unduly reducing saturation current, by using a metal gate in a Fermi-FET rather than a contra-doped polygate.

Figure 11 illustrates an embodiment of a metal gate Fermi-FET. This embodiment is patterned after the N-channel, short-channel Fermi-FET of U.S. Patent 5,543,654 that is illustrated in Figure 4 of the present application. However, it will be recognized by those having skill in the art that metal gate Fermi-FET technology can be applied to all Fermi-FETs to lower the threshold voltage thereof.

As shown in Figure 11, metal gate Fermi-FET 110 includes a metal gate 28' rather than the P-type polysilicon gate 28 and metal gate electrode layer 29 of Figure 4. For ease of illustration, all other elements of transistor 110 are unchanged from that of Figure 4. Accordingly, as shown in Figure 11, a metal gate 28' is included directly on the gate insulating layer 26. Stated differently, the metal gate 28' of the Fermi-FET 110 is free of doped polysilicon directly on the gate insulating layer 26. Thus, the contact potential is not controlled by the Fermi- potential of polysilicon. It will be understood that the metal gate may include multiple layers, wherein the layer that is directly on the gate insulating layer is free of doped polysilicon.

The ability of a metal gate 28' to lower the Fermi-FET threshold voltage without unduly incurring other penalties, will now be described. As was described above, V, has a lower bound due to minimum polysilicon doping levels that should be used to avoid the formation of Schottky barriers. However, other materials may be used with different properties to remove this constraint from the V, term.

Specifically, metals, suicides, or other metal alloys with work functions near the center of the silicon band gap can significantly reduce the Fermi- FET threshold without unduly increasing detrimental two-dimensional effects.

If a metal, silicide or other non-semiconductor is utilized as a gate material, Equation (6) for V, is modified to reflect the work function difference rather than the contact potential of the gate material:

where φ_gate is the work function of the material being used for the gate and φ_si is the mid-gap (intrinsic) level for silicon or 4.85V.

Figure 12 shows the work function of some of the materials that may be utilized as Fermi-FET gate structures. Materials with a work function near 4.85V are particularly preferred in Fermi-FET structures because they can result in symmetrical N-Channel and P-Channel dopings. Other materials may be used to give a lower relative threshold to either the N- or P-channel devices depending upon a desired performance. Preferably, metals or metal alloys having work function between that of P-type silicon and N-type silicon are used, as indicated by the dashed lines in Figure 12.

Figure 13 simulates the same high threshold N-Channel transistor that was simulated in Figures 9 and 10, utilizing different gate materials and shows how the threshold voltage moves due to the change in V,. Figure 13 depicts the initial 0.95 volt device with various gate materials. All of the substrate profiles and junctions were unchanged. As shown, the various I_dV_g curves are offset by only the voltage component in V,. All of the curves have identical subthreshold swing values.

Proper selection of the gate material thus can produce low threshold Fermi-FET transistors with high threshold off-state performance parameters. The metal gate Fermi-FET is uniquely situated to take advantage of alteration of gate work function. In particular, due to the reversal of the vertical electric field at V_τ,.a Fermi-FET can optimize both the N-Channel and the P-Channel devices with a single gate material, provided the work function is near the mid-range between N- and P-type polysilicon.

Materials that have been used in MOSFET technology with work function near 4.85V include, but are not limited to Tungsten, Tungsten Suicide, Nickel, Cobalt and Cobalt Suicide. A simulation of the same N-Channel transistor of Figures 9 and 10 utilizing Tungsten as the gate material produces an increase saturation current from 225 μA/μm to 423 μA/μm without changing DIBL or subthreshold swing. Figure 14 shows the I_dV_g curves on a log scale, using P-type polysilicon optimized for Fermi-tub depth and Fermi-tub doping as described above along with the Tungsten gate simulation. As shown, the threshold voltage can be lowered dramatically, and better subthreshold swing may be obtained for the metal gate structure. Figure 15 shows the same relationships on a linear scale.

In order to illustrate an impact of lowered threshold voltages via gate work function engineering according to the invention, the large-signal transient response of several inverter structures was simulated. A comparison of conventional CMOS, polysilicon gate Fermi-FET and metal-gate Fermi-FET structures was performed. A schematic representing all three simulations is shown in Figure 16. A fixed load capacitance of 0.05 fF was used to emulate the effective maximum gate capacitance of a single inverter, i.e. a fan-out of 1. The devices used for these simulations were all 0.4μm in channel length with gate oxide thickness of 6θA. The supply voltage was 2.5 volts, used for comparison purposes since the MOSFET devices were designed for this value. The MOSFET simulated DC device characteristics correlated well with measurement.

The inverters were simulated in a mixed-mode hybrid simulator that allows circuit elements to be modeled either by conventional, industry-standard compact analytical models, or by a full two-dimensional numerical solution based upon the physical device structure. Thus, critical devices, or devices with no compact analytical model yet developed, may be simulated numerically alongside conventional devices and circuit elements in a familiar circuit simulation environment. As in conventional circuit analysis programs, standard circuit analyses including DC, AC and/or large-signal transient simulations may be performed with the hybrid simulator.

For these simulations, only the large-signal transient simulations were performed, because the individual device DC characteristics were already well-known from the device simulations. For each inverter, the supply voltage was ramped up to V_d with a delay sufficient to allow the circuit nodes to settle to their initial DC state with the input low. The input was then pulsed high, then low, again with a delay time long enough to allow all nodes to reach steady state.

The resulting output responses are shown together in Figure 17. The different delay characteristics may be seen. It can be seen that a conventional Fermi-FET inverter displays significantly improved rise and fall times compared to the MOSFET, with metal-gate Fermi-FETs providing an even further improvement.

The use of a mid-gap work function material for the gate electrode allows the device channel implants to be designed so that the threshold may be lowered to a reasonable value. As a result, more overdrive (V_gs-V_t) may be provided by the device to drive the fixed capacitive load. The improvement difference between the conventional Fermi-FET and metal-gate Fermi-FETs may also increase substantially for supply voltages approaching or below 1.5 volts. Accordingly, improved low voltage operation may be provided for Fermi-FET transistors. In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

THAT WHICH IS CLAIMED:

1. A Fermi-threshold field effect transistor (Fermi-FET) comprising: spaced apart source and drain regions in an integrated circuit substrate; a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions; a gate insulating layer on the integrated circuit substrate, between the spaced apart source and drain regions; and a metal gate directly on the gate insulating layer.

2. A Fermi-FET according to Claim 1 further comprising: a Fermi-FET tub in the integrated circuit substrate, beneath the Fermi-FET channel.

3. A Fermi-FET according to Claim 1 wherein the metal gate comprises a metal alloy gate.

4. A Fermi-FET according to Claim 3 wherein the metal alloy gate comprises a metal suicide gate.

5. A Fermi-FET according to Claim 1 wherein the metal gate comprises metal having a work function between that of P-type polysilicon and N- type polysilicon.

6. A Fermi-FET according to Claim 5 wherein the metal gate comprises metal having a work function of about 4.85V.

7. A Fermi-FET according to Claim 1 having a threshold voltage of less than about 0.5V.

8. A Fermi-threshold field effect transistor (Fermi-FET) comprising: spaced apart source and drain regions in an integrated circuit substrate; a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions; a gate insulating layer on the integrated circuit substrate, between the spaced apart source and drain regions; and a doped-polysilicon-free gate layer directly on the gate insulating layer.

9. A Fermi-FET according to Claim 8 further comprising: a Fermi-FET tub in the integrated circuit substrate, beneath the Fermi-FET channel.

10. A Fermi-FET according to Claim 8 wherein the doped polysilicon-free gate layer comprises a metal gate layer.

11. A Fermi-FET according to Claim 10 wherein the metal gate layer comprises a metal alloy gate layer.

12. A Fermi-FET according to Claim 11 wherein the metal alloy gate layer comprises a metal suicide gate layer.

13. A Fermi-FET according to Claim 8 wherein the doped polysilicon- free gate layer comprises material having a work function between that of P-type polysilicon and N-type polysilicon.

14. A Fermi-FET according to Claim 13 wherein the material comprises material having a work function of about 4.85V.

15. A Fermi-FET according to Claim 8 having a threshold voltage of less than about 0.5V.

16. A Fermi-threshold field effect transistor (Fermi-FET) comprising: spaced apart source and drain regions in an integrated circuit substrate; a Fermi-FET channel in the integrated circuit substrate, between the spaced apart source and drain regions; a gate insulating layer on the integrated circuit substrate, between the spaced apart source and drain regions; and a gate on the gate insulating layer having a work function between that of P-type polysilicon and N-type polysilicon.

17. A Fermi-FET according to Claim 16 further comprising: a Fermi-FET tub in the integrated circuit substrate, beneath the Fermi-FET channel.

18. A Fermi-FET according to Claim 16 wherein the gate comprises a metal gate.

19. A Fermi-FET according to Claim 18 wherein the metal gate comprises a metal alloy gate.

20. A Fermi-FET according to Claim 19 wherein the metal alloy gate comprises a metal suicide gate.

21. A Fermi-FET according to Claim 16 wherein the gate comprises material having a work function of about 4.85V.

22. A Fermi-FET according to Claim 16 having a threshold voltage of less than about 0.5V.

23. A metal gate Fermi-threshold field effect transistor (Fermi-FET).