WO1999039288A3 - Method and system for creating optimized physical implementations from high-level descriptions of electronic design - Google Patents

Method and system for creating optimized physical implementations from high-level descriptions of electronic design Download PDF

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Publication number
WO1999039288A3
WO1999039288A3 PCT/US1999/001965 US9901965W WO9939288A3 WO 1999039288 A3 WO1999039288 A3 WO 1999039288A3 US 9901965 W US9901965 W US 9901965W WO 9939288 A3 WO9939288 A3 WO 9939288A3
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WO
WIPO (PCT)
Prior art keywords
design
partitions
chip
implementations
electronic
Prior art date
Application number
PCT/US1999/001965
Other languages
French (fr)
Other versions
WO1999039288A2 (en
Inventor
Tommy K Eng
Original Assignee
Tera Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=21772380&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1999039288(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Tera Systems Inc filed Critical Tera Systems Inc
Priority to JP53957299A priority Critical patent/JP2001519958A/en
Priority to IL13208299A priority patent/IL132082A/en
Priority to EP99903493A priority patent/EP0979471A2/en
Priority to AU23500/99A priority patent/AU2350099A/en
Publication of WO1999039288A2 publication Critical patent/WO1999039288A2/en
Publication of WO1999039288A3 publication Critical patent/WO1999039288A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3947—Routing global
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Abstract

An electronic design automation system provides optimization of RTL models of electronic designs, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes an RTL model of an electronic design and maps it into an efficient, high level hierarchical representation of the hardware implementation of the design. Automatic partitioning partitions the hardware representation into functional partitions, and creates a fully characterized performance envelope for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations. In this fashion, a multiple-pass process converges on an optimal selection of physical implementations for all partitions for the entire chip that meet minimum timing requirements and other design goals. The system outputs specific control and data files which thoroughly define the implementation details of the design through the entire back-end flow process, thereby guaranteeing that the fabricated design meets all design goals without costly and time consuming design iterations.
PCT/US1999/001965 1998-01-30 1999-01-29 Method and system for creating optimized physical implementations from high-level descriptions of electronic design WO1999039288A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP53957299A JP2001519958A (en) 1998-01-30 1999-01-29 Method and system for generating optimal physical embodiments from high-level descriptions of electronic designs
IL13208299A IL132082A (en) 1998-01-30 1999-01-29 Method and system for creating optimized physical implementation from high-level descriptions of electronic design
EP99903493A EP0979471A2 (en) 1998-01-30 1999-01-29 Method and system for creating optimized physical implementations from high-level descriptions of electronic design
AU23500/99A AU2350099A (en) 1998-01-30 1999-01-29 Method and system for creating optimized physical implementations from high-level descriptions of electronic design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/015,602 1998-01-30
US09/015,602 US6145117A (en) 1998-01-30 1998-01-30 Creating optimized physical implementations from high-level descriptions of electronic design using placement based information

Publications (2)

Publication Number Publication Date
WO1999039288A2 WO1999039288A2 (en) 1999-08-05
WO1999039288A3 true WO1999039288A3 (en) 1999-09-30

Family

ID=21772380

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/001965 WO1999039288A2 (en) 1998-01-30 1999-01-29 Method and system for creating optimized physical implementations from high-level descriptions of electronic design

Country Status (6)

Country Link
US (4) US6145117A (en)
EP (1) EP0979471A2 (en)
JP (1) JP2001519958A (en)
AU (1) AU2350099A (en)
IL (1) IL132082A (en)
WO (1) WO1999039288A2 (en)

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