WO1999067703A1

WO1999067703A1 - Automatic resumption of computer operation following power failure

Info

Publication number: WO1999067703A1
Application number: PCT/IL1999/000340
Authority: WO
Inventors: Dov Yelin
Original assignee: Ephrath, Ezra
Priority date: 1998-06-22
Filing date: 1999-06-21
Publication date: 1999-12-29
Also published as: IL125056A0; AU4388699A

Abstract

A power management apparatus for a personal computer comprises a line fault detector (36), which detects loss of AC mains power (1), and a backup power source (6), preferably a battery (6), which provides electricity to the computer's memory (14) when the power loss is detected. The apparatus also includes a programmable switch (9), which distributes the electricity from the backup power source (6) only to those components within the computer that are necessary to maintain the memory (14) intact, while cutting off power from non-essential components.

Description

AUTOMATIC RESUMPTION OF COMPUTER OPERATION FOLLOWING POWER ' FAILURE

F1E1-D OP THE INVENTION

The present invention relates generally to computer memory protection, and specifically to methods and devices to preserve data in computer memory in the event of power loss.

BACKGROUND OF THE INVENTION Personal computers use semiconductor memory to provide the short-term storage required for operation of the computer and to perform many of the computer's functions. Such memory requires a substantially continuous source of electrical power from the computer's power supply. When the electricity is interrupted, even briefly, the computer transiently ceases to function and all unsaved work is lost. It is known in the art to connect to the computer a battery- powered uninterruptible power supply (UPS) , which can detect a loss of lines power and provide a short-term buffer during which the operations of the computer can be sustained or shut down in an organized fashion before the batteries within the UPS discharge. Such devices usually employ large batteries, are expensive, and do not allow the computer to automatically resume operation upon mains power restoration after having been turned off.

U.S. Patent 5,276,890 to Arai, whose disclosure is incorporated herein by reference, describes a method and system which provides a resume control function, whereby the contents of different parts of a computer memory can be temporarily saved into an external device before the computer is shut down or operation is suspended. U.S. Patent 5,276,690 is directed essentially for use in battery- powered computers, and does not relate specifically to the problem of AC mains power interruption in a desktop-type computer.

PCT Patent Publication WO 81/02362 to Parkinson, whose disclosure is incorporated herein by reference, describes apparatus for providing backup power to a semiconductor memory circuit in order to preserve the bit pattern stored therein upon failure of the memory circuit primary power. There is no suggestion as to how other power consuming components of the computer should be handled.

SUMMARY OF THE INVENTION It is an object of some aspects of the present invention to provide an improved system and method for preserving the contents of a computer memory in the event of power loss.

It is a further object of some aspects of the present invention to enable the computer to resume operation automatically following restoration of power.

In preferred embodiments of the present invention, power management apparatus for a personal computer comprises a line fault detector, which detects loss of AC mains power, and a backup power source, preferably a battery, which provides electricity to the computer' s memory chips when the power loss is detected. The apparatus also includes a programmable switch, which distributes the electricity from the backup source only to those components within the computer that are necessary to maintain the memory intact, while cutting off power from non-essential components. hen the power loss is detected, a software routine is invoked to automatically save the computer' s state and memory and to put the computer into a sleep mode. A flag is set so that when power is restored, the computer automatically resumes operation in the same state as prior to the power loss .

The present invention is based on the fact that the current operating state of a personal computer can be completely described by the contents of its main memory, the content of its display memory, and the state of various devices such as the central processor (CPU) and peripheral devices, assuming external operations such as communications and access to permanent memories (disk drives) have ceased- Only a small portion of the main memory is required to store the contents of its display memory or the state of various devices such as the central processor and peripheral devices. When this information is stored in the computer's dynamic memory (DRAM) chips or modules, the state of the computer can be preserved, as long as the DRAM is provided with continuous refresh pulses for memory retention. The refresh operation does not require large amounts of energy and consequently the memory contents can be retained using a small battery and suitable refresh circuitry. The remaining components, including any and all extension boards, can be switched off until lines power resumes.

In preferred embodiments of the present invention, the computer memory and computer state are automatically saved in the computer's main DRAM during power failure and restored to full operation upon resumption of power without the use of permanent storage devices. The apparatus of the present invention resides entirely inside the computer and requires only a small battery plus modifications to the main computer motherboard, power supply and operating software.

In some preferred embodiments of the present invention, the following modifications to the main computer motherboard, power supply and operating system software are performed in order to provide a functional automatic save and resume mode of operation: provision of a signal from the main power supply indicating the state (on or off) of the AC mains power; a battery, preferably a rechargeable type, accompanied by suitable battery charging and power conversion circuits, as are known in the art, to provide short-term operation of the main computer motherboard, and longer retention of the main memory during the absence of AC power;

semiconductor switches to control power distribution to various elements of the main motherboard in order to limit power consumption during the power down period; refresh control circuits to retain the main memory contents while power is absent; and software modi ications and drivers to permit the automatic monitoring and saving of the CPU state on power failure, and to permit the restoration of computer operation upon resumption of AC mains power.

In some preferred embodiments of the present invention, an interrupt is generated upon sensing the absence of AC mains power, this interrupt causing the CPU to: save the current state of the CPU; terminate all external input/output such as LAN, modem communications, and access to disk files; save the state of the various peripheral devices on the motherboard such as video mode, peripheral device settings, etc. ; save the video memory contents to the main memory; and halt the CPU and shut off power to the main motherboard elements except those required for retention of the saved information - Refresh circuits and Main Memory.

Preferably, upon sensing restoration of AC mains power, the CPU starts the following operations immediately after reset :

Check that the added battery has not been exhausted and continue as described below; otherwise proceed with a full system reset; restore the original state of the various peripheral devices on the motherboard; restore the video memory contents from that saved previously, in the main memory; restore the state of the CPU; reinitialize drivers and input/output devices which were turned off during power down period; and resume normal operation of the CPU.

There is therefore provided, in accordance with a preferred embodiment of the present invention, apparatus for preserving the state of a personal computer during a power loss, including: a power line sensor, which detects the power loss and generates a signal indicative thereof; a battery, which provides electrical power to selected components of the computer during the power loss; a computer memory, which receives power from the battery and stores data representative of the state of the computer responsive to the signal from the sensor; and switching circuitry, which selects the components needed to preserve the state of the computer to receive power from the battery and cuts off power to other components in order to conserve energy in the battery.

Preferably, the apparatus includes refresh circuitry, which receives power from the battery and provides signals to the memory to preserve the data stored therein.

Preferably, the data stored by the memory include a representation of a current state of a central processing unit (CPU) of the computer and, additionally or alternatively, a representation of a current state of a peripheral device associated with the computer and a

representation of current contents of a display memory associated with the computer.

Preferably, the switching circuitry includes a battery status indicator, which indicates to the computer during a power-up sequence the battery provided power to the selected components substantially throughout the power loss, wherein an indication from the battery status indicator that the battery provided power substantially throughout the power loss causes the computer to be restored to its state prior to the power loss. Preferably, the computer is restored to its state by reading out the data stored in the memory. Further preferably, an indication from the battery status indicator that the battery did not provide power substantially throughout the power loss causes the computer to reboot.

In a preferred embodiment, the apparatus includes a programmable logic-controlled power switch, which is operated by a user of the computer to cause the data representative of the state of the computer responsive to the signal from the sensor to be stored in the memory and to actuate the switching circuitry.

There is further provided, in accordance with a preferred embodiment of the present invention, a method for preserving the state of a personal computer during a power cut-off, including: sensing the power cut-off and generating a signal indicative thereof; storing data indicative of the state of the computer in a memory of the computer responsive to the signal; providing power to the memory so that the memory retains the stored data; and switching off power, responsive to the signal, from components other than the memory in order to reduce power consumption by the computer.

Preferably, storing the data in the memory includes storing a representation of a current state of a central processing unit (CPU) of the computer and, additionally or alternatively, storing a representation of a current state of a peripheral device associated with the computer and storing a representation of current contents of a display memory associated with the computer.

Preferably, the method includes sensing a resumption of power following the power cut-off and generating a signal indicative thereof to restart the computer. Preferably, providing the power to the memory includes providing battery power, and the method includes determining whether the battery provided power to the memory substantially throughout the period of power cut-off and restarting the computer responsive to the determination. Preferably, restarting the computer includes restoring the computer to its state prior to the power cut-off when it is determined that the battery provided the power substantially throughout the period. Further preferably, restarting the computer includes initiating a reboot of the computer when it is determined that the battery did not provide power substantially throughout the period of power cut-off.

In a preferred embodiment, the power cut-off includes a user-initiated cut-off, and the method includes restoring the computer to its state prior to the power cut-off responsive to a user-initiated power-on signal. Preferably, generating the signal responsive to the power cut-off includes generating a signal dependent on a user-selected program for shutting down the computer, and restoring the computer to its prior state includes restoring the computer responsive to the user-selected program.

The present invention will be more fully understood from the following detailed description of the preferred embodiment thereof, taken together with the drawing in which:

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a schematic block diagram illustrating a computer including apparatus to provide resumption of computer operations after loss of power, in accordance with a preferred embodiment of the present invention; and

Fig. 2 is a flow chart illustrating a method of operation of the computer of Fig. 1.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Fig. 1 is a block diagram illustrating a personal computer motherboard 30 including apparatus for saving the state of the computer in case of power failure, in accordance with a preferred embodiment of the present invention. In a prior art motherboard, without elements of the present invention, power from a main computer power supply 2 would be distributed uniformly to all the elements of the motherboard. Consequently, in the event of a failure of AC mains power 1, the only method of saving the state of the system in order to allow resumption of operation upon restoration of the AC Mains Power would be to provide sufficient energy storage within a main computer power supply, typically in the form of internal batteries. Alternatively, an external uninterruptible power supply (UPS) could be provided to prevent the AC mains power failure from affecting the computer.

Motherboard 30 in Fig. 1, which includes modifications to implement the invention, can now be described.

An internal bus 21 interconnects the major elements of the system, including: a BIOS ROM 32 and non-volatile CMOS memory 17; main control logic 16; a CPU 15 and its cache memory 34; and a main memory 14.

These elements are substantially similar to comparable elements known in the art, although certain changes may be made to the BIOS, as described below.

Internal bus 21 and main control logic 16 also connect to an adapter board bus 20 which allows easy connection of various adapter boards 18, such as a modem or other devices to be added to the system at various times. This bus preferably comprises an ISA, EISA or PCI bus, in accordance with standards known in the art, but may alternatively comprise any suitable type of computer bus. A display adapter 12 on bus 21 supports operation cf an external video display monitor (not shown) , although the adapter could also be a part of the motherboard if desired, and the video display need not be external. Refresh circuits 13 are included between some of the connections of ma n memory 14 and internal bus 21. Internal bus 21 and adapter board bus 20 allow control and data signals to be sent efficien iy between the various elements attached to them.

The main added elements for implementation of the present invention comprise those which affect power distribution including a battery charger circuit 4, a battery 6, a power conversion circuit 8, and power distribution switches 9. In addition, refresh circuits 13 and various signals for controlling these added elements are required.

Battery charger circuit 4 keeps battery 6 fully charged during normal operation via a connection 5, and is itself supplied with energy from main computer power supply 2 via normal power distribution connection 3.

The AC mains power is supplied to main power supply 2 via a switch 38. Preferably, switch 38 comprises a logic- controlled switch, including a relay that is controlled by CPU 15. When the switch is depressed while the computer is operating, an interrupt is sent to the CPU. The CPU then sends a control signal back to the switch to operate the relay and turn off the power only after appropriate operations have taken place to shut down the computer and/or to save the current state of the computer. Various shutdown modes may be selected by a user of the computer, as described further hereinbelow with reference to Fig. 2.

The computer operation may be described as being in one of several states or modes: normal, inoperative, save, standby, and restore.

In the normal mode, AC mains power 1 has been applied for some period, and the computer system is functioning without regard to the effects of any past power changes. In the inoperative state, the computer has remained without AC mains power 1 for a period of time sufficient to exhaust battery 6. When AC mains power is restored from the inoperative state, the computer will be required to execute a full reboot process, and it is not possible to resume operation from where it had been before the AC mains power was interrupted.

The save mode, when previously enabled by the system software, is entered upon detection of an AC mains power 1 failure, whether this is caused by an external power failure or by an intentional or unintentional action by the user. The AC mains power failure is automatically sensed by a sensor 36 in the main computer power supply a short time before the power supplied to the motherboard fails. An interrupt signal is sent from the main computer power supply to the CPU in order to initiate the save process. Signals from main control logic 16 are used to control power distribution switches 9 to effect the save process. The storage of the save enable status, as well as other vital system control flags, may be effected in non-volatile CMOS Memory 17. If the main computer power supply design allows one of its outputs to drop before failure of the primary supply voltages, this event may be detected on the motherboard and also used to interrupt the^v-^*CFU to initiate the save process.

The save process begins with CPU 15 signaling main control logic 16 to enable power distribution switches 9 to supply power: a) to main memory 14 through a main memory power circuit 10; b) to a CPU core power circuit 11; and c) to ■ display adapter board 19 through display adapter power circuit 12.

The source of power for power distribution switches 9 derives from power conversion circuit 8, which is itself supplied from battery 6. Power to these elements constitutes a heavy load on the battery, but lasts only a few hundred milliseconds, sufficient to allow saving the current state of the CPU and other devices, termination of all external input/output such as LAN, modem communications and access to disk files, and saving of the display adapter board memory into main memory 1 .

After completion of the initial save process, the CPU is halted, its cache emptied, and power consumption from the battery is significantly reduced by enabling only the main memory and refresh circuits using main memory power circuit 10, which is supplied by power distribution switches 9. At this point, the system enters a standby mode, and a logic latch in power distribution switches 9 is set indicating good battery status.

While in the standby mode, the system is inactive except for power and refreshing of main memory 14. This operation, performed for approximately 1 microsecond every 15 microseconds, requires only a relatively small amount of power. Dn erThβse conditions even a smι % single cell battery could retain the memory contents for several hours. In the event that the battery is about to become exhausted before restoration of AC mains power, the good battery status latch in power distribution switches 9 is reset. The battery status latch can be tested when AC mains power has been restored in order to determine whether battery 6 retained sufficient charge for the entire standby period.

The process of restoring the computer to an active mode can be initiated by one of three events: restoration of the AC mains power, a signal from main computer power supply 2, or detection of correct power levels on normal power distribution connection 3. The restore process begins when one of these initiating events causes a reset signal to be sent to CPU 15. After reset, the CPU first performs a number of basic initialization and self test functions according to a program stored in BIOS memory 17.

The program stored in the BIOS contains a restore function which tests the battery status latch to determine whether the system remained in standby mode until the power was restored. If battery 6 was exhausted during the standby mode, or if the standby mode was not entered, then the BIOS program directs CPU 15 to perform system tests and continue a standard boot process. If the standby mode was successful, the BIOS restore mode program causes execution of a more complete restore program which initializes system adapters to their original modes and states, restores display adapter board 19 memory from main memory 14, restores the state of CPU 15, and continues execution where it had been stopped at the time of the original AC Mains Power failure.

Fig. 2 is a flow chart illustrating modes of shutting down and starting up the computer in response to shut down and power interruptions, in accordance with a preferred embodiment of the present invention. In the case of an unintended power interruption, the computer's operating state is saved in main memory 14, as described hereinabove, until the power is restored. When the power is restored, the computer resumes operation, as described above. In addition, the user of the computer may select among several modes of intentional shut-down, which are implemented using logic-controlled switch 38, under the control of software running on CPU 15. These modes are labeled Mode 1, Mode 2 and Mode 3 in the figure.

Mode 1 is a normal shut-down mode, in which switch 38 operates in the same functional manner as a conventional on/off power switch. In this mode, the user preferably closes all open files and programs and exits from the operating system before operating the switch. Alternatively, when the user depresses the switch, the computer prompts the user to close files and exit before power is cut off .

Mode 2 is an automatic shut-down mode. In this case, when the user depresses switch 38, the CPU 15 autonomously closes all open files and programs and exits from the operating system. Preferably, any opened, unsaved files are saved to disk as temporary files, which may be restored when the computer is powered up and booted. In both this mode and in Mode 1, when the computer is later switched back on (by operating switch 38) , a normal, full boot takes place.

Mode 3 is a "sleep" mode, in which depressing switch 38 causes CPU 15 to save the current operating state of the computer in memory 14, in a manner similar to that described above with reference to an unplanned interruption of AC mains power. As long as AC power is available to power supply 2, the operating state is saved in memory, while using only, minimal electrical power and renσcing wear on other computer components. When switch 38 is depressed again to re-start the computer, the state of the computer is restored from memory 14, in substantially the same manner as described above with regard to the unplanned interruption. The computer thus starts up rapidly, without having to go through a full boot or restoring files from disk.

As noted hereinabove, in some preferred embodiments of the present invention, software modifications are required in BIOS 32 and/or in the computer operating system. If CPU 15 comprises an Intel Pentium or other processor having a System Management Mode (SMM) , as is known in the art, some or all of the modifications may be implemented in an additional non-volatile memory, preferably flash memory (not shown in the figures), added to motherboard 30. In- this manner, the changes needed in the BIOS or operating system are reduced or eliminated. Using SMM, CPU 15 can be made to access the additional memory under appropriate circumstances, such as upon entering or leaving the various modes and operating states described hereinabove.

In summary, the present invention permits a computer system to resume normal operation after the AC mains power has been interrupted. Unlike devices and systems known in the art, the present invention is capable of detecting power loss, saving the current state of the computer and automatically optimizing the computer' s power consumption, using switches 9 and software running on CPU 15, so as to allow automatic resumption of computer operation when power is restored. Unlike uninterruptible power supplies and other backup systems known in the art, the present invention allows the state of the computer to be saved and maintained over relatively long periods of power failure using a battery of minimal size and using relatively simple, low- r_>«wer circuitry, whic_h may be easily integra^te^d with the power cⁱrcu^it•/' present invention a_lso allows a computer's motherboard. ^Tne pre^s w_it_hout user to shut of_f and restart the computer quⁱck^ly, the necessity of booting from disk.

_It wi_{ll b}e a_ppreciated that the preferre^d « °^ _de_scr_ibe_d a_bove _is cite_d by way of exam^ple, ana ^the ful^l s^_pe o_f t_he _invention is limited only by the claⁱms.

Claims

1. Apparatus for preserving the state of a personal computer during a power loss, comprising: a power line sensor, which detects the power loss and generates a signal indicative thereof; a battery, which provides electrical power to selected components of the computer during the power loss; a computer memory, which receives power from the battery and stores data representative of the state of the computer responsive to the signal from the sensor; and switching circuitry, which selects the components needed to preserve the state of the computer to receive power from the battery and cuts off power to .other components in order to conserve energy in the battery.

2. Apparatus according to claim 1, and comprising refresh circuitry, which receives power from the battery and provides signals to the memory to preserve the data stored therein.

3. Apparatus according to claim 1 or 2, wherein the data stored by the memory include a representation of a current state of a central processing unit (CPU) of the computer.

4. Apparatus according to any of the preceding claims, wherein the data stored by the memory include a representation of a current state of a peripheral device associated with the computer.

5. Apparatus according to any of the preceding claims, wherein the data stored by the memory include a representation of current contents of a display memory associated with the computer.

6. Apparatus according to any of the preceding claims, wherein the switching circuitry comprises a battery status indicator, which indicates to the computer during a power-up sequence the battery provided power to the selected components substantially throughout the power loss.

7. Apparatus according to claim 6, wherein an indication from the battery status indicator that the battery provided power substantially throughout the power loss causes the computer to be restored to its state prior to the power loss .

8. Apparatus according to claim 7, wherein the computer is restored to its state by reading out the data stored in the memory.

9. Apparatus according to any of claims 6-8, wherein an indication from the battery status indicator that the battery did not provide power substantially throughout the power loss causes the computer to reboot.

10. Apparatus according to any of the preceding claims, and comprising a programmable logic-controlled power switch, which is operated by a user of the computer to cause the data representative of the state of the computer responsive to the signal from the sensor to be stored in the memory and to actuate the switching circuitry.

11. A method for preserving the state of a personal computer during a power cut-off, comprising: sensing the power cut-off and generating a signal indicative thereof; storing data indicative of the state of the computer in a memory of the computer responsive to the signal; providing power to the memory so that the memory retains the stored data; and switching off power, responsive to the signal, from components other than the memory in order to reduce power consumption by the computer.

12. A method according to claim 11, wherein storing the data in the memory comprises storing a representation of a current state of a central processing unit (CPU) of the comput r .

13. A method according to claim 11 or 12, wherein storing the data in the memory comprises storing a representation of a current state of a peripheral device associated with the computer .

14. A method according to any of claims 11-13, wherein storing the data in the memory comprises storing a representation of current contents of a display memory associated with the computer.

15. A method according to any of claims 11-14, and comprising sensing a resumption of power following the power cut-off and generating a signal indicative thereof to restart the computer.

16. A method according to claim 15, wherein providing the power to the memory comprises providing battery power, and comprising determining whether the battery provided power to the memory substantially throughout the period of power cutoff and restarting the computer responsive to the determinatio .

17. A method according to claim 16, wherein restarting the computer comprises restoring the computer to its state prior to the power cut-off when it is determined that the battery provided the power substantially throughout the period.

18. A method according to claim 16 or 17, wherein restarting the computer comprises initiating a reboot of the computer when it is determined that the battery did not provide power substantially throughout the period of power cut-off.

19. A method according to any of claims 11-15, wherein the power cut-off comprises a user-initiated cut-off.

20. A method according to claim 19, and comprising restoring the computer to its state prior to the power cutoff responsive to a user-initiated power-on signal.

21. A method according to claim 20, wherein generating the signal responsive to the power cut-off comprises generating a signal dependent on a user-selected program for shutting down the computer, and wherein restoring the computer to its prior state comprises restoring the computer responsive to the user-selected program.