WO2000016393A1

WO2000016393A1 - Method of forming interconnects using selective deposition

Info

Publication number: WO2000016393A1
Application number: PCT/US1999/019335
Authority: WO
Inventors: Geeng-Chuan Chern
Original assignee: Atmel Corporation
Priority date: 1998-09-17
Filing date: 1999-08-24
Publication date: 2000-03-23
Also published as: TW437041B

Abstract

A method of forming a multilevel interconnect includes depositing a layer (20) of insulative material atop a first conductive layer (10). Trenches and vias are formed in the insulation layer (20). A thin liner layer (40) is deposited atop the insulation layer (20). Portions of the underlying insulation layer (20) outside of the trenches and vias are exposed by etching away portions of the liner layer (40). A subsequent selective deposition of a conductive material (50) forms only within the trenches and vias, thus creating the interconnect.

Description

METHOD OF FORMING INTERCONNECTS USING SELECTIVE DEPOSITION

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor manufacture and more specifically to a method for forming interconnect structures.

BACKGROUND ART

As the scale of modern integrated circuits increases, sophisticated interconnect structures are required to connect together the various constituent active devices. However, as active device density increases due to the availability of decreasing feature sizes, interconnectivity becomes problematic; the chip area needed to route the interconnect lines exceeds the chip area occupied by the active devices. One way to overcome this limitation is to implement a multilevel interconnection system in which interconnection of the active devices is accomplished by providing one or more levels of interconnects.

The stacking of additional layers on top of one another, however, produces increasingly rugged topography. As additional levels are added in an interconnect scheme and circuit features are scaled to submicron dimensions, the required degree of planarization is increased. Thus, one or more layers must be planarized to prevent topography roughness from growing with each level. Without such planarization, the canyons and dips that result on the wafer surface from stacking of device features can lead to topographical conditions that would eventually reduce chip reliability and chip yields to unacceptable levels.

Chemical mechanical polishing (CMP) is a widely used planarization technique. A CMP polisher comprises a polishing table and a holder for holding the wafer to be polished. A slurry is continuously supplied upon the wafer as a polishing pad is drawn across the wafer. Polishing by CMP involves a combination of chemical reactions between wafer and slurry, and the combined mechanical action of the slurry and the polishing pad.

Various factors must be carefully controlled, such as the material comprising the slurry (typically a suspension containing alumina or silica particles) and the polishing pad, the pressure and rotary velocity of the polishing pad, temperature control and so on. U.S. Patent No. 4,789,648, incorporated herein by reference, shows a planarization process which uses CMP polishing. As can be seen in Fig. 5, a final CMP polishing step is used to planarize metal layer 9. Such a thick layer of metal consumes a large quantity of slurry and time to grind down.

What is needed is a planarization method that avoids the complexity of existing techniques. There is a need for a method of forming multilevel interconnect structures which can minimize the processing costs associated with CMP polishing.

SUMMARY OF THE INVENTION

The method of forming an interconnect in accordance with the invention includes depositing an insulative layer atop a layer of conductive material. This bottom layer may be a conductive layer comprised of active devices, or it may be the metallization layer of a lower interconnect level. Next, the insulative layer is etched to form trenches which will be the traces of the interconnect structure. In addition, one or more contact holes (vias) to the bottom conducting layer are formed through the insulative layer. A liner layer is then deposited over the insulative layer, including those portions of the insulative layer within the trenches and the contact holes. Next, portions of the liner layer outside of the trenches and contact holes are removed. Finally, a conductive material is selectively deposited atop the remaining portions of the liner layer. Optionally, a light planarization step may be applied to improve the planarity of the deposited material by compensating for tolerance variations of the selective deposition.

BRIEF DESCRIPTION OF THE DRAWINGS

Figs. 1A - IF show the processing steps of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to Fig. 1A, a conductive layer 100 is formed atop a semiconductor substrate 10. The conductive layer 12 may be a portion of an active devices as shown in the figure. Alternatively, where the functionality of the integrated circuit is highly complex, two or more levels of interconnect may be needed to connect the devices. In such a case, conductive layer 100 may be a lower interconnect layer, in which case the elements identified by reference numeral 12 are the traces of a lower interconnect layer.

Fig. IB shows the application of a planarized layer 20 atop the conductive layer. Typically, insulation layer 20 is formed by chemical vapor deposition (CVD) of an intermetal dielectric such as Si0₂. However, any of a number of alternate intermetal dielectrics can be used and deposited by methods including plasma-enhanced CVD of Si0₂, bias-sputtered Si0₂, low temperature decomposition of tetraethoxysilane (TEOS) gas to form a Si0₂ film, spin-on glass, low dielectric constant materials, various nitride compounds, and combinations of the above. After deposition, planarization can be achieved by known methods such as CMP. Alternatively, a planar deposition method such as high density plasma (HDP) CVD can be used.

Next, as shown in Fig. 1C, a pattern of trenches 30 and contact holes (vias) 32 are formed into insulation layer 20. The trenches 30 will eventually be filled with a conductive metal which constitutes the traces of the interconnect structure. Similarly, vias 32 will be filled with conductive material to provide electrical contact between the interconnect and the underlying active devices. Alternatively, in an application where two or more levels of interconnects are present, the vias provide an electrical connection to the traces of the underlying interconnect.

Typically the trenches and vias are formed by depositing a first dielectric layer atop substrate 10. Then an etch stop layer is deposited over the first dielectric layer and patterned with openings that correspond with vias 32. A second dielectric layer is then deposited over the etch stop. The second dielectric layer is patterned with a mask having the desired pattern of trenches 30. An etch step is then performed to etch away the portions of the second dielectric layer to form the trenches. The etch stop layer limits the depth of the trenches. Where there are openings in the etch stop layer which expose portions of the first dielectric layer, etching continues to form vias 32. In an alternate technique, a single dielectric layer would be deposited and etched to form trenches 30 and vias 32. This is shown in Fig. 1C. Turning to Fig. ID, a thin liner layer 40 of conductive material is formed. The liner layer serves as an adhesive layer to facilitate the adhesion of the subsequent conductive material onto insulation layer 20. The liner layer also serves as a barrier layer to protect the underlying metal during a subsequent metal deposition step. The material for the liner layer can be any of a number of metallic compounds such as titanium nitride (TiN) , tantalum nitride (TaN) , a multi-layered combination of titanium and TiN, or a titanium-tungsten alloy. Liner layer 40 can be deposited by a sputter deposition method, by CVD, or by a physical vapor deposition process such as an evaporation process. As can be seen in Fig. ID, liner layer 40 is formed upon all of the exposed surfaces of insulation layer 20, including the vertical walls of trenches 30 and vias 32 and upon the exposed portions of the underlying conductive layer 100. Following deposition of the thin liner layer

40, the portions of the liner layer outside of trenches 30 and vias 32 are removed. The result is shown in Fig. IE where the uppermost surfaces 21 of insulation layer 20 become exposed. This can be accomplished via a light etch back treatment using, for example, a sacrificial- layer etchback technique. Alternatively, a CMP process can be used. Recall that liner layer 40 is thin. Thus, an advantage of the present invention is that a CMP polishing step at this point in the process is simpler and less costly as compared to prior art techniques where CMP polishing is applied as a final step to a thick layer of metal. For example, U.S. Patent No. 4,789,648 shows in Fig. 5 a relatively thick metallization layer 9 which is subsequently polished by CMP. Another important aspect of the present invention is that as a consequence of the etchback or polishing step, portions of the underlying surface 21 of insulation layer 20 are exposed and portions of liner layer 40 remain. As will be explained, the presentation of two different surfaces is ideal for the subsequent selective deposition of conductive material to fill trenches 30 and vias 32.

Turning then to Fig. IF, the interconnect is formed by deposition of conductive material 50 in the trenches and vias. A preferred material is copper, but other conductive metals such as tungsten (W) , nickel (Ni, or aluminum (Al) are contemplated. The presence of the two surfaces, namely liner layer 40 and insulation layer 20, permits the use of a selective deposition process of the conductive material; e.g., electroless plating deposition of metals such as Cu, Ni, Au or Pd, or by a selective CVD technique. Consider, for example, selective deposition of tungsten. The electrophysical properties of the two different surfaces enables tungsten to form in the trenches and vias where liner layer 40 is present and not upon exposed surfaces 21 of insulation layer 20. This can be achieved, for example, in a hydrogen reduction reaction of tungsten hexafluoride (WF₆) below approximately 500 degrees C. The surface dissociation of H₂ molecules into atomic hydrogen will not be catalyzed by the Si0₂ comprising the insulation layer, but will be catalyzed on other surfaces such as that of liner layer 40. Thus, tungsten will be selectively deposited only within the trenches and the vias, while leaving exposed the surfaces 21 of insulation layer 20 as shown in Fig. IF. The result is an interconnect structure that requires no subsequent planarization step. However, it may be desirable to perform a light etch to improve the deposition process variation tolerance.

Another example is to use an electroless plating technique to deposit metals such as Cu, Ni, Au, Pd, etc. With electroless plating, the wafer to be plated is immersed in a chemical solution containing metal ions without applying an electric current or potential through electrodes. Plating occurs only to those surfaces on the wafer which have a proper electrochemical potential in the solution. In the case of the present invention, it is possible to select a chemical solution such that liner layer 40 and exposed surfaces 21 have different electrochemical potentials in solution so that selective plating deposition occurs only on the surface of liner layer 40. For example, a liner layer 40 can be formed of a combination of a thin sputtered Cu layer atop a layer of TaN. When surfaces 21 are exposed, a subsequent electroless deposition step in a Cu-containing solution will deposit copper in the trenches and vias 30 and 32 as conductive material 50, while leaving the dielectric materials of exposed surfaces 21 virtually untouched.

Claims

1. A method of providing electrical connections to a conductive layer, comprising the steps of: depositing a first layer of a dielectric material atop a conductive layer, the uppermost surface of the first layer defining a first surface; etching the first layer to create second surfaces below the first surface; forming a second layer entirely of a first conductive material only upon the second surface; and selectively depositing a second conductive material atop the second layer.

2. The method of claim 1 wherein the step of forming a second layer includes forming the second layer atop the first and second surfaces and removing some of the second layer to expose portions of the first surface.

3. The method of claim 2 wherein the step of removing includes one of an etch back step or a polishing step.

4. The method of claim 1 wherein the step of etching the first layer includes forming a pattern of trenches in the first layer.

5. The method of claim 4 wherein the step of etching further includes forming at least one contact hole through to the conductive layer, wherein one of the second surfaces is a surface of the conductive layer.

6. The method of claim 2 wherein the step of removing exposes all of the first surface.

7. The method of claim 1 further including an etch step subsequent to the step of depositing a second conductive material.

8. The method of claim 1 wherein the conductive layer includes active devices.

9. The method of claim 1 wherein the conductive layer is an interconnect layer.

AMENDED CLAIMS

[ received by the International Bureau on 29 December 1999 (29.12.99); original claims 1 and 6 amended; original claims 2 and 3 cancelled; remaining claims unchanged (2 pages) ]

1. A method of providing electrical connections to a conductive layer, comprising the steps of: depositing a first layer of a dielectric material atop a conductive layer, the uppermost surface of the first layer defining a first surface; etching the first layer to create second surfaces below the first surface; forming a second layer entirely of a first conductive material atop the first and second surfaces and removing by polishing some of the second layer to expose portions of the first surface; and selectively depositing a second conductive material atop the second layer.

2. (Cancelled)

3. (Cancelled)

6. The method of claim 1 wherein the step of removing exposes all of the first surface.

8. The method of claim 1 wherein the conductive layer includes active devices.

9. The method of claim 1 wherein the conductive layer is an interconnect layer.

mu mm CAHTJCLE I§)

STATEMENTUNDERARTICLE 19 (1)

Applicant is amending independent claim 1 to point out that the step of forming a second layer entirely of a first conductive material atop the first and second surfaces includes the step of removing by polishing some of the second layer to expose portions of the first surface. Unlike the claims as now amended the cited references of Pintchovski et al. , Ho et al. , and Chow et al . do not teach the use of a polishing step immediately after the formation of the conductive liner layer.

In the present invention, immediately after forming the liner layer of conductive material atop the insulation layer, portions of the liner layer which lie outside of the openings in the insulation layer are removed by polishing. As explained in the specification, providing a chemical mechanical polishing (CMP) step at this point in the process provides the advantage of being simpler and less costly as compared to prior art techniques in which CMP polishing is applied as a final step to a thick layer of metal. Additionally, as a consequence of the polishing step, portions of the underlying surface of the insulation layer are exposed and portions of the liner layer remain. The presence of the two surfaces permits the use of a selective deposition process of the conductive material for filling the trenches and vias.

Applicant has cancelled claims 2 and 3, as the limitations of those claims have now been incorporated into amended claim 1. Applicant has also amended claim 6 to depend from claim 1 rather than from the cancelled claim 2.