WO2000019308A1

WO2000019308A1 - System and method for performing digital signal processing on an ac link bus

Info

Publication number: WO2000019308A1
Application number: PCT/US1999/022652
Authority: WO
Inventors: Conrad M. Maxwell; David P. Braun; George Christopher Sneed
Original assignee: Conexant Systems, Inc.
Priority date: 1998-09-30
Filing date: 1999-09-28
Publication date: 2000-04-06
Also published as: EP1116097A1; TW434483B

Abstract

A system and method for performing digital signal processing on data packets communicated across an AC-link bus directly interconnecting a codec to a codec controller. The system redefines the AC-link bus protocol into a modified protocol which allows digital signal processing to be performed on particular data streams in the data packets. A digital signal processor (DSP) is positioned at a point between the codec and the codec controller to perform the desired signal processing. The redefines AC-link bus protocol to pass desired data streams from time-division multiplexed slots in the AC-link bus protocol packet through the DSP. The DSP is connected to the AC-link bus in a manner to allow the DSP to have real-time access to the input and output data streams traveling through the AC-link bus. This allows real-time signal processing to be performed on data streams communicated over the AC-link bus without requiring access to a host processing device or the codec controller.

Description

SYSTEM AND METHOD FOR PERFORMING

DIGITAL SIGNAL PROCESSING ON AN AC LINK BUS

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The present invention relates generally to the transfer of signals between

a codec and a codec controller through an interconnecting bus, and specifically

to a system and method for reconfiguring the protocol of an AC-link bus to

allow signal processing to be performed on the signals traveling through the

AC-link bus.

DESCRIPTION OF RELATED ART

Personal computers are currently being used for a wide variety of multi-

media applications, where it is now becoming desirable for personal computers

(PCs) to function with high quality audio performance. Current PC audio

architectures are designed to run midrange audio-performance-integrated ISA

products. In order to provide PCs with high performance / high quality audio

comparable to electronics devices, a new PC architecture capable of providing

this performance needed to be developed. Thus, a computer industry

consortium developed a new PC audio architecture, the Audio Codec '97 (AC

'97), for next-generation audio-intensive PC applications, such as DVD, 3-D multiplayer games, and interactive music. The AC '97 architecture defines a

high quality audio architecture for a PC platform to support a wide range of

high quality audio solutions, from a 2-channel mix of digital and analog audio

inside the PC to multi-channel audio outside the PC. The AC '97 includes at

least one codec and codec controller. The codec includes two separate chips,

one for primarily analog applications and one for primarily digital applications.

By separating the functions performed between the analog and digital chips,

individual yields can be improved which lead to overall cost reduction for the

system.

The codec performs digital-to-analog conversion (DAC) and analog-to-

digital conversion (ADC), mixing, analog processing, and modem codec

functions. The codec functions as a slave to a digital codec controller, which,

in turn, is connected to the CPU of the PC, as shown in FIG. 1. The codec

communicates with the codec controller through a digital serial link, referred to

as the AC-link bus. The codec performs the appropriate data conversion and

communicates analog signals to an input/output device. The AC-link bus was

designed to directly connect the codec to the codec controller. In prior PC

architectures, it was necessary to connect an interface device between a codec

and the core logic controlling the codec. The AC '97 eliminates the need for a

separate interface device to be incorporated by utilizing the AC-link bus to

directly connect the codec to the codec controller. The AC-link bus is a bi-directional, 5 -wire, serial time-division

multiplexed (TDM) interface designed for a dedicated point-to-point

interconnect, as illustrated in FIG. 2. All digital audio streams, modem line

codec streams, and command/status information are communicated over the

AC-link bus in data packets. The AC-link bus architecture has a defined

protocol which divides each data packet into 12 outgoing and 12 incoming data

streams. Each of the data streams are positioned in a respective one of the 12

TDM slots in the data packet, as shown in FIG. 3. The output data streams

correspond to the multiplexed bundles of all digital output data targeting the

codec's DAC inputs and control registers.

The industry consortium developing the AC '97 architecture wanted to

promote interoperability between codecs and codec controllers produced by

different vendors to function according to AC-link protocol. Thus, strict

adherence to the specified audio input and output frame slot definitions, AC-

link bus protocol, and electrical timings are required for interoperability to be

maintained between various codecs and codec controllers. The AC-link bus

basically performs one function, it transmits the data streams in the data packets

defined by the AC-link protocol between the codec controller and the codec, so

that the AC-link bus merely provides a direct data link between the codec and

the codec controller.

No significant signal processing can be performed on the data streams

communicated through the AC-link bus defined by the industry consortium. If it is desirous to perform signal processing on any of the data streams in a data

packet, it is necessary to send the data packet through the codec controller to

the host CPU of the PC where a signal processing algorithm can perform the

desired signal processing. The processed signal must then be transmitted back

through the codec controller, through the AC-link, and to the codec, where it is

transmitted to the respective input/output device. However, requiring the host

CPU to perform signal processing functions can be inefficient, since certain

signal processing applications require real-time access to the data in order to

function properly. The architecture of the AC '97 set forth by the industry

consortium does not allow such real-time signal processing to be performed.

There is clearly a need for a system and method for performing signal

processing on the data streams of data packets transmitted over an AC-link bus

directly in a real time manner. Moreover, there is a need for a system and

method for performing signal processing on the data streams of data packets

transmitted over an AC-link bus in a flexible and efficient manner without

having to send the data streams through the codec controller to a host CPU to

perform the desired signal processing.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to overcome the

aforementioned shortcomings associated with the prior art. The present invention provides a system and method for performing

real-time signal processing of data streams communicated over an AC-link bus.

The system and method for performing signal processing on an AC-link

bus of the present invention allows real-time signal processing to be performed

on both input and output data streams without requiring access to a host CPU.

These as well as additional advantages of the present invention are

achieved by providing a system and method for performing signal processing

on data streams in a data packet transmitted between a codec and a codec

controller over an AC-link bus. The codec connected to the AC-link bus is

configured for a particular AC-link bus protocol, so that the codec recognizes

which type of data stream appears in a data packet received over the AC-link

bus. Currently, the AC-link bus protocol defines twelve (12) TDM data slots,

where each data slot is assigned a respective data stream accomplishing a

particular function with one of the data slots containing TAG information about

the data packet. The codec then performs any necessary data conversion and

transmits the data appearing in a particular TDM slot to an associated

input/output device. The present invention redefines the AC-link bus protocol

in order to allow signal processing to be performed on a desired data stream

transmitted between the codec and codec controller.

The system and method of the present invention redefines the AC-link

bus protocol in order to pass a desired data stream appearing in a respective one

of the TDM slots of a data packet through a digital signal processor (DSP) directly connected to the codec. The data stream appearing in the respective

one of the TDM slots is passed through the DSP for signal processing before

being transmitted to the codec. Similarly, input data from the codec can be sent

through the DSP prior to entering the codec controller or without having to

enter the codec controller at all. The DSP is connected between the codec and

the codec controller, so that the DSP is arranged to receive signals traveling

through the AC-link bus. The DSP may be connected either directly in the

point to point connection between the codec and codec controller or may be

coupled to the AC-link bus to branch off a portion of the data packets

transmitted over the AC-link bus. This allows the DSP to have real-time access

to the input and output data streams traveling through the AC-link bus, so that

signal processing can be performed without multiple communications to the

codec controller or host computer CPU .

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention, which are believed to be novel, are

set forth with particularity in the appended claims. The present invention, both as

to its organization and manner of operation, together with further advantages,

may best be understood by reference to the following description, taken in

connection with the accompanying drawings in which the reference numerals

designate like parts throughout the figures thereof and wherein: FIG. 1 is a schematic block diagram of an Audio Codec '97 computer

architecture.

FIG. 2 is a schematic block diagram of the AC-link bus connection

between the codec and companion controller of the Audio Codec '97 architecture

of FIG. 1.

FIG. 3 shows the time-division multiplexed (TDM) slot assignment

protocol for the input and output data frames transmitted across the AC-link bus

of FIG. 2.

FIG. 4 is a schematic block diagram of a preferred embodiment of the

system for performing signal processing on an AC-link bus of the present

invention.

FIG. 5 is a schematic block diagram of another preferred embodiment of

the system for performing signal processing on an AC-link bus of the present

invention.

FIG. 6 is an operational block diagram of a preferred method of the

present invention for performing signal processing on an AC-link bus.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description is provided to enable any person skilled in the

art to make and use the invention and sets forth the best modes contemplated by

the inventors of carrying out their invention. Various modifications, however,

will remain readily apparent to those skilled in the art, since the general principles of the present invention have been defined herein specifically to provide a system

and method for performing signal processing on data streams transmitted over an

AC-link bus.

Referring back to FIG. 3, the slot assignments for the data streams

comprising each incoming and outgoing TDM data packet transmitted across the

AC-link bus according to the AC-link bus protocol are illustrated. The AC-link

bus protocol defines twelve (12) TDM data slots, where each data slot is assigned

a respective data stream corresponding to a particular function. The codec

connected to the AC-link bus is configured for this AC-link bus protocol, so that

the codec recognizes which type of data stream appears in a particular TDM data

slot. The codec then performs any necessary data conversion and transmits the

data appearing in a particular TDM slot to its associated input/output device. For

instance, slots 3 and 4 on both the incoming and outgoing data frames contain

data streams for left and right speaker devices, respectively. The codec will

perform digital-to-analog conversion on the data stream appearing in slot 3 of the

data frame received from the AC-link bus and transmit the converted signal to the

left speaker.

The system 100 of the present invention redefines the AC-link bus

protocol in order to pass predetermined data streams in the TDM slots through a

digital signal processor (DSP) 102 directly connected to the AC-link bus 108

through link 110, as illustrated in a block schematic diagram in FIG. 4. Through

link 110, the DSP 102 is connected to branch off a portion of the signals transmitted between the codec 104 and the codec controller 106. Codec 104 may

comprise any device which functions as an analog front end to the system 100.

Further, the codec 104 and codec controller 106 selected for the system 100

should operate using a digital TDM data packet protocol similar to the AC-link

bus protocol shown in FIG 3. The AC-link bus protocol defined by the industry

consortium is set forth in the Audio Codec '97 Component Specification,

Revision 1.03, released September 15, 1996 by the Audio Codec '97 Working

Group, Audio Codec '97, Revision 2.0, released September 29, 1997 by Intel

Corporation, and Audio Codec '97, Revision 2.1, released May 22, 1998 by Intel

Corporation. The disclosures of Revisions 1.03, 2.0, and 2.1 of the Audio Codec

'97 are hereby incorporated by reference into this disclosure. While the present

invention is specifically described as solving limitations presented by the Audio

Codec '97, it is understood that the present invention may also be applied to any

digital serial link bus directly connecting a codec to its respective codec

controller.

The DSP 102 may be connected between the codec 104 and codec

controller 106 in any number of manners. For instance, the DSP 102 may be

directly connected to the codec 104 as shown in FIG 4. In this embodiment, only

the portion of the signals to be processed are branched off from the AC-link bus

108 into the DSP 102. The processed signals are then fed from the DSP 102 to a

respective codec 104. Alternatively, the DSP 102 may be connected in a parallel

relationship to the AC-link bus 108 as shown in FIG 5. When connected in parallel to the AC-link bus 108, the DSP 102 is arranged so that either a portion

of a signal traveling through the AC-link bus 108 or the entire signal is branched

off into the DSP 102 for signal processing and then coupled back into the AC-

link bus 108 through links 110 and 112. The processed data streams are then

positioned back into their respective TDM slots in the transmitted data packet. In

another preferred embodiment of the present invention, the DSP 102 may be

connected directly in the point-to-point communication path of the AC-link bus

108, as shown in FIG. 6. In this embodiment, all of the signals transmitted over

the AC-link bus 108 are passed through the DSP 102 and then back onto the AC-

link bus 108.

In each of the possible embodiments of the system 100 for performing

signal processing on an AC-link bus 108 of the present invention, selected data

streams from their TDM data slots in the data packets are passed through the DSP

102. Up to four codecs 104 may be connected to and supported by a single AC-

link bus 108. Each data packet transmitted over the AC-link bus 108 includes

TAG information appearing in its first TDM data slot which may be used to

instruct the DSP 102 which portions of the data packet to process through a

particular DSP 102 for performing a particular function. Thus, the DSP 102 only

takes the portion of the packet needed for processing and the remaining portion of

the packet is left alone, so that other standard devices can co-exist on the AC-link

bus 108 with the DSP 102. Further, this arrangement also allows multiple DSPs

102 to be connected to the AC-link bus 108 to perform a variety of functions. By providing the DSP 102 between the codec 104 and codec controller

106, the DSP 102 has real-time access to the data packets communicated over the

AC-link bus 108. This allows certain signal processing functions to be performed

more efficiently and with an improved quality over previous architectures which

required the use of the codec controller 106 and host CPU to accomplish such

signal processing. In order to allow the codec 104 and codec controller 106 to

send and receive data packets normally while also performing digital signal

processing on the data packets, the system 100 of the present invention

reconfigures the AC-link bus 108 protocol to route the desired data streams in the

transmitted data packets through a DSP 102 on their way to a codec 104.

Referring now to FIG. 7, an operational block diagram of the method for

performing signal processing on the data packets communicated through an AC-

link bus 108 is illustrated. Initially in step 200, a data packet is formed using the

AC-link bus 108 protocol as shown in FIG. 3. The data packet may either be an

outgoing data packet prepared by the codec controller 106 or an incoming data

packet prepared by the codec 104. Rather than transmit this data packet as

formed over the AC-link bus 108 as previously done in known PC architectures,

the present invention redefines the bus protocol in step 202 in order to allow at

least one of the data streams in the data packet to be passed through DSP 102 for

signal processing. The AC-link bus 108 protocol is redefined according to the

desired digital signal processing to be performed on the data streams. The data

packet is modified according to the redefined bus protocol into a modified packet including the data streams to be processed. The modified packet is then

transmitted to the DSP 102 in step 204 for the desired signal processing to be

performed. After processing the desired data stream in the modified packet, the

DSP 102 outputs the processed signal to the AC-link bus 108 for transmission

according to AC-link bus protocol in step 206.

The DSP 102 can perform any type of digital signal processing function,

such as mixing, compression, decompression, filtering, audio effects, synthesis,

speech recognition, delay lines, or any other signal processing. The DSP 102 can

either be configured to perform a specific type of signal processing or,

alternatively, can be formed to be reconfigurable, such as by specific application

programs downloaded onto the personal computer. Furthermore, the DSP 102

can communicate directly with either the codec 104 or codec controller 106, so

that signals can be communicated directly between one of these devices and the

DSP 102. This further exemplifies how the present invention allows real-time

signal processing to be performed without having to transmit signals to the host

CPU for processing. With the understanding that the present invention provides a

system and method of performing any type of digital signal processing to be

performed on the data packets transmitted over an AC-link bus 108, the

following examples are set forth to illustrate manners in which the present

invention can be implemented. Example 1

For audio information to be output by the left and right speakers of a

personal computer, audio data streams containing such information would be

formed and placed in TDM slots 3 and 4, respectively, of the data packet

transmitted from the codec controller 106 to an audio codec 104. If certain

digital signal processing is desired to be performed on these data streams, such as

adding base to the signal or stripping out frequencies from the signal to be output

by the left speaker, then the data packet would be modified to route the left

speaker data stream to be processed by DSP 102. The data stream found in TDM

slot 3 of the data packet, corresponding to the left speaker information, would be

removed from the data packet and transmitted to the DSP 102, so that base could

be added or frequencies could be stripped out of the left speaker information.

The processed left speaker signal would then be reinserted in TDM slot 3 of the

data packet according to the AC-link bus protocol. The data packet including the

signal processed left speaker data stream is then transmitted to the audio codec

104 for digital-to-analog conversion, where the analog signal is then sent to the

left speaker of the personal computer. Thus, particular DSP functions can be

implemented in an efficient manner on the speaker data streams as they are

transmitted between the codec controller 106 and audio codec 104. Example 2

Acoustic echo cancellation (AEC) is an important digital signal processing

function performed in speaker phones to ensure that audio information output on

speakers is not input back into the microphone in loop fashion. In performing

AEC, the audio output by the speaker is stored and then removed from the audio

signal produced by the microphone to prevent the speaker audio output from re-

entering the microphone input and causing an echo effect. By reconfiguring the

AC-link bus protocol to pass the outgoing data streams for the audio speakers

(i.e., data streams in TDM slots 3 and 4 of the outgoing data packet) through the

DSP 102 as well as the incoming data stream from the microphone (i.e., TDM

slot 6 of the incoming data packet), the necessary AEC can be performed by the

DSP 102 with real-time access to the incoming and outgoing data streams. The

DSP 102 may then output the processed signal onto the AC-link bus 108 for

transmission to the codec controller 106. In this manner, the AEC has already

been performed on the incoming data stream before it is even sent to the codec

controller 106, which improves the efficiency and overall quality of the AEC

function.

It is understood that the above-described examples are merely described

for the purpose of illustrating possible ways in which the system and method of

the present invention can perform signal processing on an AC-link bus. These

examples are not intended to and do not encompass all possible types of digital signal processing which can be performed on the data streams communicated

over the AC-link bus.

The AC-link bus 108 protocol may be redefined using special software,

firmware, a state machine, or other similar manners developed to redefine the

bus protocol in accordance with the present invention.- When using software,

software drivers may be installed on the PC connected to the AC-link bus 108

in order to implement the software, where these software drivers will replace

the existing AC-link bus 108 protocol with the redefined protocol. This

specially software or hardware provides the redefined protocol necessary to

allow the desired data streams to be sent to the DSP 102 for digital signal

processing to be performed.

As can be seen from the foregoing, a system and method for performing

signal processing on an AC-link bus formed in accordance with the present

invention allows real-time signal processing to be performed on data streams

communicated over an AC-link bus. Moreover, by forming a system and

method for performing signal processing on an AC-link bus in accordance with

the present invention, signal processing functions can be performed on data

streams communicated to and from a codec without requiring access to a host

CPU or codec controller. Furthermore, by forming a system and method for

performing signal processing on an AC-link bus in accordance with the present

invention, the data streams communicated between a codec controller and a

codec can be flexibly and efficiently digitally signal processed. In each of the above embodiments, the structures of the system and

method for performing signal processing on an AC-link bus of the present

invention are described separately in each of the embodiments. However, it is

the full intention of the inventors of the present invention that the separate

aspects of each embodiment described herein may be combined with the other

embodiments described herein. Those skilled in the art will appreciate that

various adaptations and modifications of the just-described preferred

embodiment can be configured without departing from the scope and spirit of

the invention. For instance, the present invention may be readily applied to

variations of the TDM data packet protocol described above. Therefore, it is to

be understood that, within the scope of the appended claims, the invention may

be practiced other than as specifically described herein.

Claims

CLAIMSWhat Is Claimed Is:

1. A system for performing signal processing on data signals communicated over an AC-link bus designed to directly link a codec to a codec controller, comprising: a codec arranged to communicate signals to an input/output device; a codec controller for controlling the operation of the codec; an AC-link bus connected to provide a communication path for data signals transmitted between the codec and the codec controller; and a digital signal processor connected between the codec and the codec controller, wherein the digital signal processor is arranged to receive at least a portion of the data signals transmitted over the AC-link bus.

2. The system of claim 1, wherein the digital signal processor is positioned along the AC-link bus directly in the point-to-point connection between the codec and the codec controller.

3. The system of claim 1, wherein the digital signal processor is arranged in parallel to the AC-link bus. wherein the portion of the signals received by the digital signal processor is branched off of the data signals being transmitted over the AC-link bus.

4. The system of claim 3, wherein all of the data signals being transmitted over the AC-link bus are branched off into the digital signal processor.

5. The system of claim 1, wherein the signals are transmitted across the AC-link bus in packets of digital data according to a predetermined protocol which is redefined in order to send a desired portion of the signals to the digital signal processor.

6. The system of claim 5, wherein the predetermined protocol for the AC-link bus defines each data packet to include a plurality of time-division multiplexed data slots, each of the data slots containing a respective data stream.

7. A method of performing signal processing on data signals communicated over a bus linking a codec to a codec controller, wherein the data signals are communicated in packets of digital data according to a predetermined communication protocol, comprising the steps of: forming the digital data packet according to the predetermined communication protocol; redefining the communication protocol to specify at least a portion of the digital data packet to be digitally signal processed; modifying the digital data packet according to the redefined communication protocol; and transmitting the specified portion of the modified digital data packet to a signal processing device connected to the bus for digital signal processing to be performed.

8. The method of claim 7, further comprising the step of outputting a processed signal from the signal processing device onto the bus to be communicated to either of the codec or codec controller:

9. The method of claim 7, wherein the predetermined protocol for the bus defines each digital data packet to include a plurality of time-division multiplexed data slots, each of the data slots containing a respective data stream.

10. The method of claim 9, wherein the bus is an AC-link bus.

11. The method of claim 7, wherein the entire modified digital data packet is transmitted to the signal processing device.

12. A storage medium which stores a program for performing digital signal processing on a digital data packet communicated over a bus linking a codec to a codec controller according to a predetermined communication protocol, said program including: a protocol redefining step for redefining the communication protocol of the bus to specify at least a portion of the digital data packet to be transmitted to a digital signal processing device connected to the bus for digital signal processing to be performed; a extracting step for extracting the identified portion of the digital data packet and transmitting the identified portion to the digital signal processing device; and a digital signal processing step for digitally signal processing the extracted portion of the digital data packet.

13. The storage medium of claim 12, wherein said program further includes a reintroduction step for reintroducing the digitally signal processed extracted portion of the digital data packet onto the bus linking the codec to the codec controller.

14. The storage medium of claim 12, wherein said program further includes a transmission step for transmitting the digitally signal processed extracted portion of the digital data packet to the codec.