WO2000019537A1

WO2000019537A1 - Three dimensional rom

Info

Publication number: WO2000019537A1
Application number: PCT/CN1999/000127
Authority: WO
Inventors: Guobiao Zhang
Original assignee: Guobiao Zhang
Priority date: 1998-09-24
Filing date: 1999-08-27
Publication date: 2000-04-06
Also published as: CN1099695C; CN1212452A; AU5406199A

Abstract

A memory structure, having a three dimensional arrangement of memory elements, is disclosed. The memory elements are partitioned into multiple memory levels. Each memory level is stacked on top of another. Within each memory level, there are a plurality of memory elements and address select lines. The memory elements can be either factory programmable or electrical programmable due to three dimentional arrangement of memory elements, memory density and memory capacity maximally improved. An access time of read-only memory structure is short. A read-only memory structure is manufactured by standard semiconductor process. The present invention may be used widely to various fields.

Description

Three-dimensional read-only memory

The present invention relates to the field of integrated circuits, and more particularly, to a three-dimensional memory in an integrated circuit and a manufacturing method thereof.

Background technique

Read-only memory is a device that stores fixed information. Its information is programmed during manufacture or when used by the user. Conventional ROMs are arranged in a two-dimensional array on a semiconductor substrate. At each intersection of this array there is a memory cell that provides a resistive, inductive, capacitive, diode-type or coupling mechanism using active components. Each storage element represents a piece of digital information. At the same time, each memory cell is connected to the input and output through electrical signals, which can ensure a very short access time. There are two types of read-only memory: one is factory-programmed read-only memory, including mask-programmed read-only memory (MPROM), and the other is user-programmed read-only memory, including electrical programming read-only memory (EPROM). MPROM information is controlled by a reticle during manufacture. On the other hand, EPROM information can be written at least once by the user.

U.S. Patent 5,429,968 (July 4, 1995) to Koyoma is an example of existing MPROM technology. It uses a field-effect transistor as a storage element, and changes the digital information in the storage element by adjusting the threshold voltage of the FET. By adjusting the amount of ion implantation, the FETs at different locations become enhanced or depleted. Under the proper voltage, the enhanced FET is turned on and the depleted FET is turned on. By detecting the current on different bit lines, digital information at different locations can be read. Since these FETs can only be formed on a semiconductor substrate, this MPROM can only be arranged in a two-dimensional structure.

On the other hand, EPROM generally uses a resistive coupling mechanism to represent digital information. Representative resistive coupling mechanisms include fuses and antifuse. US Patent 4,899,205 to Hamdy et al. (February 6, 1990) describes the use of a silicon-silicon antifuse as a programming element 2D EPROM. In this structure, the source / drain of the anti-fuse and the access FET are integrated to form a memory. Yuan. Because the access FET must be grown on a semiconductor substrate, EPROMs using silicon-silicon antifuse can only be arranged in a two-dimensional array. When using this structure, the amount of digital information on a unit area chip is limited by the size of the access field effect transistor. U.S. Patent No. 4,442,507 to Roesner et al. (April 10, 1984) describes another electrically programmable read-only memory. It uses a Schottky diode stack as a memory cell. One of its address selection lines is generated from polysilicon, and the other of its address selection lines is generated from aluminum. Because the polysilicon formation temperature needs at least 600, and the maximum temperature that aluminum can withstand is 500X. So polysilicon cannot grow on aluminum. Therefore, this memory can only use one layer of EPROM. At the same time, Roesner's patented manufacturing process is: first forming a transistor and an interconnect on a substrate, and then forming a read-only memory over the transistor. That is, the transistor and its interconnects are subjected to a high temperature of 600X during the manufacture of the ROM. In the prior art, the interconnect lines of the transistors are all made of highly conductive materials, such as aluminum (A1). These materials are not stable at 6001: high temperatures and can cause a variety of problems. Therefore, Roesner's read-only memory not only has limited storage density, but also causes difficulties in the process of transistor circuits on the substrate.

As described above, since the memory cells of the read-only memory in the prior art are formed on a substrate made of a semiconductor material, that is, the prior art can only arrange the memory cells in an integrated circuit in a two-dimensional space, so that The storage density of the read-only memory is greatly limited. In addition, the word lines formed of polysilicon in the prior art also have the disadvantages of large resistivity and slow access rate.

Summary of the Invention

In order to improve the storage density of the memory in the integrated circuit, the inventors set the storage element in a three-dimensional form based on changing the constituent material of the storage element from the perspective of improving the setting dimensions of the storage element, thereby improving the storage density. It can also improve access speed. To generate a memory cell in three dimensions, it means that the read-only memory has multiple overlapping memory layers, and each memory layer has multiple memory cells and corresponding word lines and bit lines. The overlapping of multiple storage layers requires that the lower storage layer must provide a good foundation for the upper storage layer. With the advent of chemical mechanical polishing (CMP) technology, this requirement can be easily met. A first object of the present invention is to provide a three-dimensional memory device including at least one memory layer.

A second object of the present invention is to provide a method for manufacturing a three-dimensional memory; a third object of the present invention is to provide a novel three-dimensional read-only memory cell.

The read-only memory cell of the present invention includes: a first electrode containing a metal material; a second electrode containing a metal material; and a quasi-conduction film sandwiched between the first and second electrodes.

The three-dimensional memory of the present invention includes at least: a substrate including a plurality of transistors and a plurality of metallization interconnection lines coupling at least part of the transistors to each other; a first insulation covering at least part of the transistors and at least part of the metal interconnection lines A dielectric film; a plurality of first interlayer connection channel openings passing through at least a portion of the first insulating dielectric film; and a first storage layer formed on the first insulating dielectric film, the first storage layer containing A plurality of first memory cells and a plurality of first address selection lines containing a metal material.

The method for manufacturing a three-dimensional memory of the present invention includes at least the following steps: a) forming a plurality of transistors on a substrate and a plurality of metallization interconnection lines coupling at least a part of the transistors to each other; b) forming a cover that covers at least part of The transistor and a first insulating dielectric film of at least a portion of the metallized interconnection line; c) forming at least one first interlayer connection channel opening passing through at least a portion of the first insulating dielectric film; d) in the first A first memory layer is formed on the insulating dielectric film, and the first memory layer includes a plurality of first memory cells and a plurality of first address selection lines containing a metal material.

Since both electrodes of the read-only memory cell of the present invention are composed of a metal material, not only does not occupy a space on the semiconductor substrate, makes the manufacture of a three-dimensional memory possible, but also the memory cell made of a semiconductor material with at least one electrode Compared with this, it also has the advantages of small resistivity and faster storage speed.

The three-dimensional memory of the present invention arranges storage elements in a three-dimensional space, thereby greatly improving the storage density and capacity of the memory, and because the three-dimensional memory of the present invention can be integrated with other semiconductor circuits, thereby improving the data / The instruction transfer rate reduces the access time.

The manufacturing process of the three-dimensional memory of the present invention can be compared with the conventional semiconductor manufacturing process Compatible. Therefore, it can be manufactured using standard semiconductor production equipment and processes. The peripheral circuit design of the three-dimensional memory of the present invention can make use of the existing peripheral circuit designs of various memories, so the design cycle can be shortened.

Overview of the drawings

The three-dimensional read-only memory and its manufacturing method of the present invention will be described in detail below with reference to the drawings. among them,

Figure 1 is a perspective view showing a 3D-ROM with two memory layers.

Figure 2 shows a circuit diagram on a 3D-MPROM chip substrate. This circuit provides addressing and reading functions.

Figure 3 is a circuit diagram showing a 3D-EPROM chip substrate. This circuit provides addressing, programming, and reading functions.

Fig. 4 is a sectional view showing a 3D-ROM memory cell.

5A-5C are cross-sectional views showing several MPROM films.

6A to 6E are cross-sectional views showing several 3D-MPROM memory cells.

Figure 7 shows a 4-memory array in the most difficult-to-read case, where O represents 0 and X represents 1.

FIG. 8 is a volt-ampere characteristic curve showing the logic "0" and the logic "Γ" of the 3D-MPROM film.

FIG. 9A is a cross-sectional view describing a first EPROM film; FIG. 9B is a cross-sectional view describing a second EPROM film;

Fig. 9C is a cross-sectional view illustrating a third type of EPROM film.

FIG. 10A is a cross-sectional view showing a 3D-EPROM memory cell; FIG. 10B is a cross-sectional view showing another 3D-EPROM memory cell.

Figure 11 shows the volt-ampere characteristic curves of the quasi-conduction film, antifuse film, and EPROM film.

FIG. 12A is a top view showing a first type of wiring in a 3D-ROM storage layer; FIG.

FIG. 12B is a top view showing a second type of wiring in a 3D-ROM storage layer; FIG. FIG. 12C is a plan view showing a third type of wiring in a 3D-ROM memory layer.

Figure 13 is a cross-sectional view showing the structure of the first 3D-ROM memory.

FIG. 14 is a cross-sectional view showing a second 3D-ROM memory structure.

15A-15B are cross-sectional views showing a third type of 3D-ROM memory structure. Best practice

Figure 1 shows a 2 X 2 X 2 3D-ROM. Here, the symbol Z x / wx / i 3D-ROM refers to a 3D-ROM containing / memory layers, m word lines and "bit lines." This 3D-ROM is grown on a semiconductor substrate 10, which has Two storage layers 100, 200. The substrate 10 may contain multiple transistors. With the prior art, these transistors can easily form addressing circuits, memory circuits, central processor circuits, etc., through metallized interconnect lines. The bottom surface is an XY plane, and each storage layer plane is parallel to the substrate surface. The storage layer 200 is stacked on top of the storage layer 100, that is, stacked in the Z direction. Each storage layer consists of a 2 x 2 memory cell array, two along the X Address selection lines in the direction and two address selection lines in the Y direction. The address selection lines in the X direction are called word lines, and they include the word lines 101 and 102 on the memory layer 100 and the word line 201 on the memory layer 200. , 202. The address selection lines in the Y direction are called bit lines, and they include bit lines 111 and 112 on the memory layer 100 and bit lines 211 and 212 on the memory layer 200. At least one address selection line, preferably two Kinds of address selection lines, which contain high conductivity materials, such as aluminum (A1), copper (Cu), silver (Ag), gold (An), etc. The film conductivity of at least one type of address selection line is less than 1 ohm / □. Using high-conductivity material as the address selection line can increase the memory speed. There are memory cells at the intersection of word line and bit line, such as 121-124, 221-224. Each memory cell can store a bit of binary information and A coupling mechanism is provided between the word line and the bit line. Such coupling mechanisms include resistive, inductive, capacitive, diode-type or coupling mechanisms using active components. Each memory cell is represented by changing the size of the coupling mechanism One bit of binary information. The address select line provides a programming / reading path for the selected memory cell.

FIG. 1 also shows how the substrate 10 and the address selection lines in different memory layers are connected. In the memory layer 100, the word lines 101, 102 pass through the contact hole 101a, 102a is connected to the substrate 10 at the contact points 131, 132. On the other hand, the bit lines 111 and 112 are connected to the substrate 10 at the contact points 141 and 142 through the contact channel holes 111a and 112a. Similarly, in the memory layer 200, the word lines 201 and 202 are connected to the substrate 10 at the contact points 231 and 232 through the contact channel holes 201a and 202a. On the other hand, the bit lines 211 and 212 are connected to the substrate 10 at the contact points 241 and 242 through the contact channel holes 211a and 212a. In order to connect the memory layer 200 and the substrate 10, the address selection line needs to be extended. For example, the bit line 211 must extend beyond the contact channel hole 111a until it contacts the channel hole 211a, so as not to damage the bit line 111 or the contact channel hole 111a. .

Figure 1 shows a 2 x 2 x 2 3D-MPROM addressing / reading circuit diagram. Since a transistor is used to perform the addressing and reading functions, the addressing / reading circuit needs to be built on a semiconductor substrate 10. It consists of a Z address decoder 190, two X address decoders 160, 260, and two Y address decoders 170, 270. Z address decoder 190 contains X address input 191, Y address input 192, and Z address input 193. These inputs are connected to the input pins of the semiconductor manifold or some other circuit.

In order to address / read information stored in a memory cell (for example, memory cell 121 in FIG. 1), an appropriate voltage must be applied to the X, Y, and Z address inputs 191, 192, and 193 to make memory cell 121 The applied voltage is equal to the read voltage V _R. The level signal applied to Z address input 193 can realize the connection of the following two electrical signals: one is between X address input 1 ⁹ 1 and X address input 1 (161), and the other is at Y address input 192 and Enter the Y address between 1 (171). Therefore, when the address signal on X address input 191 and the address signal on Y address input 192 are input to X address decoder 1 (160) and Y address decoder 1 (170) respectively, only The voltage of the address lines on the storage layer 100 will change accordingly. At the same time, the level signal on Z address input 193 enables the connection between output 1 (164) of X address decoder 1 (160) and output 196 of Z address decoder 190.

The address signal on the X address decoder 1 (160) raises the voltage at the contact point 131 to half the read voltage V _R , V _R / 2. At the same time, Y address decoder 1 (170) The addressing signal of 降 drops the voltage at contact point 141 to a negative 1/2 reading voltage,-V _R / 2. By contacting the channel holes 101a and 111a, the voltage on the word line 101 is therefore also increased to V _R / 2, and the voltage on the bit line 111 is reduced to -V _R / 2. Thus, a read voltage V _R is applied across the memory element 121. For different states of the memory cell 121, there are different currents on the word line 101. The output signal goes from output 1 (164) to output 196 and then to the output pin. Thus, the information stored in the memory element 121 can be read.

FIG. 3 is a circuit diagram of addressing / reading / programming, which shows a 2 × 2 χ 2 3D-EPROM. Similar to the circuit of FIG. 2, this circuit is also formed on a semiconductor substrate 10. It includes a Z address decoder 190, two X address decoders 160, 260, and two Y address decoders 170, 270. In addition to the X, Y, and Z address inputs 191, 192, and 193, the Z address decoder 190 includes an output 196, a PGM 195 that is programmed, a power supply 197 that is half the programming voltage (V _PP / 2), and a voltage that is Power supply 198 with a negative programming voltage half (-V _PP / 2).

The read operation of 3D-EPROM is similar to that of 3D-MPROM. The programming of 3D-EPROM can be performed in the following way. For example, in order to program memory cell 224 in Figure 1, Z address input 193 should make X address input 191, Y address input 192, Vpp / 2 power supply 197, -Vpp / 2 Power supply 198 and PGM 195 are connected to their corresponding terminals on X address decoder 2 (260) and Y address decoder 2 (270). Then, the word line 202 and the bit line 212 are selected by the signals of the contact points 232 and 242 on the X and Y address lines. When PGM 195 is selected, the voltage of word line 202 rises to V _PP / 2, and the voltage of bit line 212 drops to -V _PP / 2, while other address lines are grounded. Because the memory cell 224 is located at the intersection of the word line 202 and the bit line 212, the voltage applied to it is a programming voltage V _PP . Thus, memory cell 224 is programmed. On the other hand, the voltage applied to the other memory cells is only V _PP / 2, and they continue to be in their unprogrammed state.

Figure 4 shows a cross-sectional view of a 3D-ROM memory cell of the present invention. It has a top electrode 501, a ROM film 502, a bottom electrode 503, and a field region 504. The top electrode 501 is used as an address line, for example, as a bit line. It consists of Metal material composition. Here, the metal material refers to a metal element, a metal alloy, and a metal compound, for example, aluminum or copper having a thickness between 0.2 and 2 μm, and preferably 0.5 μm. Between the top electrode 501 and the ROM film 502, there may also be a barrier metal film, such as TiW. This barrier film prevents a reaction between the top electrode 501 and the ROM film 502. The bottom electrode 503 can be used as another address line, for example, a word line. It also contains metallic materials, such as aluminum or copper with a thickness between 0.2-2 μm, preferably 0.5 μm. There may also be a barrier film between the bottom electrode 503 and the ROM film 502, for example, TiW. This barrier film prevents a reaction between the bottom electrode 503 and the ROM film 502.

The ROM film 502 represents digital information stored in this memory cell. The ROM film is called MPROM film in MPROM. If the MPROM film is in a high-resistance state at a read voltage, it represents "0" logic. Accordingly, the "0" logic MPROM film is called a barrier film. On the other hand, if the MPROM film is in a low-resistance state at a read voltage, it represents "1" logic. Accordingly, the MPROM film of "Γ logic" is called a quasi-conduction film. The reason for using the "quasi-conduction film" will be explained in more detail in FIGS. 7 and 8.

In EPROM, the ROM film is called EPROM film. The EPROM film contains a quasi-conduction film and an antifuse film. The quasi-conducting film has the same characteristics as the quasi-conducting film in 3D-MPROM. The anti-fuse film is in a high resistance state before programming, and it irreversibly transitions to a low resistance state after programming. For a newly shipped EPROM chip, the antifuse film is complete. Therefore, the EPROM film is in a high-resistance state and represents "0" logic. After programming, the anti-fuse film becomes a low-resistance state. Accordingly, the EPROM film becomes a quasi-conduction film and represents "logic." Different The memory cells are separated from each other by a field region 504. The field region 504 is composed of an insulating material (for example, silicon oxide). Its thickness is between 0.2 and 2 μm, and preferably 0.5 μm.

Figures 5A to 5C show several MPROM films.

FIG. 5A shows an MPROM film suitable as a "0" logical memory cell. This MPROM film contains an insulating medium 502a that blocks the flow of current. For example, it can be silicon oxide produced by PECVD. 0.02 ~ 2 μm, preferably 0.5 μm.

Figures 5B-5C show two types of MPROM films suitable for "Γ logic". It contains a quasi-conducting film. The quasi-conducting film has a non-linear resistance characteristic: a) it is in a low resistance state at a read voltage; b) when Its resistance increases significantly when subjected to a voltage smaller than the read voltage or in the direction opposite to the read voltage. Figure 7 and Figure 8 will explain this in detail.

Figure 5B shows a quasi-conducting film 502b used as "Γ logic". It contains amorphous silicon, with a thickness of 5-500nm, preferably 100nm. Amorphous silicon can be generated by the following methods, such as: sputtering, light emission Discharge method. If the address line consists of a refractory metal, that is, it can withstand a higher temperature heat treatment, then polysilicon can be used as a quasi-conduction film. The amorphous silicon film can be undoped or doped. Because amorphous silicon has an exponential volt-ampere characteristic curve, in general, it can meet the requirements of the aligning film volt-ampere characteristic curve proposed in the above discussion. On the other hand, protective ceramics Materials, especially protective oxides, also have an exponential volt-ampere characteristic curve, so they can also be used as quasi-conducting film 502b. Here, a protective ceramic material refers to a ceramic material with a Pilling-Bedworth ratio greater than 1 (/ Shackelford, "Introduction to Materials Science for Engineers", Second Edition, pages 609-610, 1988). Some examples of protective ceramic materials include Be, Cu, AI, Cr, Mn, The oxides of Fe, Co, Pd, Pb, Ce, Sc, Zn, Zr, La, Y, Nb, Rh and Pt. Protective ceramic materials t can often be formed by the following methods: 1. Deposition method, for example, CVD, Sputtering; 2. Generation method. For example, thermal oxidation method, plasma oxidation method, anodic oxidation method, etc. The thickness of the protective ceramic material is between 2 ~ 200nm, preferably 10nm. Others can be used for quasi-conduction The material of the film 502b includes amorphous germanium, carbon, silicon carbide, and the like.

FIG. 5C shows another quasi-conduction film 502b as a "1" logic memory cell. It is made of an amorphous silicon pn junction diode. If the address line is a refractory metal, a polysilicon pn junction diode can be used. The thickness of the p-layer 502bb and the n-layer 502ba is between 20 and 300 nm, preferably 60 nm. The resistance difference between the forward and reverse directions of the pn junction is extremely large. Therefore, the pn junction diode can meet the requirements of a quasi-conduction film. Conditions. Accordingly, it can be used as a "1" logical store. Besides the pn junction diode, the pin junction can also be used as a quasi-conduction film 502b. Figures 7 and 8 discuss the benefits of using a pn junction or a pin junction in more detail.

Figures 6A ~ 6E show the structure of several 3D-MPROM memory cells. Figure 6A is suitable for "0" logic, and Figures 6B-6E are suitable for "1" logic or "0" logic, preferably "Γ" logic.

Figure 6A shows a cross-sectional view of a memory cell. This memory cell is suitable for "0" logic, and accordingly, the MPROM film 502 is a barrier film 502a. This barrier film may be an extension of the field region 504. It can be made of a thick insulating material. Because of the barrier film, no current passes between the top electrode 501 and the bottom electrode 503. Therefore, high resistance is exhibited between the top electrode 501 and the bottom electrode 503.

Figures 6B ~ 6E show cross-sectional views of four other 3D-MPROM memory cells. They have a similar structure to metal-to-metal antifuse elements. A channel hole 505 is formed in the field region 504, and then the MPROM film 502 is formed inside, below or above the channel hole 505. According to the logic state of this memory cell, the MPROM film can be a blocking film representing "0" logic or a quasi-conduction film of "Γ logic."

Figure 6B shows a cross-sectional view of a 3D-MPROM memory cell. Here, the MPROM film 502 is formed in the channel hole 505. The process of manufacturing this memory cell is as follows: Firstly, a bottom electrode 503 is formed, then a field film 504 is deposited, and the field film 504 is etched to form a channel hole 505. After that, an MPROM film 502 and a top electrode 501 are sequentially formed in the channel. Inside the hole 505, the top electrode 501 and the MPROM film 502 are finally etched and formed.

Figure 6C shows a cross-sectional view of another 3D-MPROM memory cell. Here, the MPROM film 502 is formed on the channel hole 505. The process of manufacturing this memory cell is as follows: First, a bottom electrode 503, a deposition field region 504, a channel hole 505 are etched, and then the channel hole 505 is filled with a hole plug 506 made of tungsten, for example, and tungsten and the surrounding field region 504 material is polished, and finally the MPROM film 502 and the top electrode 501 are deposited and etched.

Fig. 6D shows a cross-sectional view of another 3D-MPROM memory cell. Here The MPROM film 502 is formed under the channel hole 505. The process of manufacturing this memory cell is as follows: First, a bottom electrode 503 and an MPROM film 502 are formed, then a field film 504 is deposited, and a channel hole 505 is etched. After the passage hole 505 is formed, a part of the upper surface of the MPROM film 502 is exposed. Finally, a top electrode film is deposited and the top electrode 501 is etched.

Figure 6E shows a cross-sectional view of another 3D-MPROM memory cell. The difference between this memory cell and the memory cell in FIG. 6D is that a top buffer film 508 is formed between the MPROM film 502 and the top electrode 501. This top buffer film 508 contains a conductor, for example, a thickness between 50-500 nm, and preferably 100 nm tungsten. The function of the top buffer film is to prevent the MPROM film 502 from being over-etched when the channel hole 505 is opened. For the various structural changes of this MPROM memory cell and their manufacturing steps, please refer to the anti-melting in Zhang Guobiao's US Patent No. 5,831,325 (November 3, 1998, "Antifuse structures with improved manufacturability") Description of silk element structure.

Figure 7 shows a memory cell array in its most difficult to read state. At this time, the memory cell to be read is 600aa, which is in the "0" logic state, and all other memory cells are in the "Γ" logic state. As an example, when reading, the voltage on the word line 400a rises to V _R / 2 The voltage on the bit line 500a drops to -V _R / 2, and all other address lines are floating. Figure 8 shows the characteristic curve of the ROM with "0" logic state and the ROM with "Γ" logic state. For "0" logic and "Γ logic memory cells, there is a non-linear relationship between current and voltage, and the reverse current is smaller or approximately equal than the forward current. The benefits of this volt-ampere characteristic are discussed in detail below. .

When reading memory cell 600aa ("0" logic), the voltage on word line 400a is VR / 2, and the voltage on bit line 500a is -V _R / 2. Therefore, the current through memory cell 600aa is applied to word line 400a. The contribution of the current is

l600aa ⁼ I "0" $ series (VR)

There are other currents on word line 400a, which come from other lines, such as 600ab → 600bb → 600ba. If a single amorphous silicon film is used as the quasi-conduction film 502b, then its reverse volt-ampere characteristic curve and forward volt-ampere characteristic curve are similar Like. In this case, the voltage drop across each "Γ logical memory cell, such as 600ab, 600bb, 600ba, is about 1/3 of the read voltage. Therefore, the leakage current through the line 600ab ^→ 600bb → 600ba is about I series ( V _R / 3). Because there are n X n memory cells in this storage layer, in the most difficult to read case, there are w leakage lines like 600ab → 600bb → 600ba. Therefore, in the most difficult to read case, in Other currents on word line 400a are approximately

I Other I "V $ (VR / 3) X n.

In general, the current on word line 400a in the "0" logic is

I -0- $ series word line ^¾ I600aa ⁺ I others = 1-(Γ a series (VR) + I 'r series (VR / 3) X rt. In another most difficult case, "Γ logical Word line current is

I -1 "it series word line ⁼ I -r series (VR) °

This most difficult to read scenario means that the memory cells we are interested in are in the "logical state" and the remaining memory cells are in the "0" logic state. These memory cells in the "0" logic state contribute little to the word line current.

In order to distinguish between "0" logic and "Γ logic, we hope

I * r $ 辑字线> Ι * ο "$ 辑字线

which is

I -r _¾ (V _R )> I. _0. Series (V _R ) + I -r ^ (VR / 3) X n.

Generally speaking, I n series (V _R ) «I. _R series (V _R ), so as an estimate,-

I "Γ ^ (V _R )

n <(1)

I Ί '$ Series (VR / 3)

Since the storage capacity in a storage tier is " ² , equation (1) provides an estimate of the storage capacity in a storage tier.

According to equation (1), the size of the storage capacity depends on the nonlinear characteristics of the volt-ampere characteristic curve of the quasi-conduction film. If the quasi-conducting film has an exponential volt-ampere characteristic curve, the ROM can have a large capacity.

If the voltage applied to the quasi-conducting film and the reading voltage are in opposite directions, the quasi-conducting film Has a higher resistance (Figure 8), for example, amorphous silicon ρ-η junction diodes. For the "0" logic in the most difficult to read state, the current will be smaller. This is because for a leakage circuit like 600ab → 600bb → 600ba, the voltage on 600bb is a reverse voltage, so the leakage current is much smaller than I.r $ series (VR / 3). Accordingly, it can be much larger than the upper limit set by equation (1), that is, the storage capacity will be larger.

Figures 9A to 11 are descriptions of 3D-EPROM. The difference between 3D-EPROM and 3D-MPROM is that: all 3D-EPROM memory cells have the same structure, they are initially in the "0" logic state, or unprogrammed state; the user can selectively perform address programming To make it into a "Γ logic state. EPROM film contains a quasi-conduction film and an anti-fuse film. The quasi-conduction film and the" Γ logic quasi-conduction film in 3D-MPROM have similar structures and functions; On the one hand, the anti-fuse film has high resistance when unprogrammed, and becomes low resistance after programming. Figures 9A to 9C show some examples.

Fig. 9A shows an EPROM film 502c of a 3D-EPROM memory cell. It contains a quasi-conduction film 502cb and an antifuse film 502ca. This quasi-conduction film 502cb is similar to the quasi-conduction film used in 3D-MPROM, as shown in FIG. 5B. The anti-fuse film 502ca is made of amorphous silicon or protective ceramic. For example, the thickness of the anti-fuse film 502ca is between 3 and 100 nm, and preferably 10 nm of chromium oxide. FIG. 11 shows the volt-ampere characteristic curves of the quasi-conduction film 502cb, the anti-fuse film 502ca, and the unprogrammed EPROM film 502c. The anti-fuse film 502ca is programmed at an appropriate programming voltage Vpp and a programming current Ip. The proper V _PP and Ip are selected to avoid damage to the quasi-conduction film 502cb. After programming, the anti-fuse film 502ca is converted to a low resistance state. Accordingly, the volt-ampere characteristic curve of the EPROM film is similar to the volt-ampere characteristic curve of the quasi-conduction film 502cb. Therefore, the memory cell enters the "Γ logic state.

Fig. 9B shows another 3D-EPROM EPROM film 502c. Here the EPROM film 502c includes a pn junction diode 502cb and an anti-fuse film 502ca. This pn junction diode 502cb (ie, a quasi-conduction film) is similar to the pn junction diode shown in FIG. 5C. It is doped by a p-doped silicon region 502cbb and n The silicon region is composed of 502cba, and the thickness is between 50 and 500 nm, preferably 60 nm. The anti-fuse film 502ca may be formed under or above the quasi-conduction film. The 3D-EPROM operates similarly to the 3D-EPROM in Figure 9A, except that the pn-junction diode has more ideal conduction characteristics.

Figure 9C shows another 3D-EPROM EPROM film 502c. Here, an intermediate transition film 502cc is embedded between the quasi-conduction film 502 cb and the antifuse film 502ca. It is made of refractory metal, for example, tungsten with a thickness between 10ηπ and 2μιη. During the programming of the anti-fuse film 502ca, local Joule heat is generated. This Joule heat will increase the temperature of the anti-fuse film 502ca. After the intermediate transition film 502cc is added, it can prevent thermal damage from being caused by the alignment transition film 502cb. This memory cell is programmed and read similar to the memory cells in Figures 9A and 9B.

Except that the quasi-conducting film 502b in FIGS. 6A-6E is replaced with the EPROM film 502c, the memory cells of 3D-EPROM can use the structure of FIGS. 6A-6E. For the EPROM film in Fig. 9C, Fig. 10A and Fig. 10B show other corresponding EPROM memory cell structures. For those skilled in the art, the positions of the quasi-conducting film 502cb and the anti-fuse film 502ca in FIG. 10A and FIG. 10B are interchangeable.

Figure 10A shows a 3D-EPROM memory cell. It has a bottom electrode 503, a quasi-conduction film 502cb, an intermediate transition film 502cc, an antifuse film 502ca, and a top electrode 501. Its manufacturing steps include: depositing and etching a bottom electrode 503 and a quasi-conducting film 502cb; depositing an insulating dielectric film 504; etching the insulating dielectric film 504 to form a window 505 to expose a portion of the quasi-conducting film 502cb; filling in the middle of the window 505 The intermediate transition film 502cc, and finally an antifuse film 502ca and a top electrode 501 are formed. Figure 10B shows another 3D-EPROM memory cell. The manufacturing steps of this memory cell are: depositing a bottom electrode 503, a quasi-conduction film 502cb, and an intermediate transition film 502cc; etching the intermediate transition film 502cc and a quasi-conduction film 502cb; etching the bottom electrode 503; depositing a field region dielectric film 504; The field region dielectric film 504 is etched to form a via hole 505 to expose a portion of the intermediate transition film 502cc; finally, an antifuse film 502ca and a top electrode 501 are deposited and etched. About this EPROM memory cell in FIG. 10B Various structural changes and their manufacturing steps, please refer to Zhang Guobiao ’s US patent

5,831,325 (November 3, 1998, "Antifuse structures with improved manufacturability") describes the antifuse element structure.

Figures 12A-12C show top views of several layouts in a 3D-ROM storage layer. In these layouts, the word lines 450a to 450d are in the X direction, and the bit lines 470a to 470c are in the Y direction. The contact channel holes 460a to 460d provide a connection between the word line and the transistor on the substrate.

Figure 12A shows the first layout, where all the contact channel holes 460a ~ 460d fall on a straight line. Figure 12B shows the second layout, where the contact channel holes are divided into two groups: Group A 460a and 460c; Group B 460b and 460d. The contact channel holes of group B are at a distance from the contact channel holes of group A, so all the contact channel holes 460a ~ 460d fall on two straight lines. Because the contact channel holes become relatively sparse, the design of the decoder can be made simpler. Figure 12C shows the third layout, and the contact channel holes are also divided into two groups: Group C 460a and 460c; Group D 460b and 460d. The contact channel holes of group C and group D are placed at both ends of the word line, so the design of the site selector becomes simpler.

Figure 13 shows a sectional view of a 3D-ROM memory. Here is a 3D-MPROM structure as an example. The process of manufacturing this memory includes: first forming a transistor 4 on a semiconductor substrate 10, and then forming a metallized interconnect 6 on the transistor 4. The metallized interconnect 6 preferably uses a highly conductive material such as aluminum (A1), copper (Cu) and so on. After that, an insulating dielectric film 20 is formed on the conventional circuit layer 000. In this embodiment, the transistors 4 are MOS, which includes a gate 1, a diffusion region 3 (source / drain), and are isolated from each other by a field region 5. In the above embodiment, only one layer of metallized interconnection line 6 is shown. In fact, the prior art allows the use of multiple layers of metallized interconnection lines. The transistor 4 and the metallization interconnection 6 constitute a conventional circuit layer 000. It can have functions such as address selection / reading, storage, and central processing unit. Those skilled in the art should know that these transistors 4 and metallized interconnects 6 can be manufactured by standard semiconductor process flow. The above-mentioned insulating dielectric film 20 may be silicon oxide, or some other more advanced dielectric systems. These more advanced media systems can fill gaps more successfully. Absolutely The edge dielectric film 20 may be planarized using a method such as CMP. Thereafter, the contact via hole 101a and the interlayer connection via port 201a3 are formed by a method such as RIE. A conductor is formed on the planarized surface, and then a first word line 101 is formed by pattern conversion, and a base 201a2 is also formed. The word line 101 may contain a highly conductive metal, such as aluminum or copper. Another insulating film 30 is formed on the word line 101 and is planarized. At this time, the digital information is converted to the insulating film 30 by graphic conversion. If "0" logic and "Γ logic" are to be generated at addresses 123 and 121, respectively, the mask patterns on 123 and 121 should be opaque and transparent, respectively. Therefore, only the resist film on 121 will be removed after exposure. Via holes are formed by RIE, and a part of the word line 101 is exposed. Next, a quasi-conduction film 121 and bit lines 111 and 112 are formed. Here After that, another insulating film 40 is formed on the bit lines 111 and 112, which can be planarized by a method such as CMP, and provides a flat foundation for the second memory layer 200.

The second storage layer 200 can be formed by a similar method, but an additional step is needed to form the interlayer connection channel opening 201al. 201al provides a connection between the word line 201 on the storage layer 200 and the base 201a2 on the storage layer 100. Therefore, the second storage layer 200 is electrically connected to the substrate 10 through the contact via hole 201a. After the second storage layer was generated, the wafer surface was continued flattened using CMP polishing technology. Repeat the above steps to make a multilayer 3D-ROM.

The above description is based on the storage cells in FIGS. 6A and 6B as examples. Those skilled in the art should understand the above process steps and structures. The storage cells in FIGS. 6C to 6E can also be used. For the sake of clarity, the details of the conventional circuit layer 000 will not be drawn in the following figures, but only "represented by the substrate 10 containing a transistor".

Figure 14 shows a cross-sectional view of another 3D-ROM memory. Taking a 3D-MPROM as an example, it can be seen from Fig. 2 that the X and Y positioners occupy a certain area. Accordingly, the distance between the contact points 131 and 231 must exceed a certain value. In order to maintain the storage capacity of the 3D-ROM, at least one wiring layer 109b may be added between the substrate 10 and the first storage layer 100. This wiring layer 109b stores The contact point 131 on the reservoir 100 is moved away from the contact point 231 on the storage layer 200. Therefore, more chip area can be saved. Accordingly, the storage capacity can also be increased.

Figures 15A ~ 15B show cross-sectional views of another 3D-ROM memory. Here, by connecting the address selection lines on different layers together, the number of contact points between the address lines and the substrate 10 can be reduced. When the number of contact points is reduced, the complexity of the site selector is reduced accordingly. Accordingly, the manufacturability of 3D-ROM is also improved. Using the method in Fig. 13 and Fig. 14, a 3D-ROM of I x m x n has I χ (m + n) contact points. But for a memory, the minimum number of contact points can be 2 x. For example, a 4 x 3 x 3 3D-ROM can only use 6 word line contact points and 6 bit line contact points.

FIG. 15A shows a cross-sectional view of the 3D-ROM memory perpendicular to the bit lines 482a to 482d. There are four storage layers 500a ~ 500d in this 3D-ROM. Word lines 480a to 480d are divided into two groups: Group A 480a and 480b; Group B 480c and 480d. The word lines in each group are connected together, and a contact channel hole to the substrate 10 is commonly used. For example, the word lines 480b and 480a are connected together through a metal plug 490b, and then connected to the substrate 10 through a contact channel hole 490a. Similarly, the word lines 480d and 480c are connected together through a metal plug 490d, and then connected to the substrate 10 through a contact channel hole 490c. FIG. 15B shows a cross-sectional view of the 3D-ROM memory perpendicular to the word lines 480a to 480d. The bit lines 482a-482d are divided into two groups:. Group C 482a and 482c; Group D 482b and 482d. The bit lines in each group are connected together and collectively use a contact via hole to the substrate 10. For example, the bit lines 482c and 482a are connected together through a metal plug 492c, and then connected to the substrate 10 through a contact channel hole 492a. Similarly, the bit lines 482d and 482b are connected together through a metal plug 492d, and then connected to the substrate 10 through a contact channel hole 492b. In general, the number of contact points of the bit line and the word line with the substrate 10 can be reduced by using this method.

Figures 13 to 15B use 3D-MPROM as an example to describe the structure of 3D-MPROM. These structures are also applicable to 3D-EPROM. The only difference is that for all memory cells of the 3D-EPROM, a window is etched and an EPROM film is formed; The EPROM film contains a quasi-conduction film and an anti-fuse film instead of a quasi-conduction film like 3D-MPROM. In addition, all manufacturing process steps are applicable.

Because 3D-ROM memory has a huge storage capacity, it can be applied in many fields. For example, today computers use most of their hard disk space to store software, and these software are rarely changed, so many hard disk resources are wasted. Using CD-ROM can partially alleviate this problem, but CD-ROM read time is very long. 3D-ROM memory has a large storage capacity and fast read time, so it is an ideal device for storing software. A computer that uses 3D-ROM to store software can relax the requirements for hard disk capacity. When 3D-ROM memory is used as the storage element of computer software, a separate 3D-ROM memory chip can be used or the 3D-ROM can be integrated on the central processing unit (€ 11). Another application of 3D-ROM memory is sensitive cards, also called security. ^ Min—The card can store a large amount of personal information, and it can replace ID cards, telephone magnetic cards, credit cards, etc. in the near future. Some information in the smart card needs to be retained permanently, while other information needs to be replaced at any time. Therefore, the MPROM, EPROM and other non-volatile memories of the present invention, such as E ² PROM, can be integrated into a single 3D-ROM chip. And use it as a sensitive card, for example, E ² PROM and the addresser of the present invention can be generated on a semiconductor substrate, and then the MPROM and EPROM of the present invention can be generated on them. Because the MPROM and EPROM of the present invention are low in cost and high in integration, the sensitive card that integrates E ² PROM, MPROM and EPROM in a three-dimensional form _: their markets will be discovered in the near future.

Although the above description specifically describes some examples of the present invention, those skilled in the art should understand that the form and details of the present invention can be modified without departing from the spirit and scope of the present invention. For example, in the above description, The description of each embodiment is based on positive logic, and those skilled in the art know that if the "0" logic and "Γ logic" are interchanged, the present invention can also be used for negative logic. EPROM in the present invention It can also be written by the user multiple times, such as using Chakogenide glass as the EPROM film material. At the same time, the three-dimensional memory of the present invention is not limited to using binary logic. It can also use multi-ary logic such as ternary and quaternary, that is, That is, a memory cell can represent one of multiple digital states. Accordingly, the invention should not be limited in any way except in accordance with the spirit of the appended claims.

Claims

Rights request

1. A three-dimensional memory containing at least one storage layer, comprising at least: a substrate including a plurality of transistors and a plurality of metallization interconnection lines coupling at least part of the transistors to each other; and covering at least part of the transistors and at least part of the transistors A first insulating dielectric film of the metal interconnection line; a plurality of first interlayer connection channel openings passing through at least part of the first insulating dielectric film; and a first storage layer formed on the first insulating dielectric film The first storage layer includes a plurality of first memory cells and a plurality of first address selection lines containing a metal material.

2. The three-dimensional memory according to claim 1, wherein the first insulating dielectric film is planarized.

3. The three-dimensional memory according to claim 1, further comprising: a second insulating dielectric film covering at least part of the first storage layer; and a plurality of first insulating dielectric films passing through at least part of the second insulating dielectric film. An inter-layer connection channel opening; and a second storage layer formed on the second insulating dielectric film, the second storage layer containing a plurality of second memory cells and a plurality of second address selection lines containing a metal material.

The three-dimensional memory according to claim 3, wherein the second insulating dielectric film is planarized.

5. The three-dimensional memory according to claim 1, wherein: at least one memory cell is a read-only memory cell.

6. The three-dimensional memory according to claim 5, wherein the read-only memory cell has: a first electrode containing a metal material and coupled to an address selection line; and a first electrode containing a metal material coupled to another address selection line A second electrode; and a quasi-conduction film sandwiched between the first electrode and the second electrode.

7. The three-dimensional memory according to claim 6, wherein at least one of said address selection lines contains a high conductivity material.

8. The three-dimensional memory according to claim 6, wherein at least one of the electrodes includes a barrier film.

9. The three-dimensional memory according to claim 6, wherein the quasi-conduction film is made of a semiconductor material.

10. The three-dimensional memory according to claim 6, wherein when the voltage direction on the memory cell is opposite to the direction of the read voltage, the quasi-conduction film has a higher resistance.

11. The read-only memory cell according to claim 10, wherein the quasi-conduction film comprises a first semiconductor film and a second semiconductor film, wherein the doping type of the first semiconductor film and the second semiconductor film in contrast.

12. The three-dimensional memory according to claim 6, wherein the quasi-conduction film has a non-single crystal structure.

13. The three-dimensional memory according to claim 6, further comprising: an insulating field region and a via hole passing through the insulating field region on the second electrode; and the quasi-conducting film is formed on the second electrode. The field region and the vicinity of the via hole; the first electrode covers at least part of the quasi-conduction film.

14. The three-dimensional memory according to claim 13, characterized in that: at least part of the quasi-conduction film is in the channel hole and covers at least part of the field region.

15. The three-dimensional memory according to claim 13, wherein: at least part of the quasi-conduction film is above the channel hole and covers at least part of the field region.

16. The three-dimensional memory according to claim 13, characterized in that: at least a part of the quasi-conduction film is below the passage hole and covers at least a part of the second electrode.

17. The three-dimensional memory according to claim 16, wherein: a top buffer film is interposed between at least part of the quasi-conduction film and the channel hole.

18. The three-dimensional memory according to claim 6, further comprising: an anti-fuse film formed between the first electrode and the second electrode.

The three-dimensional memory according to claim 18, further comprising: an intermediate transition film formed between the antifuse film and the quasi-conduction film, the intermediate transition film containing a metal material.

20. The three-dimensional memory according to claim 18, wherein: the anti-fuse The film contains non-single-crystal silicon.

The three-dimensional memory according to claim 18, wherein the anti-fuse film contains a protective ceramic material.

22. The three-dimensional memory according to claim 18, wherein: the second electrode has an insulating field region and a via hole passing through the field region; the antifuse film and the standard At least a part of a layer of the conductive film is below the channel hole, and at least a part of the other layer of the film is above the channel hole.

23. The three-dimensional memory according to claim 18, wherein: the second electrode has an insulating field region and a via hole passing through the field region; the anti-fuse film and the standard At least a part of the conductive film is under the channel hole and covers at least part of the second electrode, an intermediate transition film covers at least part of the anti-fuse film and the quasi-conduction film covers the second This layer of the electrode; another layer of the anti-fuse film and the quasi-conduction film is formed in the channel hole and covers at least part of the intermediate transition film.

24. The three-dimensional memory according to claim 1, wherein: the storage layer further comprises a plurality of word lines and a first contact channel hole; the substrate contains a plurality of first contact points; the word line The first contact channel hole is coupled to the substrate at a first contact point; the plurality of first contact points fall on at least one straight line.

25. The three-dimensional memory according to claim 24, wherein: the storage layer further comprises a plurality of bit lines and a second via hole; the substrate includes a plurality of second contact points; the word A line is coupled to the substrate at a second contact point through a second contact channel hole; the plurality of second contact points fall on at least one straight line.

26. The three-dimensional memory according to claim 1, further comprising a wiring layer.

27. The three-dimensional memory according to claim 3, wherein the first address selection line is connected to a second address selection line.

28. A method for manufacturing a three-dimensional device containing at least one storage layer, including at least the following steps: a) forming a plurality of transistors on a substrate and a plurality of metallization interconnection lines coupling at least part of the transistors to each other;

b) forming a first insulating dielectric film capable of covering at least part of said transistor and at least part of said metallized interconnection line;

c) forming at least one first interlayer connection channel opening through at least part of said first insulating dielectric film;

d) forming a first memory layer on the first insulating dielectric film, the first memory layer containing a plurality of first memory cells and a plurality of first address selection lines containing a metal material.

29. The method for manufacturing a three-dimensional memory according to claim 28, further comprising the following steps between steps b) and c):

b,) Planarize the first insulating dielectric film.

30. The method for manufacturing a three-dimensional memory according to claim 28, further comprising the following steps after step d):

e) forming a second insulating dielectric shield film capable of covering at least part of the first storage layer; f) forming at least one second interlayer connection channel opening passing through at least part of the second insulating dielectric film;

g) A second memory layer is formed on the second insulating dielectric film, and the second memory layer includes a plurality of second memory cells and a plurality of second address selection lines containing a metal material.

31. The method for manufacturing a three-dimensional memory according to claim 30, further comprising the following steps between steps e) and f).

e,) Planarize the second insulating dielectric film.

32. —Three-dimensional memory, comprising: a first storage layer, the first storage layer containing a plurality of first storage elements and a plurality of first address selection lines containing a metallic material; a layer covering at least part of the first storage layer An insulating dielectric film; a plurality of interlayer connection channel openings that pass through at least part of the insulating shield film; a second storage layer on the insulating dielectric film, the second storage layer containing a plurality of second storage elements And a plurality of second address selection lines containing a metallic material.

33. The three-dimensional memory according to claim 32, wherein: the insulating medium The plasma membrane is planar.

34. The three-dimensional memory according to claim 32, wherein at least one of said first memory cell and said second memory cell is a read-only memory cell.

35. The three-dimensional memory according to claim 34, wherein the read-only memory cell has: a first electrode containing a metal material and coupled to an address selection line; containing a metal material and coupled to another address selection line A second electrode; and a quasi-conduction film sandwiched between the first electrode and the second electrode.

36. The three-dimensional memory according to claim 35, wherein the read-only memory cell further comprises: an anti-fuse film between the first electrode and the second electrode.

37. A read-only memory cell, comprising: a first electrode containing a metal material; a second electrode containing a metal material; and a quasi-conduction film sandwiched between the first electrode and a second electrical element.

38. The read-only memory cell of claim 37, wherein: the first electrode is coupled to an address selection line; the second electrode is coupled to another address selection line; at least one of the address selection lines Contains a material with high conductivity; the highest temperature during the manufacturing of the read-only memory cell is less than 600 Γ; the read-only memory cell represents a single digit in binary logic.