WO2000058872A1 - Field programmable ball array - Google Patents

Field programmable ball array Download PDF

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Publication number
WO2000058872A1
WO2000058872A1 PCT/US2000/007375 US0007375W WO0058872A1 WO 2000058872 A1 WO2000058872 A1 WO 2000058872A1 US 0007375 W US0007375 W US 0007375W WO 0058872 A1 WO0058872 A1 WO 0058872A1
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WIPO (PCT)
Prior art keywords
integrated circuits
field programmable
ball array
cluster
spheres
Prior art date
Application number
PCT/US2000/007375
Other languages
French (fr)
Inventor
Sriram Govindarajan
Manish N. Patel
Akira Ishikawa
Original Assignee
Ball Semiconductor, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ball Semiconductor, Inc. filed Critical Ball Semiconductor, Inc.
Publication of WO2000058872A1 publication Critical patent/WO2000058872A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1017—Shape being a sphere
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the invention relates generally to integrated circuits, and more particularly, to a modified field programmable gate array made of one or more spherical shaped integrated circuits and method for creating same.
  • chips are formed from a flat surface semiconductor wafer.
  • the semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter fabrication facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages.
  • Each chip is assembled onto some type of lead frame or other package by connecting specific bond pads on the chip with specific leads of the lead frame. Once assembled, the chip can be connected to other devices (e.g., other chips or circuit boards) through the leads. For very tight, low-profile chips, a solder bump is placed on each bonding pad of the chip and then connected directly to the other device.
  • These technologies have several variances, such as flip chip technology, tape-automated bonding, ball-grid array and so forth.
  • FPGA field programmable gate array
  • FPGAs are a class of user-programmable devices that provide a large amount of logic and great flexibility.
  • FPGAs are extremely useful for producing small series of devices that cannot justify their own unique design and for rapid prototyping. Designs for the FPGAs can be created with schematic layout tools or a hardware description language model.
  • FPGAs There are four main categories of FPGAs currently available: symmetrical array, row-based, hierarchical programmable logic device, and sea-of-gates. In all of these FPGAs, the interconnections and how they are programmed vary. There are also four general technologies in use: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. Both the categories and technologies are well known by those of ordinary skill in the art.
  • the FPGA has three major configurable elements: configurable logic blocks (“CLBs”), input/output (“I/O”) blocks, and interconnects.
  • CLBs provide the functional elements for constructing digital logic.
  • the I/O blocks provide internal interfaces between internal signal lines as well as external interfaces to other devices.
  • the programmable interconnects provide internal routing paths to connect the inputs and outputs of the CLBs and I/O blocks onto appropriate networks. Customized configuration is established by programming internal static memory cells that determine the logic functions and internal connections implemented in the FPGA.
  • a designer first creates a schematic digital design with a design editor or a hardware description language to produce a netlist.
  • the netlist is converted into a bitstream file which configures the FPGA.
  • the bitstream file first maps the design onto the FPGA resources and then places or assigns logic blocks created in the mapping process in specific locations inside the FPGA.
  • the third step routes interconnect paths between the logic blocks and creates a logic cell array file ("LCA") for the bitstream file.
  • LCA logic cell array file
  • Design verification tests the design's logic and timing using input stimuli.
  • Various software packages provide verification/simulation tools to perform detailed characterization of the design. This detailed characterization may utilize both functional and timing simulations. Despite best efforts of design verification, design errors often occur in the final FPGA product.
  • bitstream file Once the bitstream file has been created and tested, a configuration process downloads the bitstream file into the FPGA.
  • the method for configuring the FPGA determines the type of bitstream file.
  • the FPGA can be configured by a programmable read-only memory ("PROM"). If the FPGA is used in a reconfigurable computing platform, the bitstream file may be converted into a high level language (i.e. C) function. Through this method, the FPGA can be configured from within an application program, as required.
  • logic circuitry requirements for FPGAs have increased dramatically. Despite advances in current fabrication technology, the size of a chip is still constrained to a limited degree. Therefore, complex logic circuitry cannot be realized without using multiple chips, such as multiple FPGAs.
  • the method chooses one or more spherical shaped integrated circuits from a library of circuits.
  • a spherical shaped integrated circuit (“sphere”) may be clustered with other spheres to form a single, large-scale device.
  • VLSI very large scale integrated
  • the spheres may be assembled onto very complicated surfaces.
  • the VLSI circuit may be constructed inside a pipe or on an uneven surface.
  • the distance between the spheres is greatly reduced, thereby enhancing the overall operation of the VLSI circuit.
  • the chosen integrated circuits are configured into a cluster and at least one of them is programmed.
  • the chosen integrated circuits may also be tested after being programmed.
  • the chosen integrated circuits are mounted onto a printed circuit board.
  • One advantage of the present invention is that each of the component spheres can be of different manufacturing technologies.
  • Another advantage of the present invention is that the cluster is scalable to accommodate different applications. Another advantage of the present invention is that the cluster can have very many
  • I/O pins as compared to a conventional FPGA.
  • Another advantage of the present invention is that groups of one or more spheres can be physically and/or electrically isolated from other spheres.
  • Another advantage of the present invention is that analog and digital components can be easily combined and configured on the same cluster.
  • Another advantage of the present invention is that the clustering arrangement facilitates programming and/or testing individual spheres or subsets of spheres.
  • Fig. 1 is a flow chart for implementing features of the present invention.
  • Figs. 2-5 are side elevations of examples of a field programmable ball array according to the present invention.
  • the reference numeral 10 refers, in general, to one embodiment of a method for creating one or more field programmable ball arrays ("FPBAs").
  • the method 10 begins with step 12 where one or more spherical shaped integrated circuits ("spheres") are chosen from a library of spheres.
  • the spheres may be of the type described in U.S. Patent Nos. 5,955,776 and 5,945,725, which are hereby incorporated by reference.
  • the library may consist of many different types of components, including conventional FPGA CLBs and interconnects as well as non-conventional components.
  • one library may contain the components listed in Table 1, below.
  • the chosen spheres are configured into a cluster.
  • the cluster is a flexible structure that can be arranged to accommodate the eventual circuit being implemented as well as the environment in which the circuit is to be implemented. Clusters are discussed in greater detail with respect to Figs. 2-5, below.
  • the programmable components are programmed.
  • the programming can be done using conventional techniques, such as described above.
  • the programing can be performed on the entire cluster of components.
  • the programming may be done before the cluster of components is created, or on individual components inside the cluster. Because the cluster of spheres is readily accessible to outside influences, a probe can be placed on a bonding pad of a single, specific component inside the cluster. In this way, programming signals can be provided to the specific component.
  • the programmed cluster may be tested.
  • the testing may use conventional techniques for testing the entire cluster, or may use individualized techniques for testing specific components in the cluster. For example, as discussed above with reference to step 16, some components may be tested before clustering, while other components may be tested separately using probes.
  • the reference numeral 50 refers to a cluster of spheres providing one example of a double-layer array FPBA.
  • the FPBA 50 includes twelve spheres 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72 and 74.
  • the spheres 52-74 include the functionality described in Table 2, below.
  • the "Ref. No.” column refers to the reference numerals used in Fig. 2, the "Part No.” column provides an exemplary part number from the library of components described in Table 1, and the Description column describes the function associated with that particular component.
  • the spheres 52-74 are interconnected through their respective solder bumps, collectively designated with the reference numeral 76. Not only do the solder bumps 76 interconnect the spheres 52-74, but they also allow a user to place a probe on an individual sphere for programming and/or testing. In addition, auxiliary solder bumps, such as bumps 76a, may be provided for the sole purpose of programming and/or testing.
  • the spheres 52, 54, 56, 70, 72, 74 are also physically and electrically connected to a plurality of bond pads, collectively designated with the reference numeral 78, on a printed circuit board 80.
  • the printed circuit board 80 may be of a conventional type and include a plurality of traces 82 and other components, such as a resistor 84 or a capacitor (not shown).
  • Figs. 3-5 provide additional examples of a FPBA.
  • Fig. 3 illustrates a single layer array FPBA 100 mounted to a circuit board 102.
  • Fig. 4 illustrates a double layer array FPBA 104 with an intermediate silicon substrate 106 and a printed circuit board 108.
  • the "sandwiched" layer 106 can provide direct connection between non-adjacent spheres by using appropriate routing, similar to a routing sphere (Part No. 16, Table 1).
  • Fig. 5 illustrates a non-uniform FPBA 110 mounted to a silicon substrate 112.
  • the FPBAs can then be used in different applications.
  • the printed circuit board 80 of Fig. 2 can be configured as a device that fits into a slot of a computer mother board.
  • the board 80 may include a plurality of pins (not shown) so that the FPBA 50 can be mounted as if it were a single chip.
  • each of the component spheres can be of different manufacturing technologies.
  • a .5 micron Bipolar/CMOS component can connect with a 1.2 micron CMOS component.
  • the cluster is scalable to accommodate different applications.
  • the cluster can have very many I/O pins, as compared to a conventional FPGA.
  • groups of one or more spheres can be physically and/or electrically isolated from other spheres.
  • one or more spheres may provide a ground power supply and can be used as an emf shield for other spheres.
  • analog and digital components can be easily combined and configured on the same cluster.
  • the clustering arrangement facilitates programming and/or testing individual spheres or subsets of spheres.

Abstract

A unique field programmable ball array ('FPBA') and method (10) for making the same is disclosed. The method first chooses one or more spherical shaped ICs from a library of circuits (12). The chosen ICs are then configured into a cluster (14) and mounted onto a PCB. One or more of the ICs are programmed (16) and tested (18). The FPBA serves as a unique field programmable gate array ('FPGA') with different components and interconnects.

Description

FIELD PROGRAMMABLE BALL ARRAY
Cross Reference to Related Application
This application claims the benefit of U.S. Patent Ser. No. 60/126,344 filed March 26, 1999.
Background of the Invention
The invention relates generally to integrated circuits, and more particularly, to a modified field programmable gate array made of one or more spherical shaped integrated circuits and method for creating same.
Conventional integrated circuits, or "chips," are formed from a flat surface semiconductor wafer. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter fabrication facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages.
Each chip is assembled onto some type of lead frame or other package by connecting specific bond pads on the chip with specific leads of the lead frame. Once assembled, the chip can be connected to other devices (e.g., other chips or circuit boards) through the leads. For very tight, low-profile chips, a solder bump is placed on each bonding pad of the chip and then connected directly to the other device. These technologies have several variances, such as flip chip technology, tape-automated bonding, ball-grid array and so forth.
One type of integrated circuit is a field programmable gate array ("FPGA"). Unlike conventional gate arrays, FPGAs are a class of user-programmable devices that provide a large amount of logic and great flexibility. Unlike application specific integrated circuits, FPGAs are extremely useful for producing small series of devices that cannot justify their own unique design and for rapid prototyping. Designs for the FPGAs can be created with schematic layout tools or a hardware description language model.
There are four main categories of FPGAs currently available: symmetrical array, row-based, hierarchical programmable logic device, and sea-of-gates. In all of these FPGAs, the interconnections and how they are programmed vary. There are also four general technologies in use: static RAM cells, anti-fuse, EPROM transistors, and EEPROM transistors. Both the categories and technologies are well known by those of ordinary skill in the art.
The FPGA has three major configurable elements: configurable logic blocks ("CLBs"), input/output ("I/O") blocks, and interconnects. The CLBs provide the functional elements for constructing digital logic. The I/O blocks provide internal interfaces between internal signal lines as well as external interfaces to other devices. The programmable interconnects provide internal routing paths to connect the inputs and outputs of the CLBs and I/O blocks onto appropriate networks. Customized configuration is established by programming internal static memory cells that determine the logic functions and internal connections implemented in the FPGA.
To use a FPGA in a particular application, a designer first creates a schematic digital design with a design editor or a hardware description language to produce a netlist. Next, in the design implementation stage, the netlist is converted into a bitstream file which configures the FPGA. The bitstream file first maps the design onto the FPGA resources and then places or assigns logic blocks created in the mapping process in specific locations inside the FPGA. The third step routes interconnect paths between the logic blocks and creates a logic cell array file ("LCA") for the bitstream file.
A common intermediate process is design verification. Design verification tests the design's logic and timing using input stimuli. Various software packages provide verification/simulation tools to perform detailed characterization of the design. This detailed characterization may utilize both functional and timing simulations. Despite best efforts of design verification, design errors often occur in the final FPGA product.
Once the bitstream file has been created and tested, a configuration process downloads the bitstream file into the FPGA. The method for configuring the FPGA determines the type of bitstream file. For example, the FPGA can be configured by a programmable read-only memory ("PROM"). If the FPGA is used in a reconfigurable computing platform, the bitstream file may be converted into a high level language (i.e. C) function. Through this method, the FPGA can be configured from within an application program, as required. As technology increases, logic circuitry requirements for FPGAs have increased dramatically. Despite advances in current fabrication technology, the size of a chip is still constrained to a limited degree. Therefore, complex logic circuitry cannot be realized without using multiple chips, such as multiple FPGAs. This results in more configuration resources and more I/O requirements for multiple FPGAs. In addition, complex algorithms have to be employed to partition the circuit to be laid out on multiple FPGAs. Furthermore, the available logic area provided by the FPGAs may not be the most beneficial for any given application.
Another problem with current FPGAs is that they only support digital logic, and cannot handle many analog circuit requirements.
Yet another problem with current FPGAs is that they are limited in their number of I/O pins.
Still another problem is that different applications require different amounts of logic. Therefore, certain FPGAs are suitable for some applications and are too big (too many circuits) or too small (too few circuits) for others.
Summary of the Invention In response to the above-described problems and difficulties, a technical advance is achieved by a unique field programmable ball array and method for making same. In one embodiment, the method chooses one or more spherical shaped integrated circuits from a library of circuits.
A spherical shaped integrated circuit ("sphere") may be clustered with other spheres to form a single, large-scale device. By clustering the spheres in different directions based on structural design, they form a very large scale integrated ("VLSI") circuit which may be assembled onto very complicated surfaces. For example, the VLSI circuit may be constructed inside a pipe or on an uneven surface. In addition, the distance between the spheres is greatly reduced, thereby enhancing the overall operation of the VLSI circuit.
The chosen integrated circuits are configured into a cluster and at least one of them is programmed. The chosen integrated circuits may also be tested after being programmed. In some embodiments, the chosen integrated circuits are mounted onto a printed circuit board. One advantage of the present invention is that each of the component spheres can be of different manufacturing technologies.
Another advantage of the present invention is that the cluster is scalable to accommodate different applications. Another advantage of the present invention is that the cluster can have very many
I/O pins, as compared to a conventional FPGA.
Another advantage of the present invention is that groups of one or more spheres can be physically and/or electrically isolated from other spheres.
Another advantage of the present invention is that analog and digital components can be easily combined and configured on the same cluster.
Another advantage of the present invention is that the clustering arrangement facilitates programming and/or testing individual spheres or subsets of spheres.
Additional advantages can be clearly seen by the attached drawings and the following description. Brief Description of the Drawings
Fig. 1 is a flow chart for implementing features of the present invention. Figs. 2-5 are side elevations of examples of a field programmable ball array according to the present invention.
Description of Embodiments Referring to Fig. 1, the reference numeral 10 refers, in general, to one embodiment of a method for creating one or more field programmable ball arrays ("FPBAs"). The method 10 begins with step 12 where one or more spherical shaped integrated circuits ("spheres") are chosen from a library of spheres. For the sake of example, the spheres may be of the type described in U.S. Patent Nos. 5,955,776 and 5,945,725, which are hereby incorporated by reference.
The library may consist of many different types of components, including conventional FPGA CLBs and interconnects as well as non-conventional components. For the sake of example, one library may contain the components listed in Table 1, below.
Figure imgf000007_0001
Table 1
At step 14, the chosen spheres are configured into a cluster. The cluster is a flexible structure that can be arranged to accommodate the eventual circuit being implemented as well as the environment in which the circuit is to be implemented. Clusters are discussed in greater detail with respect to Figs. 2-5, below.
At step 16, the programmable components are programmed. The programming can be done using conventional techniques, such as described above. In some embodiments, the programing can be performed on the entire cluster of components. In other embodiments, the programming may be done before the cluster of components is created, or on individual components inside the cluster. Because the cluster of spheres is readily accessible to outside influences, a probe can be placed on a bonding pad of a single, specific component inside the cluster. In this way, programming signals can be provided to the specific component.
At step 18, the programmed cluster may be tested. The testing may use conventional techniques for testing the entire cluster, or may use individualized techniques for testing specific components in the cluster. For example, as discussed above with reference to step 16, some components may be tested before clustering, while other components may be tested separately using probes.
Referring to Fig. 2, the reference numeral 50 refers to a cluster of spheres providing one example of a double-layer array FPBA. The FPBA 50 includes twelve spheres 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72 and 74. For the sake of example, the spheres 52-74 include the functionality described in Table 2, below. The "Ref. No." column refers to the reference numerals used in Fig. 2, the "Part No." column provides an exemplary part number from the library of components described in Table 1, and the Description column describes the function associated with that particular component.
Figure imgf000008_0001
Table 2 The spheres 52-74 are interconnected through their respective solder bumps, collectively designated with the reference numeral 76. Not only do the solder bumps 76 interconnect the spheres 52-74, but they also allow a user to place a probe on an individual sphere for programming and/or testing. In addition, auxiliary solder bumps, such as bumps 76a, may be provided for the sole purpose of programming and/or testing.
In the present example, the spheres 52, 54, 56, 70, 72, 74 are also physically and electrically connected to a plurality of bond pads, collectively designated with the reference numeral 78, on a printed circuit board 80. The printed circuit board 80 may be of a conventional type and include a plurality of traces 82 and other components, such as a resistor 84 or a capacitor (not shown).
Figs. 3-5 provide additional examples of a FPBA. Fig. 3 illustrates a single layer array FPBA 100 mounted to a circuit board 102. Fig. 4 illustrates a double layer array FPBA 104 with an intermediate silicon substrate 106 and a printed circuit board 108. The "sandwiched" layer 106 can provide direct connection between non-adjacent spheres by using appropriate routing, similar to a routing sphere (Part No. 16, Table 1). Fig. 5 illustrates a non-uniform FPBA 110 mounted to a silicon substrate 112.
Referring to all the figures, the FPBAs can then be used in different applications. For example, the printed circuit board 80 of Fig. 2 can be configured as a device that fits into a slot of a computer mother board. Alternatively, the board 80 may include a plurality of pins (not shown) so that the FPBA 50 can be mounted as if it were a single chip.
The present invention has many advantages. For one, each of the component spheres can be of different manufacturing technologies. For example, a .5 micron Bipolar/CMOS component can connect with a 1.2 micron CMOS component. Also, the cluster is scalable to accommodate different applications. Further, the cluster can have very many I/O pins, as compared to a conventional FPGA. Further still, groups of one or more spheres can be physically and/or electrically isolated from other spheres. For example, one or more spheres may provide a ground power supply and can be used as an emf shield for other spheres. Also, analog and digital components can be easily combined and configured on the same cluster. Further, the clustering arrangement facilitates programming and/or testing individual spheres or subsets of spheres. It should be clearly understood that various modifications, changes and substitutions are intended in the foregoing disclosure and in some instances some features of the invention will be employed without a corresponding use of other features. For example, individual spheres may be one-time programmable (e.g., burning a fuse) or repeatedly programmable (e.g., a memory array). Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.

Claims

WHAT IS CLAIMED IS:
1. A method for making a field programmable ball array, the method comprising the steps of: choosing a plurality of spherical shaped integrated circuits from a library; configuring the chosen integrated circuits into a cluster; and programming at least one of the integrated circuits.
2. The method of claim 1 further comprising the step of: testing the chosen integrated circuits after programming.
3. The method of claim 1 further comprising the step of: mounting the chosen integrated circuits onto a printed circuit board.
4. The method of claim 1 further comprising the step of: positioning a printed circuit board between at least two of the integrated circuits to interconnect electrical routing there between.
5. The method of claim 1 wherein the at least one integrated circuit is an internal component, and the step of programming utilizes probes to directly connect with the at least one integrated circuit.
6. The method of claim 1 further comprising the step of: individually testing at least one of the integrated circuits.
7. A field programmable ball array, comprising: a plurality of spherical shaped integrated circuits formed into a cluster, wherein at least one of the integrated circuits can be individually programmed through external means.
8. The field programmable ball array of claim 7 wherein the at least one of the integrated circuits can be tested after programming.
9. The field programmable ball array of claim 7 further comprising: means for mounting the integrated circuits onto a printed circuit board.
10. The field programmable ball array of claim 7 further comprising: a printed circuit board positioned between at least two of the integrated circuits to interconnect electrical routing there between.
11. The field programmable ball array of claim 7 wherein the at least one integrated circuit is an internal component.
12. The field programmable ball array of claim 7 wherein the at least two of the integrated circuits are created with different integrated circuit technologies.
13. The field programmable ball array of claim 7 wherein another one of the integrated circuits is non-programmable.
PCT/US2000/007375 1999-03-26 2000-03-20 Field programmable ball array WO2000058872A1 (en)

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US60/126,344 1999-03-26

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Cited By (1)

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US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5877943A (en) * 1998-03-26 1999-03-02 Ball Semiconductor, Inc. Clustering adapter for spherical shaped devices
US5955776A (en) * 1996-12-04 1999-09-21 Ball Semiconductor, Inc. Spherical shaped semiconductor integrated circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5955776A (en) * 1996-12-04 1999-09-21 Ball Semiconductor, Inc. Spherical shaped semiconductor integrated circuit
US5877943A (en) * 1998-03-26 1999-03-02 Ball Semiconductor, Inc. Clustering adapter for spherical shaped devices

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Title
TAKEDA: "Ball Semiconductor Technology and Its Application to MEMS", 13TH ANNUAL INT'L CONFERENCE ON MEMS, 23 January 2000 (2000-01-23) - 27 January 2000 (2000-01-27), pages 11 - 16, XP002928544 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1251560A1 (en) * 2000-08-28 2002-10-23 Dai Nippon Printing Co., Ltd. Cluster globular semiconductor device
EP1251560A4 (en) * 2000-08-28 2004-04-21 Dainippon Printing Co Ltd Cluster globular semiconductor device

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