WO2000064197A1 - Scalable multi-processor system for real time applications in communications engineering - Google Patents

Scalable multi-processor system for real time applications in communications engineering Download PDF

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Publication number
WO2000064197A1
WO2000064197A1 PCT/DE2000/001015 DE0001015W WO0064197A1 WO 2000064197 A1 WO2000064197 A1 WO 2000064197A1 DE 0001015 W DE0001015 W DE 0001015W WO 0064197 A1 WO0064197 A1 WO 0064197A1
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Prior art keywords
memory
processor
access
data
local bus
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PCT/DE2000/001015
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German (de)
French (fr)
Inventor
Günter Schwarz
Dirk Amandi
Franz Hechfellner
Robert Winter
Gebhard Oelmaier
Alfred Burger
Helmut Brazdrum
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Siemens Aktiengesellschaft
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Priority to DE10081049T priority Critical patent/DE10081049D2/en
Publication of WO2000064197A1 publication Critical patent/WO2000064197A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13091—CLI, identification of calling line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13092—Scanning of subscriber lines, monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103—Memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106—Microprocessor, CPU
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13107—Control equipment for a part of the connection, distributed control, co-processing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1329—Asynchronous transfer mode, ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13299—Bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Definitions

  • the subject of the application relates to an arrangement for data processing in real time, which can be flexibly adapted to changed tasks.
  • the processor receives the necessary data at the right time, by means of a pre-load of the data, controlled by the software-controlled processor MP, which is carried out by the support device in a controlled manner via the control interface COM, from the external memory (HOST memory) to the local memory a significant improvement in system performance is achieved (pipelining).
  • the processor also has direct access to the peripheral bus and thus to the external memory via the local bus in order to be able to load and save data directly in special cases.
  • the arrangement in accordance with the subject of the application relieves the processor of the performance of critical tasks by the support device.
  • the support device is able to carry out combined application-specific burst accesses to the external memory which are not covered by the processor functionality.
  • the processor base system is scalable, i.e. it can be parallelized n times to increase the data throughput.
  • connection data between the individual processor base systems can e.g. according to the connection number (parallel processing of different connections).
  • the subject of the application offers a scalable processor base system that supports the processor in data management and processing and is optimized for connection-oriented data streams, with which high-performance programmability of real-time-critical functions in telecommunications technology can be implemented.
  • FIG. 1 shows the architecture of a multi-processor system according to the application.
  • a plurality of basic processor systems PBSL.PBSn are connected via a peripheral bus PB to a central data processing memory HOST memory which has an external common memory.
  • the processor base systems PBSl..PBSn are connected to a receiving unit RI (for: Receive Interface) and a transmitting unit TI (for: Transmit Interface), which are connected to the physical layer PL (for: physical layer) of a switching system.
  • a processor base system PBSL.PBSn has a fast local bus LB which is equipped with a processor MP (for: microprocessor), a receive memory RM DP (for: receive memory dual port) with double access, a transmit memory TM DP (for: Transmit Memory Dual Port) with double access, a support device SU (for: Service Unit) and the peripheral bus PB.
  • the processor MP may be provided by a processor kernel of the type MIPS RISC, Power PC, ..., for example.
  • the processor can read and write access to the receive memory RM DP and the transmit memory TM DP can be done on one side by the processor and on the other side by the support device SU.
  • the support facility SU is on the processing of special tasks such.
  • the support device SU is connected to the processor via a control interface COM and the local bus LB and can execute and acknowledge proprietary commands from the processor. It is essentially a load / store of data that is built into the program sequence in such a way that the data is available in time in a FIFO (also in the dual port RAM) (preload, pipelining).
  • the receiving unit RI can store data via the support device SU in the receiving memory RM DP (dual port RAM) according to the FIFO principle. This ensures that sufficient processing data is always available to the processor and so it cannot "run empty". This principle is applied separately on the receive and transmit side, making use of the knowledge that both sides generally based on different connection data.
  • the local bus LB is a fast bus system for fast communication between processor receive / transmit memory (transient data) and processor service unit, connection to the peripheral bus PB for external communication.
  • the processor is the only master on the local bus, which prevents congestion, known as bus concentra- tions.
  • the support device SU is a hardware (hardware) unit (proprietary coprocessor) that is controlled by the processor via a control interface (COM) and provides performance-optimized standard functions, in particular burst load / store operations between peripherals and the receive / transmit memories RMDP / TMDP.
  • COM control interface
  • a pre-load of the data from the external memory (HOST memory) into the local memory controlled by the software-controlled processor MP achieves a significant improvement in the system performance.
  • the receive memory RMDP and the transmit memory TMDP are fast access memories for the transient (connection) data separated after incoming connection messages and connection messages to be sent.
  • the processor essentially works on these memories.
  • the peripheral bus is relieved.
  • the receiving unit RI, the transmitting unit TI and the peripheral bus PB are arranged in the periphery of the multi-processor system.
  • the receiving unit RI is used to connect external devices, eg switching network, physical layer.
  • a division device CR for: channel router
  • the assignment of the individual connections to the processor base systems is permanently configured.
  • the connection data may be assigned to the individual processor base systems in accordance with the connection name VPI / VCI (Virtual Path Identifier / Virtual Channel Identifier).
  • the sending unit TI sends the connection messages to the external devices in accordance with a send request procedure (polling of the control interfaces in the service units). It is generally only important that the
  • the transmission unit TI has a merging device CM (for: channel merger) for merging the data of the individual connections.
  • CM channel merger
  • the peripheral bus PB serves as an interface to the shared memories.
  • the shared memory contains e.g. the complete connection data and are managed by the HOST. Due to the large number of connected processor base systems, there is a risk of overload (bus contentions) at this interface.
  • the peripheral bus is relieved with the pre-load / store mechanism supported by the service unit and the holding of transient data in the local memories.
  • the multi-processor system according to the application may be implemented in system on chip (SoC) technology, in which several (RISC) processors are arranged as core goods in an ASIC,
  • SoC system on chip

Abstract

The invention relates to an arrangement for processing data in accordance with real time requirements which can be flexibly adapted to the modified tasks. According to the invention, a processor (MP) is interactively connected to each of the following by a local bus (LB): a first access part of a receive memory (RMDP) with dual access, a first access part of a transmit memory (TMDP) with dual access and a peripheral bus (PB). A support device (SU) is connected to the second access part of the receive memory, to the second access part of the transmit memory, to the local bus, to a receive unit (RI) and to a transmission unit (TI). The local bus and the support device are connected by the peripheral bus to a data processing device (HOST) with an external memory. The inventive arrangement has a scalable processor base system that supports the processor in data management and processing and that is optimised for connection-oriented data streams, in order to increase capacity. This ensures the excellent programmability of real time-critical functions in telecommunications technology.

Description

Beschreibungdescription
Skalierbares Multi-Prozessorsyste für Echtzeitanwendungen in der NachrichtentechnikScalable multi-processor system for real-time applications in telecommunications
Der Anmeldungsgegenstand bezieht sich auf eine Anordnung zur Datenverarbeitung in Echtzeitanforderung, die an geänderte Aufgaben flexibel anpaßbar ist.The subject of the application relates to an arrangement for data processing in real time, which can be flexibly adapted to changed tasks.
Anwendungen in der Nachrichtentechnik, wie z.B. in der Telekommunikationstechnik die Handhabung des Layers 1 und 2 des Signalisierungsprotokolls No. 7 (CCS7), stellen durch das Erfordernis der Echtzeitverarbeitung hohe Anforderungen an die Leistungsfähigkeit (Performance) der Verarbeitungslogik. Bis- her wurden die hohen Anforderungen durch Einsatz von hart verdrahteter Logik, beispielsweise durch ASIC's (Application Specific Integrated Circuit) erfüllt. Darüberhinaus ist eine Programmierbarkeit von Funktionen wünschenswert, um schnell Fehler beseitigen und flexibel auf Kundenwünsche reagieren zu können. Bisherige Multi/Single Prozessor Lösungen sind zwar programmierbar, genügen jedoch nicht den Anforderungen der Echtzeitverarbeitung.Applications in communications engineering, such as in telecommunications technology the handling of layers 1 and 2 of signaling protocol No. 7 (CCS7), place high demands on the performance of the processing logic due to the requirement of real-time processing. So far, the high requirements have been met using hard-wired logic, for example ASIC's (Application Specific Integrated Circuit). In addition, it is desirable to be able to program functions so that errors can be eliminated quickly and flexibly reacted to customer requests. Previous multi / single processor solutions are programmable, but do not meet the requirements of real-time processing.
Probeprogrammierungen im Rahmen einer Evaluierung ergeben, dass eine Standardlösung mit einem Prozessor und einem gemeinsamen Speicher (shared memory) bei weitem nicht den Performance Anforderungen genügt. Durch die Vielzahl von Komponenten, die bei SoC (System on Chip) Designs üblich sind, kommt es im allgemeinen zu längeren Wartezeiten am shared me- mory, da physikalisch längere Wartezeiten am externen Speicher entstehen und im weiteren mit Zugriffsbelegungen (bus contentions) durch andere Komponenten zu rechnen ist. Auch wenn die gemittelte Zugriffsrate akzeptabel ist, so können aus Prozessorsicht die Wartezeiten nicht akzeptiert werden, da sie zu Stillstand des Programmablaufs führen und somit wertvolle MIPS (Million Instructions Per Second) Performance verschenken, d.h. der Prozessor läuft zeitweise leer. Dem Anmeldungsgegenstand liegt das Problem zugrunde, eine Anordnung für die Bearbeitung von Daten mit hohem Datendurchsatz zur Verfügung zu stellen, die an geänderte Aufgabenstel- lungen flexibel anpaßbar ist.Trial programming as part of an evaluation shows that a standard solution with a processor and a shared memory is far from meeting the performance requirements. Due to the large number of components that are common in SoC (System on Chip) designs, there are generally longer waiting times at the shared memory, since physically longer waiting times occur at the external memory and furthermore with access assignments (bus contentions) by others Components is to be expected. Even if the averaged access rate is acceptable, the waiting times cannot be accepted from the processor's point of view, since they lead to the program sequence being stopped and thus giving away valuable MIPS (Million Instructions Per Second) performance, ie the processor is temporarily idle. The object of the application is based on the problem of providing an arrangement for processing data with a high data throughput, which can be flexibly adapted to changed tasks.
Das Problem wird durch die Merkmale des Anspruchs 1 gelöst.The problem is solved by the features of claim 1.
Die Anordnung gemäß dem Anmeldungsgegenstand lastet durch die vom Prozessor gesteuerte Unterstützungseinrichtung für dasThe arrangement according to the subject of the application rests on the processor-controlled support device for the
Daten Laden und Speichern in die Empfangs- und Sendespeicher den Peripheren Bus aus, womit lange Wartezeiten (Latenzzeiten) , die beim Zugriff auf den externen Speicher (shared memory) entstehen, für den Prozessor nicht auftreten, da er ei- nen schnellen Zugriff auf die lokalen Speicher hat. Durch ein vom Software-gesteuerten Prozessor MP gesteuertes Pre-Load der Daten, welches gesteuert über das Control interface COM von der Unterstützungseinrichtung ausgeführt wird, vom externen Speicher (HOST Speicher) in die lokalen Speicher erhält der Prozessor die erforderlichen Daten zur richtigen Zeit, womit eine wesentliche Verbesserung der Systemperformance erreicht wird (pipelining) . Über den lokalen Bus hat der Prozessor zusätzlich einen direkten Zugriff auf den Peripheren Bus und damit zum externen Speicher, um in besonderen Fällen auch Daten direkt laden und speichern zu können.Data is loaded and stored in the receive and transmit memories from the peripheral bus, so long waiting times (latency times) that arise when accessing the external memory (shared memory) do not occur for the processor, since it provides quick access to the has local storage. The processor receives the necessary data at the right time, by means of a pre-load of the data, controlled by the software-controlled processor MP, which is carried out by the support device in a controlled manner via the control interface COM, from the external memory (HOST memory) to the local memory a significant improvement in system performance is achieved (pipelining). The processor also has direct access to the peripheral bus and thus to the external memory via the local bus in order to be able to load and save data directly in special cases.
Die Anordnung gemäß dem Anmeldungsgegenstand entlastet durch die Unterstützungseinrichtung den Prozessor bei Performance kritischen Aufgaben. Insbesondere ist die Unterstützungsein- richtung in der Lage, kombinierte anwendungsspezifische Burst Zugriffe auf den externen Speicher auszuführen, die von der Prozessorfunktionalität nicht abgedeckt werden. Die Bearbeitung von Hardware-nahen Standardfunktionen, wie z. B. Bildung von Checksummen, etc. , in der Unterstützungseinrichtung, welche über das Control interface COM vom Prozessor gesteuert wird, entlastet den Prozessor von diesen Aufgaben, bei denen er zumal eine schlechte Performance aufweisen würde, womit die Leistungsfähigkeit der Anordnung weiter gesteigert ist.The arrangement in accordance with the subject of the application relieves the processor of the performance of critical tasks by the support device. In particular, the support device is able to carry out combined application-specific burst accesses to the external memory which are not covered by the processor functionality. The processing of hardware-related standard functions, such as B. formation of checksums, etc., in the support device, which is controlled by the processor via the control interface COM, relieves the processor of these tasks in which especially since it would have poor performance, which further increases the performance of the arrangement.
Das Prozessor Basissystem ist skalierbar, d.h. es ist zur Er- höhung des Datendurchsatzes n-fach parallelisierbar .The processor base system is scalable, i.e. it can be parallelized n times to increase the data throughput.
Die Aufteilung der Verbindungsdaten auf die einzelnen Prozessor Basissysteme kann z.B. entsprechend der Verbindungsnummer gemacht werden (paralleles Verarbeiten verschiedener Verbin- düngen) .The division of the connection data between the individual processor base systems can e.g. according to the connection number (parallel processing of different connections).
Der Anmeldungsgegenstand bietet ein skalierbares Prozessor Basissystem, das den Prozessor in der Datenverwaltung und Bearbeitung unterstützt und auf verbindungs-orientierte Daten- ströme hin optimiert ist, womit eine performante Programmierbarkeit von echtzeitkritischen Funktionen in der Telekommunikationstechnik realisierbar ist.The subject of the application offers a scalable processor base system that supports the processor in data management and processing and is optimized for connection-oriented data streams, with which high-performance programmability of real-time-critical functions in telecommunications technology can be implemented.
Vorteilhafte Weiterbildungen des Anmeldungsgegenstandes sind in den Unteransprüchen angegeben.Advantageous further developments of the subject of the application are specified in the subclaims.
Der Anmeldungsgegenstand wird im folgenden als Ausführungsbeispiel in einem zum Verständnis erforderlichen Umfang anhand einer Figur näher erläutert. Dabei zeigt: Fig 1 die Architektur eines anmeldungsgemäßen Multi- Prozessorsystems .The subject of the application is explained in more detail below as an exemplary embodiment to the extent necessary for understanding with the aid of a figure. 1 shows the architecture of a multi-processor system according to the application.
Bei dem in Fig 1 dargestellten Multi-Prozessorsystem stehen mehrere Prozessor-Basissysteme PBSL.PBSn über einen Periphe- ren Bus PB mit einem zentralen Datenverarbeitungsspeicher HOST Speicher, die einen externen gemeinsamen Speicher aufweist, in Verbindung. Die Prozessor-Basissysteme PBSl..PBSn sind mit einer Empfangseinheit RI (für: Receive Interface) und einer Sendeeinheit TI (für: Transmit Interface) verbun- den, die mit der physikalischen Schicht PL (für: physikal layer) eines Vermittlungssystems verbunden sind. Ein Prozessor-Basissystem PBSL.PBSn weist einen schnellen lokalen Bus LB auf, der mit einem Prozessor MP (für: Mikro Prozessor), einem Empfangsspeicher RM DP (für: Receive Memory Dual Port) mit zweifachem Zugang, einem Sendespeicher TM DP (für: Transmit Memory Dual Port) mit zweifachem Zugang, einem Unterstützungseinrichtung SU (für: Service Unit) und dem Peripheren Bus PB verbunden ist. Der Prozessor MP mag durch einen Prozessor Kernel beispielsweise vom Typ MIPS RISC, Power PC, ...gegeben sein. Auf den Empfangsspeicher RM DP und den Sendespeicher TM DP kann jeweils auf der einen Seite vom Prozessor und auf der anderen Seite von der Unterstützungseinrichtung SU lesend/schreibend zugegeriffen werden. Die Unterstützungseinrichtung SU ist auf die Abarbeitung besonderer Aufgaben, wie z. B. performance-optimierte Standardfunktio- nen, insbesondere Burst Load/Store Operationen, Bildung von Checksummen, ausgelegt und kann durch einen proprietären Coprozessor oder eine festverdrahtete Logik gegeben sein. Die Unterstützungseinrichtung SU ist über ein Control Interface COM und den lokalen Bus LB mit dem Prozessor verbunden und kann proprietäre Befehle des Prozessors ausführen und quittieren. Im wesentlichen handelt es sich um Load/Store von Daten, die in dem Programmablauf so eingebaut sind, daß die Daten rechtzeitig in einem FIFO (auch im Dual Port RAM) zur Verfügung stehen (preload, pipelining) .In the multi-processor system shown in FIG. 1, a plurality of basic processor systems PBSL.PBSn are connected via a peripheral bus PB to a central data processing memory HOST memory which has an external common memory. The processor base systems PBSl..PBSn are connected to a receiving unit RI (for: Receive Interface) and a transmitting unit TI (for: Transmit Interface), which are connected to the physical layer PL (for: physical layer) of a switching system. A processor base system PBSL.PBSn has a fast local bus LB which is equipped with a processor MP (for: microprocessor), a receive memory RM DP (for: receive memory dual port) with double access, a transmit memory TM DP (for: Transmit Memory Dual Port) with double access, a support device SU (for: Service Unit) and the peripheral bus PB. The processor MP may be provided by a processor kernel of the type MIPS RISC, Power PC, ..., for example. The processor can read and write access to the receive memory RM DP and the transmit memory TM DP can be done on one side by the processor and on the other side by the support device SU. The support facility SU is on the processing of special tasks such. B. performance-optimized standard functions, in particular burst load / store operations, formation of checksums, and can be provided by a proprietary coprocessor or hard-wired logic. The support device SU is connected to the processor via a control interface COM and the local bus LB and can execute and acknowledge proprietary commands from the processor. It is essentially a load / store of data that is built into the program sequence in such a way that the data is available in time in a FIFO (also in the dual port RAM) (preload, pipelining).
Die Empfangseinheit RI vermag Daten über die Unterstützungseinrichtung SU im Empfangsspeicher RM DP (Dual Port RAM) nach dem FIFO Prinzip zu speichern. Damit wird erreicht, daß immer ausreichend Verarbeitungsdaten dem Prozessor zur Verfügung stehen und er so nicht "leerlaufen" kann. Dieses Prinzip wird auf Receive und Transmit Seite getrennt angewendet, wobei die Erkenntnis ausgenutzt wird, daß beide Seiten i.a. auf unterschiedlichen Verbindungsdaten aufsetzen.The receiving unit RI can store data via the support device SU in the receiving memory RM DP (dual port RAM) according to the FIFO principle. This ensures that sufficient processing data is always available to the processor and so it cannot "run empty". This principle is applied separately on the receive and transmit side, making use of the knowledge that both sides generally based on different connection data.
Der lokale Bus LB ist ein schnelles Bussystem für schnelle Kommunikation zwischen Prozessor - Receive/Transmit Speicher (transiente Daten) und Prozessor - Service Unit, Anschluss an den Peripheren Bus PB zur externen Kommunikation. Der Prozessor ist der einzige Master am lokalen Bus, womit als bus con- tentions bezeichnete Staubildungen vermieden werden.The local bus LB is a fast bus system for fast communication between processor receive / transmit memory (transient data) and processor service unit, connection to the peripheral bus PB for external communication. The processor is the only master on the local bus, which prevents congestion, known as bus concentra- tions.
Die Unterstützungseinrichtung SU ist eine HW (Hardware) Einheit (proprietärer Coprozessor) , die vom Prozessor über ein Control interface (COM) gesteuert wird und performanceoptimierte Standardfunktionen zur Verfügung stellt, insbesondere Burst Load/Store Operationen zwischen Peripherie und den Receive/Transmit Speichern RMDP/TMDP.The support device SU is a hardware (hardware) unit (proprietary coprocessor) that is controlled by the processor via a control interface (COM) and provides performance-optimized standard functions, in particular burst load / store operations between peripherals and the receive / transmit memories RMDP / TMDP.
Durch ein vom Software-gesteuerten Prozessor MP gesteuertes Pre-Load der Daten vom externen Speicher (HOST Speicher) in die lokalen Speicher wird eine wesentliche Verbesserung der Systemperformance erreicht.A pre-load of the data from the external memory (HOST memory) into the local memory controlled by the software-controlled processor MP achieves a significant improvement in the system performance.
Der Empfangsspeicher RMDP und der Sendespeicher TMDP (Receive/Transmit Speicher) sind schnelle Zugriffsspeicher für die transienten (Verbindungs-) Daten getrennt nach eingehenden Verbindungs-Nachrichten und abzuschickenden Verbindungsnachrichten. Der Prozessor arbeitet im wesentlichen auf diesen Speichern. Der periphere Bus wird entlastet.The receive memory RMDP and the transmit memory TMDP (Receive / Transmit memory) are fast access memories for the transient (connection) data separated after incoming connection messages and connection messages to be sent. The processor essentially works on these memories. The peripheral bus is relieved.
In der Peripherie des Multi-Prozessorsystems sind die Emp- fangseinheit RI, die Sendeeinheit TI und der Periphere Bus PB angeordnet .The receiving unit RI, the transmitting unit TI and the peripheral bus PB are arranged in the periphery of the multi-processor system.
Die Empfangseinheit RI dient dem Anschluss externer Einrichtungen, z.B. switching network, physical layer. Eine Auftei- lungseinrichtung CR (für: Channel Router) verteilt die eingehenden (Verbindungs-) Daten auf die Prozessor-Basissysteme PBSl..PBSn, die darauf entkoppelt parallel arbeiten können (Service Unit schreibt die Empfangsdaten entsprechend Verbindungsnummer in den Receive Speicher, Fifo Prinzip) . In einer besonderen Ausführungsform ist die Zuordnung der einzelnen Verbindungen zu den Prozessor Basissystemen fest konfiguriert. Bei einem asynchronen Ubertragungsverfahren, wie z. B. dem ATM (Asynchronous Transfer Mode) -Verfahren, mag die Zuordnung der Verbindungsdaten zu den einzelnen Prozessor Basissystemen nach Maßgabe der Verbindungsbezeichnung VPI/VCI (Virtual Path Identifier/ Virtual Channel Identifier) erfol- gen.The receiving unit RI is used to connect external devices, eg switching network, physical layer. A division device CR (for: channel router) distributes the incoming (connection) data to the processor base systems PBSl..PBSn, which can then work in parallel when decoupled (service unit writes the received data according to the connection number into the receive memory, FIFO principle) ). In a special embodiment, the assignment of the individual connections to the processor base systems is permanently configured. In an asynchronous transmission method, such as. B. the ATM (Asynchronous Transfer Mode) method, the connection data may be assigned to the individual processor base systems in accordance with the connection name VPI / VCI (Virtual Path Identifier / Virtual Channel Identifier).
Die Sendeeinheit TI schickt entsprechend eines Sende-request Verfahrens (polling der Control Schnittstellen in den Service Units) die Verbindungs Nachrichten an die externen Einrich- tungen. Dabei ist es im allgemeinen nur wichtig, daß dieThe sending unit TI sends the connection messages to the external devices in accordance with a send request procedure (polling of the control interfaces in the service units). It is generally only important that the
Nachrichtensequenz pro Verbindung eingehalten wird. Die Sendeeinheit TI weist eine Zusammenführungseinrichtung CM (für: Channel Merger) zur Zusammenführung der Daten der einzelnen Verbindungen auf.Message sequence per connection is observed. The transmission unit TI has a merging device CM (for: channel merger) for merging the data of the individual connections.
Der Periphere Bus PB dient als Schnittstelle zu den gemeinsamen Speichern. Die gemeinsamen Speicher (Host Speicher) enthalten z.B. die kompletten Verbindungsdaten und werden vom HOST verwaltet. Durch die Vielzahl der angeschlossenen Pro- zessor Basissysteme besteht Überlast Gefahr (bus contentions) an dieser Schnittstelle. Mit dem von der Service Unit unterstützten Pre-Load/Store Mechanismus und das Halten von tran- sienten Daten in den lokalen Speichern wird der Peripheral Bus entlastet.The peripheral bus PB serves as an interface to the shared memories. The shared memory (host memory) contains e.g. the complete connection data and are managed by the HOST. Due to the large number of connected processor base systems, there is a risk of overload (bus contentions) at this interface. The peripheral bus is relieved with the pre-load / store mechanism supported by the service unit and the holding of transient data in the local memories.
Das anmeldungsgemäße Multi-Prozessorsystem mag in System on Chip (SoC) -Technologie, bei dem mehrere (RISC-) Prozessoren als Core-Ware in einem ASIC angeordnet sind, realisiert sein, The multi-processor system according to the application may be implemented in system on chip (SoC) technology, in which several (RISC) processors are arranged as core goods in an ASIC,

Claims

Patentansprüche claims
1. Anordnung zur Datenverarbeitung in Echtzeitanforderung, die an geänderte Aufgaben flexibel anpaßbar ist, bei der - ein Prozessor (MP) über einen lokalen Bus (LB) jeweils mit einem ersten Zugang eines Empfangsspeichers (RMDP) mit zweifachem Zugang und einem ersten Zugang eines Sendespeichers (TMDP) mit zweifachem Zugang und einem peripheren Bus (PB) in Wirkverbindung steht - eine Unterstützungseinrichtung (SU) mit dem zweiten Zugang des Empfangsspeichers, dem zweiten Zugang des Sendespei- chers, dem lokalen Bus, einer Empfangseinheit (RI) und einer Sendeeinheit (TI) verbunden ist1. Arrangement for data processing in real time request, which can be flexibly adapted to changed tasks, in which - a processor (MP) via a local bus (LB) each with a first access of a receive memory (RMDP) with double access and a first access of a transmit memory (TMDP) with double access and a peripheral bus (PB) is in operative connection - a support device (SU) with the second access of the reception memory, the second access of the transmission memory, the local bus, a reception unit (RI) and a transmission unit ( TI) is connected
- der lokale Bus und die Unterstützungseinrichtung über den peripheren Bus (PB) mit einer Datenverarbeitungseinrichtung- The local bus and the support device via the peripheral bus (PB) with a data processing device
(HOST) mit externem Speicher verbunden sind.(HOST) are connected to external storage.
2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß - der Prozessor, der lokale Bus, der Sendespeicher, der Empfangsspeicher und die Unterstützungseinrichtung ein Basissystem (PBSL.PBSn) bilden2. Arrangement according to claim 1, characterized in that - the processor, the local bus, the transmit memory, the receive memory and the support device form a basic system (PBSL.PBSn)
- mehrere Basissysteme gegeben sind, denen der periphere Bus, der externe Speicher der Datenverarbeitungseinrichtung, die Empfangseinheit und die Sendeeinheit gemeinsam zugeordnet sind.- There are several basic systems to which the peripheral bus, the external memory of the data processing device, the receiving unit and the transmitting unit are assigned together.
3. Anordnung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß - der Empfangseinrichtung Daten von Telekommunikationsverbindungen zuführbar sind und3. Arrangement according to one of the preceding claims, characterized in that - the receiving device data from telecommunications connections can be fed and
- die Daten auf die einzelnen Basissysteme nach Maßgabe der Bezeichnungen der Verbindungen aufteilbar sind.- The data can be divided into the individual basic systems in accordance with the names of the connections.
4. Anordnung nach einem der vorstehenden Ansprüche, gekennzeichnet durch eine Unterstützungseinrichtung, in der Standard-Funktionen ausführbar sind.4. Arrangement according to one of the preceding claims, characterized by a support facility in which standard functions can be carried out.
5. Anordnung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß5. Arrangement according to one of the preceding claims, characterized in that
Daten aus dem externen Speicher in den Sendespeicher und/oder den Empfangsspeicher vorladbar (pre-load) sind.Data can be preloaded from the external memory into the transmit memory and / or the receive memory (pre-load).
6. Anordnung nach einem der vorstehenden Ansprüche, gekennzeichnet durch eine Realisierung in einer System on Chip Anordnung. 6. Arrangement according to one of the preceding claims, characterized by an implementation in a system on chip arrangement.
PCT/DE2000/001015 1999-04-20 2000-04-03 Scalable multi-processor system for real time applications in communications engineering WO2000064197A1 (en)

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