WO2000067113A3 - Method and apparatus for thread switching within a multithreaded processor - Google Patents

Method and apparatus for thread switching within a multithreaded processor Download PDF

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Publication number
WO2000067113A3
WO2000067113A3 PCT/US2000/010800 US0010800W WO0067113A3 WO 2000067113 A3 WO2000067113 A3 WO 2000067113A3 US 0010800 W US0010800 W US 0010800W WO 0067113 A3 WO0067113 A3 WO 0067113A3
Authority
WO
WIPO (PCT)
Prior art keywords
thread
instruction
dispatch
multithreaded processor
thread switching
Prior art date
Application number
PCT/US2000/010800
Other languages
French (fr)
Other versions
WO2000067113A2 (en
Inventor
Stavros Kalafatis
Alan B Kyker
Robert D Fisch
Original Assignee
Intel Corp
Stavros Kalafatis
Alan B Kyker
Robert D Fisch
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Stavros Kalafatis, Alan B Kyker, Robert D Fisch filed Critical Intel Corp
Priority to BRPI0010602-0A priority Critical patent/BR0010602B1/en
Priority to DE60032481T priority patent/DE60032481T2/en
Priority to IL14615900A priority patent/IL146159A0/en
Priority to EP00926240A priority patent/EP1185924B1/en
Priority to AU44802/00A priority patent/AU4480200A/en
Publication of WO2000067113A2 publication Critical patent/WO2000067113A2/en
Publication of WO2000067113A3 publication Critical patent/WO2000067113A3/en
Priority to IL146159A priority patent/IL146159A/en
Priority to HK02104141A priority patent/HK1042363A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

A method of performing a thread switching operation within a multithreaded processor. The dispatch of a first predetermined quantity of instruction information for a first thread, from an instruction streaming buffer to an instruction pre-decoder within the multithreaded processor, is detected. Responsive to the detection of the dispatch of the first predetermined quantity of instruction information for the first thread, a thread switching operation is performed with respect to the output of the instruction streaming buffer. The dispatch of instruction information for a second thread from the instruction streaming buffer is thus commenced. The utilization of processor resources is distributed between threads according to the quantity of instruction data for a particular thread that has been processed (or dispatch for processing), and not according to an arbitrary timing mechanism.
PCT/US2000/010800 1999-04-29 2000-04-20 Method and apparatus for thread switching within a multithreaded processor WO2000067113A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
BRPI0010602-0A BR0010602B1 (en) 1999-04-29 2000-04-20 method of performing a task switching operation on a multitasking processor.
DE60032481T DE60032481T2 (en) 1999-04-29 2000-04-20 METHOD AND DEVICE FOR THREAD-SWITCHING IN A MULTITHREAD PROCESSOR
IL14615900A IL146159A0 (en) 1999-04-29 2000-04-20 Method and apparatus for thread switching within a multi-threaded processor
EP00926240A EP1185924B1 (en) 1999-04-29 2000-04-20 Method and apparatus for thread switching within a multithreaded processor
AU44802/00A AU4480200A (en) 1999-04-29 2000-04-20 Method and apparatus for thread switching within a multithreaded processor
IL146159A IL146159A (en) 1999-04-29 2001-10-25 Method and apparatus for thread switching within a
HK02104141A HK1042363A1 (en) 1999-04-29 2002-05-31 Method and apparatus for thread switching within amultithreaded processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/302,633 US6535905B1 (en) 1999-04-29 1999-04-29 Method and apparatus for thread switching within a multithreaded processor
US09/302,633 1999-04-29

Publications (2)

Publication Number Publication Date
WO2000067113A2 WO2000067113A2 (en) 2000-11-09
WO2000067113A3 true WO2000067113A3 (en) 2001-09-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/010800 WO2000067113A2 (en) 1999-04-29 2000-04-20 Method and apparatus for thread switching within a multithreaded processor

Country Status (10)

Country Link
US (8) US6535905B1 (en)
EP (1) EP1185924B1 (en)
CN (2) CN1196060C (en)
AU (1) AU4480200A (en)
BR (1) BR0010602B1 (en)
DE (1) DE60032481T2 (en)
HK (1) HK1042363A1 (en)
IL (2) IL146159A0 (en)
TW (1) TW476915B (en)
WO (1) WO2000067113A2 (en)

Families Citing this family (224)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2728559B1 (en) * 1994-12-23 1997-01-31 Saint Gobain Vitrage GLASS SUBSTRATES COATED WITH A STACK OF THIN LAYERS WITH INFRARED REFLECTION PROPERTIES AND / OR IN THE FIELD OF SOLAR RADIATION
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US7035997B1 (en) * 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
US7020879B1 (en) * 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6507862B1 (en) * 1999-05-11 2003-01-14 Sun Microsystems, Inc. Switching method in a multi-threaded processor
US6671795B1 (en) * 2000-01-21 2003-12-30 Intel Corporation Method and apparatus for pausing execution in a processor or the like
US7155516B2 (en) * 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7042887B2 (en) * 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7076630B2 (en) * 2000-02-08 2006-07-11 Mips Tech Inc Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
US7139901B2 (en) * 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7649901B2 (en) * 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7058065B2 (en) * 2000-02-08 2006-06-06 Mips Tech Inc Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
US7032226B1 (en) * 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
US7065096B2 (en) 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7058064B2 (en) * 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US20010052053A1 (en) * 2000-02-08 2001-12-13 Mario Nemirovsky Stream processing unit for a multi-streaming processor
US7856633B1 (en) * 2000-03-24 2010-12-21 Intel Corporation LRU cache replacement for a partitioned set associative cache
US7162615B1 (en) * 2000-06-12 2007-01-09 Mips Technologies, Inc. Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch
JP2004518183A (en) * 2000-07-14 2004-06-17 クリアウオーター・ネツトワークス・インコーポレイテツド Instruction fetch and dispatch in multithreaded systems
US6701518B1 (en) * 2000-08-03 2004-03-02 Hewlett-Packard Development Company, L.P. System and method for enabling efficient processing of a program that includes assertion instructions
US6981129B1 (en) * 2000-11-02 2005-12-27 Intel Corporation Breaking replay dependency loops in a processor using a rescheduled replay queue
US7757065B1 (en) * 2000-11-09 2010-07-13 Intel Corporation Instruction segment recording scheme
US20020087844A1 (en) * 2000-12-29 2002-07-04 Udo Walterscheidt Apparatus and method for concealing switch latency
US6895520B1 (en) 2001-03-02 2005-05-17 Advanced Micro Devices, Inc. Performance and power optimization via block oriented performance measurement and control
US20020156999A1 (en) * 2001-04-19 2002-10-24 International Business Machines Corporation Mixed-mode hardware multithreading
US6651158B2 (en) * 2001-06-22 2003-11-18 Intel Corporation Determination of approaching instruction starvation of threads based on a plurality of conditions
US20030120896A1 (en) * 2001-06-29 2003-06-26 Jason Gosior System on chip architecture
US20030126416A1 (en) * 2001-12-31 2003-07-03 Marr Deborah T. Suspending execution of a thread in a multi-threaded processor
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7127561B2 (en) * 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US7366884B2 (en) * 2002-02-25 2008-04-29 Agere Systems Inc. Context switching system for a multi-thread execution pipeline loop and method of operation thereof
US9207958B1 (en) 2002-08-12 2015-12-08 Arm Finance Overseas Limited Virtual machine coprocessor for accelerating software execution
US7065596B2 (en) * 2002-09-19 2006-06-20 Intel Corporation Method and apparatus to resolve instruction starvation
US7200721B1 (en) * 2002-10-09 2007-04-03 Unisys Corporation Verification of memory operations by multiple processors to a shared memory
US7149900B2 (en) * 2002-12-12 2006-12-12 Intel Corporation Method of defending software from debugger attacks
US20040128476A1 (en) * 2002-12-26 2004-07-01 Robert Nuckolls Scheme to simplify instruction buffer logic supporting multiple strands
US20040128488A1 (en) * 2002-12-26 2004-07-01 Thimmannagari Chandra M. R. Strand switching algorithm to avoid strand starvation
US7657893B2 (en) 2003-04-23 2010-02-02 International Business Machines Corporation Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor
US7363625B2 (en) * 2003-04-24 2008-04-22 International Business Machines Corporation Method for changing a thread priority in a simultaneous multithread processor
US20040216103A1 (en) * 2003-04-24 2004-10-28 International Business Machines Corporation Mechanism for detecting and handling a starvation of a thread in a multithreading processor environment
US7401207B2 (en) 2003-04-25 2008-07-15 International Business Machines Corporation Apparatus and method for adjusting instruction thread priority in a multi-thread processor
US7401208B2 (en) * 2003-04-25 2008-07-15 International Business Machines Corporation Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor
US7360062B2 (en) * 2003-04-25 2008-04-15 International Business Machines Corporation Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
US20040268099A1 (en) * 2003-06-30 2004-12-30 Smith Peter J Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory
US7441245B2 (en) * 2003-08-14 2008-10-21 Intel Corporation Phasing for a multi-threaded network processor
US7873785B2 (en) * 2003-08-19 2011-01-18 Oracle America, Inc. Multi-core multi-thread processor
US20050047439A1 (en) * 2003-08-26 2005-03-03 Madajczak Tomasz Bogdan System to process packets according to an assigned sequence number
US7496921B2 (en) * 2003-08-29 2009-02-24 Intel Corporation Processing block with integrated light weight multi-threading support
US20050055594A1 (en) * 2003-09-05 2005-03-10 Doering Andreas C. Method and device for synchronizing a processor and a coprocessor
US7133969B2 (en) * 2003-10-01 2006-11-07 Advanced Micro Devices, Inc. System and method for handling exceptional instructions in a trace cache based processor
US7555633B1 (en) 2003-11-03 2009-06-30 Advanced Micro Devices, Inc. Instruction cache prefetch based on trace cache eviction
JP2007516662A (en) * 2003-11-07 2007-06-21 シャープ株式会社 System and method for network channel characteristic value measurement and network management
DE10353267B3 (en) * 2003-11-14 2005-07-28 Infineon Technologies Ag Multithread processor architecture for triggered thread switching without cycle time loss and without switching program command
US8069336B2 (en) * 2003-12-03 2011-11-29 Globalfoundries Inc. Transitioning from instruction cache to trace cache on label boundaries
US7631307B2 (en) 2003-12-05 2009-12-08 Intel Corporation User-programmable low-overhead multithreading
US7360064B1 (en) 2003-12-10 2008-04-15 Cisco Technology, Inc. Thread interleaving in a multithreaded embedded processor
US7441101B1 (en) 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US20060212874A1 (en) * 2003-12-12 2006-09-21 Johnson Erik J Inserting instructions
US7493621B2 (en) * 2003-12-18 2009-02-17 International Business Machines Corporation Context switch data prefetching in multithreaded computer
US7206922B1 (en) 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US7213126B1 (en) 2004-01-12 2007-05-01 Advanced Micro Devices, Inc. Method and processor including logic for storing traces within a trace cache
US20050166177A1 (en) * 2004-01-27 2005-07-28 Ylian Saint-Hilaire Thread module chaining
US20050183065A1 (en) * 2004-02-13 2005-08-18 Wolczko Mario I. Performance counters in a multi-threaded processor
US20090299756A1 (en) * 2004-03-01 2009-12-03 Dolby Laboratories Licensing Corporation Ratio of speech to non-speech audio such as for elderly or hearing-impaired listeners
US7426731B2 (en) * 2004-03-22 2008-09-16 Hewlett-Packard Development Company, L.P. Determining processor usage by a thread
US9189230B2 (en) 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US7197630B1 (en) 2004-04-12 2007-03-27 Advanced Micro Devices, Inc. Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation
US7418582B1 (en) 2004-05-13 2008-08-26 Sun Microsystems, Inc. Versatile register file design for a multi-threaded processor utilizing different modes and register windows
US7519796B1 (en) 2004-06-30 2009-04-14 Sun Microsystems, Inc. Efficient utilization of a store buffer using counters
US7543132B1 (en) 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US7365007B2 (en) * 2004-06-30 2008-04-29 Intel Corporation Interconnects with direct metalization and conductive polymer
US7290116B1 (en) 2004-06-30 2007-10-30 Sun Microsystems, Inc. Level 2 cache index hashing to avoid hot spots
US20060009265A1 (en) * 2004-06-30 2006-01-12 Clapper Edward O Communication blackout feature
US7509484B1 (en) 2004-06-30 2009-03-24 Sun Microsystems, Inc. Handling cache misses by selectively flushing the pipeline
US7571284B1 (en) 2004-06-30 2009-08-04 Sun Microsystems, Inc. Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7748001B2 (en) * 2004-09-23 2010-06-29 Intel Corporation Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time
US9626194B2 (en) 2004-09-23 2017-04-18 Intel Corporation Thread livelock unit
US7533139B2 (en) * 2004-09-27 2009-05-12 Microsoft Corporation Method and system for multithread processing of spreadsheet chain calculations
CN100384181C (en) * 2004-11-09 2008-04-23 北京中星微电子有限公司 A multipath audio frequency buffering method under IP network environment
US7254693B2 (en) * 2004-12-02 2007-08-07 International Business Machines Corporation Selectively prohibiting speculative execution of conditional branch type based on instruction bit
US8756605B2 (en) * 2004-12-17 2014-06-17 Oracle America, Inc. Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline
US7937709B2 (en) * 2004-12-29 2011-05-03 Intel Corporation Synchronizing multiple threads efficiently
US7430643B2 (en) * 2004-12-30 2008-09-30 Sun Microsystems, Inc. Multiple contexts for efficient use of translation lookaside buffer
US7490230B2 (en) * 2005-02-04 2009-02-10 Mips Technologies, Inc. Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
US7752627B2 (en) * 2005-02-04 2010-07-06 Mips Technologies, Inc. Leaky-bucket thread scheduler in a multithreading microprocessor
US7657891B2 (en) 2005-02-04 2010-02-02 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US7853777B2 (en) * 2005-02-04 2010-12-14 Mips Technologies, Inc. Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
US7664936B2 (en) * 2005-02-04 2010-02-16 Mips Technologies, Inc. Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
US7631130B2 (en) * 2005-02-04 2009-12-08 Mips Technologies, Inc Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US7657883B2 (en) * 2005-02-04 2010-02-02 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
US7506140B2 (en) * 2005-02-04 2009-03-17 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US7681014B2 (en) 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7613904B2 (en) * 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
DE102005009083B4 (en) * 2005-02-28 2007-05-10 Infineon Technologies Ag Multithread processor with a synchronization unit and method of operating such
US20060206902A1 (en) * 2005-03-14 2006-09-14 Sujat Jamil Variable interleaved multithreaded processor method and system
US20060212853A1 (en) * 2005-03-18 2006-09-21 Marvell World Trade Ltd. Real-time control apparatus having a multi-thread processor
US8195922B2 (en) * 2005-03-18 2012-06-05 Marvell World Trade, Ltd. System for dynamically allocating processing time to multiple threads
US8230423B2 (en) * 2005-04-07 2012-07-24 International Business Machines Corporation Multithreaded processor architecture with operational latency hiding
US8041930B2 (en) * 2005-05-11 2011-10-18 Arm Limited Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains
US20070067502A1 (en) * 2005-09-22 2007-03-22 Silicon Integrated Systems Corp. Method for preventing long latency event
US7937564B1 (en) 2005-09-28 2011-05-03 Oracle America, Inc. Emit vector optimization of a trace
US7949854B1 (en) 2005-09-28 2011-05-24 Oracle America, Inc. Trace unit with a trace builder
US8024522B1 (en) 2005-09-28 2011-09-20 Oracle America, Inc. Memory ordering queue/versioning cache circuit
US7953961B1 (en) 2005-09-28 2011-05-31 Oracle America, Inc. Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder
US8051247B1 (en) 2005-09-28 2011-11-01 Oracle America, Inc. Trace based deallocation of entries in a versioning cache circuit
US8370576B1 (en) 2005-09-28 2013-02-05 Oracle America, Inc. Cache rollback acceleration via a bank based versioning cache ciruit
US8037285B1 (en) 2005-09-28 2011-10-11 Oracle America, Inc. Trace unit
US8032710B1 (en) 2005-09-28 2011-10-04 Oracle America, Inc. System and method for ensuring coherency in trace execution
US7987342B1 (en) 2005-09-28 2011-07-26 Oracle America, Inc. Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer
US8015359B1 (en) 2005-09-28 2011-09-06 Oracle America, Inc. Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit
US8019944B1 (en) * 2005-09-28 2011-09-13 Oracle America, Inc. Checking for a memory ordering violation after a speculative cache write
US7870369B1 (en) 2005-09-28 2011-01-11 Oracle America, Inc. Abort prioritization in a trace-based processor
US7966479B1 (en) 2005-09-28 2011-06-21 Oracle America, Inc. Concurrent vs. low power branch prediction
US7676634B1 (en) 2005-09-28 2010-03-09 Sun Microsystems, Inc. Selective trace cache invalidation for self-modifying code via memory aging
US8499293B1 (en) 2005-09-28 2013-07-30 Oracle America, Inc. Symbolic renaming optimization of a trace
US7877630B1 (en) 2005-09-28 2011-01-25 Oracle America, Inc. Trace based rollback of a speculatively updated cache
US20070101102A1 (en) * 2005-10-27 2007-05-03 Dierks Herman D Jr Selectively pausing a software thread
US20070150895A1 (en) * 2005-12-06 2007-06-28 Kurland Aaron S Methods and apparatus for multi-core processing with dedicated thread management
US8275942B2 (en) * 2005-12-22 2012-09-25 Intel Corporation Performance prioritization in multi-threaded processors
JP4519082B2 (en) * 2006-02-15 2010-08-04 株式会社ソニー・コンピュータエンタテインメント Information processing method, moving image thumbnail display method, decoding device, and information processing device
US7877757B2 (en) * 2006-05-05 2011-01-25 Microsoft Corporation Work item event monitor for procession of queued events
US8032821B2 (en) 2006-05-08 2011-10-04 Microsoft Corporation Multi-thread spreadsheet processing with dependency levels
US9146745B2 (en) * 2006-06-29 2015-09-29 Intel Corporation Method and apparatus for partitioned pipelined execution of multiple execution threads
US20080022283A1 (en) * 2006-07-19 2008-01-24 International Business Machines Corporation Quality of service scheduling for simultaneous multi-threaded processors
US8495649B2 (en) * 2006-07-19 2013-07-23 International Business Machines Corporation Scheduling threads having complementary functional unit usage on SMT processors
US8046775B2 (en) * 2006-08-14 2011-10-25 Marvell World Trade Ltd. Event-based bandwidth allocation mode switching method and apparatus
US7941643B2 (en) * 2006-08-14 2011-05-10 Marvell World Trade Ltd. Multi-thread processor with multiple program counters
US20090012564A1 (en) * 2007-03-07 2009-01-08 Spineworks Medical, Inc. Transdiscal interbody fusion device and method
US7773621B2 (en) * 2006-09-16 2010-08-10 Mips Technologies, Inc. Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
US7990989B2 (en) * 2006-09-16 2011-08-02 Mips Technologies, Inc. Transaction selector employing transaction queue group priorities in multi-port switch
US7961745B2 (en) * 2006-09-16 2011-06-14 Mips Technologies, Inc. Bifurcated transaction selector supporting dynamic priorities in multi-port switch
US7760748B2 (en) * 2006-09-16 2010-07-20 Mips Technologies, Inc. Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
US8370609B1 (en) 2006-09-27 2013-02-05 Oracle America, Inc. Data cache rollbacks for failed speculative traces with memory operations
US8010745B1 (en) * 2006-09-27 2011-08-30 Oracle America, Inc. Rolling back a speculative update of a non-modifiable cache line
US8516462B2 (en) * 2006-10-09 2013-08-20 International Business Machines Corporation Method and apparatus for managing a stack
US8380966B2 (en) 2006-11-15 2013-02-19 Qualcomm Incorporated Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging
US8533530B2 (en) 2006-11-15 2013-09-10 Qualcomm Incorporated Method and system for trusted/untrusted digital signal processor debugging operations
US8341604B2 (en) 2006-11-15 2012-12-25 Qualcomm Incorporated Embedded trace macrocell for enhanced digital signal processor debugging operations
US8370806B2 (en) 2006-11-15 2013-02-05 Qualcomm Incorporated Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor
US20080148022A1 (en) * 2006-12-13 2008-06-19 Arm Limited Marking registers as available for register renaming
US8347068B2 (en) * 2007-04-04 2013-01-01 International Business Machines Corporation Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor
US8521993B2 (en) * 2007-04-09 2013-08-27 Intel Corporation Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessor
US8261049B1 (en) 2007-04-10 2012-09-04 Marvell International Ltd. Determinative branch prediction indexing
US8484516B2 (en) 2007-04-11 2013-07-09 Qualcomm Incorporated Inter-thread trace alignment method and system for a multi-threaded processor
US20080263325A1 (en) * 2007-04-19 2008-10-23 International Business Machines Corporation System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessor
US7711935B2 (en) * 2007-04-30 2010-05-04 Netlogic Microsystems, Inc. Universal branch identifier for invalidation of speculative instructions
US7958323B1 (en) 2007-05-09 2011-06-07 Marvell Israel (M.I.S.L.) Ltd. Multithreading implementation for flops and register files
JP5136553B2 (en) * 2007-06-20 2013-02-06 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
KR101100145B1 (en) * 2007-06-20 2011-12-29 후지쯔 가부시끼가이샤 Instruction execution controller and instruction execution control method
WO2008155807A1 (en) * 2007-06-20 2008-12-24 Fujitsu Limited Information processor and load arbitration control method
WO2008155834A1 (en) * 2007-06-20 2008-12-24 Fujitsu Limited Processing device
EP2159691B1 (en) * 2007-06-20 2013-08-28 Fujitsu Limited Simultaneous multithreaded instruction completion controller
US7779234B2 (en) * 2007-10-23 2010-08-17 International Business Machines Corporation System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor
US8086825B2 (en) * 2007-12-31 2011-12-27 Advanced Micro Devices, Inc. Processing pipeline having stage-specific thread selection and method thereof
US7793080B2 (en) * 2007-12-31 2010-09-07 Globalfoundries Inc. Processing pipeline having parallel dispatch and method thereof
US20090172370A1 (en) * 2007-12-31 2009-07-02 Advanced Micro Devices, Inc. Eager execution in a processing pipeline having multiple integer execution units
US8479173B2 (en) * 2008-07-09 2013-07-02 International Business Machines Corporation Efficient and self-balancing verification of multi-threaded microprocessors
US8161493B2 (en) * 2008-07-15 2012-04-17 International Business Machines Corporation Weighted-region cycle accounting for multi-threaded processor cores
US8386547B2 (en) * 2008-10-31 2013-02-26 Intel Corporation Instruction and logic for performing range detection
US8347309B2 (en) * 2009-07-29 2013-01-01 Oracle America, Inc. Dynamic mitigation of thread hogs on a threaded processor
EP2494361B2 (en) * 2009-10-26 2019-01-09 Externautics S.p.A. Ovary tumor markers and methods of use thereof
US20110191775A1 (en) * 2010-01-29 2011-08-04 Microsoft Corporation Array-based thread countdown
US9354926B2 (en) * 2011-03-22 2016-05-31 International Business Machines Corporation Processor management via thread status
JP5861354B2 (en) * 2011-09-22 2016-02-16 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device
CN102495762B (en) * 2011-11-16 2014-04-02 华为技术有限公司 Thread scheduling method, thread scheduling device and multi-core processor system
US9052909B2 (en) 2011-12-07 2015-06-09 Arm Limited Recovering from exceptions and timing errors
US8738971B2 (en) 2011-12-07 2014-05-27 Arm Limited Limiting certain processing activities as error rate probability rises
US8935574B2 (en) 2011-12-16 2015-01-13 Advanced Micro Devices, Inc. Correlating traces in a computing system
US9075621B2 (en) 2011-12-23 2015-07-07 Arm Limited Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution
US8640008B2 (en) 2011-12-23 2014-01-28 Arm Limited Error recovery in a data processing apparatus
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US9665375B2 (en) 2012-04-26 2017-05-30 Oracle International Corporation Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss
US9875105B2 (en) * 2012-05-03 2018-01-23 Nvidia Corporation Checkpointed buffer for re-entry from runahead
US9824013B2 (en) 2012-05-08 2017-11-21 Qualcomm Incorporated Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US9514069B1 (en) 2012-05-24 2016-12-06 Schwegman, Lundberg & Woessner, P.A. Enhanced computer processor and memory management architecture
US8832500B2 (en) 2012-08-10 2014-09-09 Advanced Micro Devices, Inc. Multiple clock domain tracing
US9323315B2 (en) * 2012-08-15 2016-04-26 Nvidia Corporation Method and system for automatic clock-gating of a clock grid at a clock source
US8959398B2 (en) 2012-08-16 2015-02-17 Advanced Micro Devices, Inc. Multiple clock domain debug capability
US9645929B2 (en) 2012-09-14 2017-05-09 Nvidia Corporation Speculative permission acquisition for shared memory
US9317297B2 (en) * 2012-09-27 2016-04-19 Intel Corporation Replay execution of instructions in thread chunks in the chunk order recorded during previous execution
US10001996B2 (en) 2012-10-26 2018-06-19 Nvidia Corporation Selective poisoning of data during runahead
US9740553B2 (en) 2012-11-14 2017-08-22 Nvidia Corporation Managing potentially invalid results during runahead
US9632976B2 (en) 2012-12-07 2017-04-25 Nvidia Corporation Lazy runahead operation for a microprocessor
US20140181484A1 (en) * 2012-12-21 2014-06-26 James Callister Mechanism to provide high performance and fairness in a multi-threading computer system
US9569214B2 (en) 2012-12-27 2017-02-14 Nvidia Corporation Execution pipeline data forwarding
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US9823931B2 (en) 2012-12-28 2017-11-21 Nvidia Corporation Queued instruction re-dispatch after runahead
US9547602B2 (en) 2013-03-14 2017-01-17 Nvidia Corporation Translation lookaside buffer entry systems and methods
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
US9471318B2 (en) 2013-03-15 2016-10-18 International Business Machines Corporation System management and instruction counting
CN104123195B (en) * 2013-04-23 2018-03-13 华为技术有限公司 One kind instruction sweep-out method and device
US9367472B2 (en) 2013-06-10 2016-06-14 Oracle International Corporation Observation of data in persistent memory
US9582280B2 (en) 2013-07-18 2017-02-28 Nvidia Corporation Branching to alternate code based on runahead determination
KR20150019349A (en) * 2013-08-13 2015-02-25 삼성전자주식회사 Multiple threads execution processor and its operating method
GB2519103B (en) * 2013-10-09 2020-05-06 Advanced Risc Mach Ltd Decoding a complex program instruction corresponding to multiple micro-operations
TWI602113B (en) * 2013-11-14 2017-10-11 宏碁股份有限公司 Method for switching operation interface and mobile communication apparatus using the same
US9535746B2 (en) * 2013-12-19 2017-01-03 International Business Machines Corporation Honoring hardware entitlement of a hardware thread
US10241498B1 (en) * 2014-05-15 2019-03-26 Feetz, Inc. Customized, additive-manufactured outerwear and methods for manufacturing thereof
US9824413B2 (en) * 2014-11-15 2017-11-21 Intel Corporation Sort-free threading model for a multi-threaded graphics pipeline
CN105786448B (en) * 2014-12-26 2019-02-05 深圳市中兴微电子技术有限公司 A kind of instruction dispatching method and device
JP6477216B2 (en) * 2015-05-08 2019-03-06 富士通株式会社 Arithmetic device, thread switching method, and multi-thread program
GB2544994A (en) * 2015-12-02 2017-06-07 Swarm64 As Data processing
CN106126336B (en) * 2016-06-17 2019-06-04 上海兆芯集成电路有限公司 Processor and dispatching method
US10269088B2 (en) * 2017-04-21 2019-04-23 Intel Corporation Dynamic thread execution arbitration
US10325341B2 (en) 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
US10503550B2 (en) 2017-09-30 2019-12-10 Intel Corporation Dynamic performance biasing in a processor
US11789741B2 (en) * 2018-03-08 2023-10-17 Sap Se Determining an optimum quantity of interleaved instruction streams of defined coroutines
US10831492B2 (en) 2018-07-05 2020-11-10 International Business Machines Corporation Most favored branch issue
US10997058B2 (en) * 2018-07-30 2021-05-04 EMC IP Holding Company LLC Method for performance analysis in a continuous integration pipeline
US20190253357A1 (en) * 2018-10-15 2019-08-15 Intel Corporation Load balancing based on packet processing loads
US11856073B1 (en) * 2019-03-22 2023-12-26 Amazon Technologies, Inc. Message batching for communication protocols
US11886916B2 (en) 2020-06-30 2024-01-30 Microsoft Technology Licensing, Llc System for adaptive multithreaded recalculation operations

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0346003A2 (en) * 1988-06-07 1989-12-13 Fujitsu Limited Multiprocessor control system
EP0352935A2 (en) * 1988-07-27 1990-01-31 International Computers Limited Pipelined processor
EP0747816A2 (en) * 1995-06-07 1996-12-11 International Business Machines Corporation Method and system for high performance multithread operation in a data processing system
US5761522A (en) * 1995-05-24 1998-06-02 Fuji Xerox Co., Ltd. Program control system programmable to selectively execute a plurality of programs
WO1999021082A1 (en) * 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771138A (en) 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
WO1990014629A2 (en) 1989-05-26 1990-11-29 Massachusetts Institute Of Technology Parallel multithreaded data processing system
GB2234613B (en) 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US5396635A (en) 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
DE4129614C2 (en) 1990-09-07 2002-03-21 Hitachi Ltd System and method for data processing
US5088788A (en) * 1991-03-22 1992-02-18 Moulton Lee A Vehicle cover apparatus
US5430850A (en) * 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
JP2520544B2 (en) * 1991-09-26 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション Method for monitoring task overrun status and apparatus for detecting overrun of task execution cycle
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5404469A (en) 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5452401A (en) 1992-03-31 1995-09-19 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5386561A (en) 1992-03-31 1995-01-31 International Business Machines Corporation Method of integrated system load control through dynamic time-slicing in a virtual storage environment
US5325526A (en) * 1992-05-12 1994-06-28 Intel Corporation Task scheduling in a multicomputer system
JPH0695898A (en) * 1992-09-16 1994-04-08 Hitachi Ltd Control method for virtual computer and virtual computer system
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
KR100313261B1 (en) 1992-12-23 2002-02-28 앙드래베이너,조엘브르리아드 Low Power Multi-task Controller (Name Correction)
US5586332A (en) 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
DE69429204T2 (en) * 1993-03-26 2002-07-25 Cabletron Systems Inc Sequence control method and device for a communication network
US5528513A (en) * 1993-11-04 1996-06-18 Digital Equipment Corp. Scheduling and admission control policy for a continuous media server
US5524263A (en) * 1994-02-25 1996-06-04 Intel Corporation Method and apparatus for partial and full stall handling in allocation
US5809271A (en) * 1994-03-01 1998-09-15 Intel Corporation Method and apparatus for changing flow of control in a processor
JP3547482B2 (en) * 1994-04-15 2004-07-28 株式会社日立製作所 Information processing equipment
US6009454A (en) * 1994-09-30 1999-12-28 Allen-Bradley Company, Llc Multi-tasking operation system for industrial controller
US5724565A (en) 1995-02-03 1998-03-03 International Business Machines Corporation Method and system for processing first and second sets of instructions by first and second types of processing systems
US5983339A (en) 1995-08-21 1999-11-09 International Business Machines Corporation Power down system and method for pipelined logic functions
GB2306147B (en) 1995-10-13 1999-11-17 Marconi Gec Ltd Drag-producing aerodynamic device
US5701432A (en) 1995-10-13 1997-12-23 Sun Microsystems, Inc. Multi-threaded processing system having a cache that is commonly accessible to each thread
US5809522A (en) 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
GB2311880A (en) 1996-04-03 1997-10-08 Advanced Risc Mach Ltd Partitioned cache memory
CN1147785C (en) * 1996-08-27 2004-04-28 松下电器产业株式会社 Multi-program-flow synchronous processor independently processing multiple instruction stream, soft controlling processing function of every instrunetion
US6088788A (en) 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
EP0856797B1 (en) 1997-01-30 2003-05-21 STMicroelectronics Limited A cache system for concurrent processes
EP0863462B8 (en) * 1997-03-04 2010-07-28 Panasonic Corporation Processor capable of efficiently executing many asynchronous event tasks
US5835705A (en) 1997-03-11 1998-11-10 International Business Machines Corporation Method and system for performance per-thread monitoring in a multithreaded processor
GB2323188B (en) 1997-03-14 2002-02-06 Nokia Mobile Phones Ltd Enabling and disabling clocking signals to elements
US6314530B1 (en) * 1997-04-08 2001-11-06 Advanced Micro Devices, Inc. Processor having a trace access instruction to access on-chip trace memory
US5996085A (en) 1997-07-15 1999-11-30 International Business Machines Corporation Concurrent execution of machine context synchronization operations and non-interruptible instructions
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6105051A (en) 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6092175A (en) * 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6330584B1 (en) * 1998-04-03 2001-12-11 Mmc Networks, Inc. Systems and methods for multi-tasking, resource sharing and execution of computer instructions
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6289461B1 (en) * 1998-06-09 2001-09-11 Placeware, Inc. Bi-directional process-to-process byte stream protocol
US6625635B1 (en) 1998-11-02 2003-09-23 International Business Machines Corporation Deterministic and preemptive thread scheduling and its use in debugging multithreaded applications
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0346003A2 (en) * 1988-06-07 1989-12-13 Fujitsu Limited Multiprocessor control system
EP0352935A2 (en) * 1988-07-27 1990-01-31 International Computers Limited Pipelined processor
US5761522A (en) * 1995-05-24 1998-06-02 Fuji Xerox Co., Ltd. Program control system programmable to selectively execute a plurality of programs
EP0747816A2 (en) * 1995-06-07 1996-12-11 International Business Machines Corporation Method and system for high performance multithread operation in a data processing system
WO1999021082A1 (en) * 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor

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