WO2000075964A3 - Method of fabricating semiconductor device employing copper interconnect structure - Google Patents

Method of fabricating semiconductor device employing copper interconnect structure Download PDF

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Publication number
WO2000075964A3
WO2000075964A3 PCT/KR1999/000847 KR9900847W WO0075964A3 WO 2000075964 A3 WO2000075964 A3 WO 2000075964A3 KR 9900847 W KR9900847 W KR 9900847W WO 0075964 A3 WO0075964 A3 WO 0075964A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
interconnect structure
fabricating semiconductor
layer
device employing
Prior art date
Application number
PCT/KR1999/000847
Other languages
French (fr)
Other versions
WO2000075964A2 (en
Inventor
Ki-Bum Kim
Original Assignee
Kim Ki Bum
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kim Ki Bum filed Critical Kim Ki Bum
Publication of WO2000075964A2 publication Critical patent/WO2000075964A2/en
Publication of WO2000075964A3 publication Critical patent/WO2000075964A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a method of forming interconnect structure in a process for fabricating semiconductor device, which enables high-reliability copper interconnect. The present invention uses the structure comprised of TiN layer (32) and intermediate aluminum layer (34) as a diffusion barrier. A copper layer (40) is deposited on the aluminum layer (34), after aluminum layer (34) is deposited on the TiN layer (32). At this time, with the aluminum layer (34) being made to the minimum thickness, metallization is formed substantially with the copper.
PCT/KR1999/000847 1999-06-05 1999-12-30 Method of fabricating semiconductor device employing copper interconnect structure WO2000075964A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1999/20828 1999-06-05
KR1019990020828A KR20010001543A (en) 1999-06-05 1999-06-05 Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure

Publications (2)

Publication Number Publication Date
WO2000075964A2 WO2000075964A2 (en) 2000-12-14
WO2000075964A3 true WO2000075964A3 (en) 2001-03-15

Family

ID=19590309

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR1999/000847 WO2000075964A2 (en) 1999-06-05 1999-12-30 Method of fabricating semiconductor device employing copper interconnect structure

Country Status (2)

Country Link
KR (1) KR20010001543A (en)
WO (1) WO2000075964A2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7655543B2 (en) 2007-12-21 2010-02-02 Asm America, Inc. Separate injection of reactive species in selective formation of films
US7687383B2 (en) 2005-02-04 2010-03-30 Asm America, Inc. Methods of depositing electrically active doped crystalline Si-containing films
US7759199B2 (en) 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US7863163B2 (en) 2005-12-22 2011-01-04 Asm America, Inc. Epitaxial deposition of doped semiconductor materials
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US8486191B2 (en) 2009-04-07 2013-07-16 Asm America, Inc. Substrate reactor with adjustable injectors for mixing gases within reaction chamber
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6727169B1 (en) 1999-10-15 2004-04-27 Asm International, N.V. Method of making conformal lining layers for damascene metallization
KR100386034B1 (en) * 2000-12-06 2003-06-02 에이에스엠 마이크로케미스트리 리미티드 Method of Fabricating Semiconductor Device Employing Copper Interconnect Structure Having Diffusion Barrier Stuffed with Metal Oxide
JP2005528776A (en) * 2001-09-26 2005-09-22 アプライド　マテリアルズ　インコーポレイテッド Integration of barrier layer and seed layer
KR100877268B1 (en) * 2007-06-25 2009-01-07 주식회사 동부하이텍 Method for improving interconnection between aluminum and copper in semiconductor metal line process
CN111105990B (en) * 2018-10-29 2023-06-23 株洲中车时代半导体有限公司 Thin film structure suitable for copper metallized semiconductor device and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275973A (en) * 1993-03-01 1994-01-04 Motorola, Inc. Method for forming metallization in an integrated circuit
US5592024A (en) * 1993-10-29 1997-01-07 Kabushiki Kaisha Toshiba Semiconductor device having a wiring layer with a barrier layer
US5595937A (en) * 1995-04-13 1997-01-21 Nec Corporation Method for fabricating semiconductor device with interconnections buried in trenches
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5747360A (en) * 1993-09-17 1998-05-05 Applied Materials, Inc. Method of metalizing a semiconductor wafer
JPH07283219A (en) * 1994-04-13 1995-10-27 Sanyo Electric Co Ltd Manufacture of semiconductor device
JP3911643B2 (en) * 1995-07-05 2007-05-09 富士通株式会社 Method for forming buried conductive layer
KR100336655B1 (en) * 1995-12-15 2002-11-07 주식회사 하이닉스반도체 Method for forming metal wiring in semiconductor device
JP4311771B2 (en) * 1996-11-19 2009-08-12 Ｏｋｉセミコンダクタ株式会社 Manufacturing method of semiconductor device
KR19980060532A (en) * 1996-12-31 1998-10-07 김영환 Metal wiring formation method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5275973A (en) * 1993-03-01 1994-01-04 Motorola, Inc. Method for forming metallization in an integrated circuit
US5592024A (en) * 1993-10-29 1997-01-07 Kabushiki Kaisha Toshiba Semiconductor device having a wiring layer with a barrier layer
US5595937A (en) * 1995-04-13 1997-01-21 Nec Corporation Method for fabricating semiconductor device with interconnections buried in trenches
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893433B2 (en) 2001-02-12 2011-02-22 Asm America, Inc. Thin films and methods of making them
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films
US7687383B2 (en) 2005-02-04 2010-03-30 Asm America, Inc. Methods of depositing electrically active doped crystalline Si-containing films
US7816236B2 (en) 2005-02-04 2010-10-19 Asm America Inc. Selective deposition of silicon-containing films
US9190515B2 (en) 2005-02-04 2015-11-17 Asm America, Inc. Structure comprises an As-deposited doped single crystalline Si-containing film
US7863163B2 (en) 2005-12-22 2011-01-04 Asm America, Inc. Epitaxial deposition of doped semiconductor materials
US9312131B2 (en) 2006-06-07 2016-04-12 Asm America, Inc. Selective epitaxial formation of semiconductive films
US8278176B2 (en) 2006-06-07 2012-10-02 Asm America, Inc. Selective epitaxial formation of semiconductor films
US7759199B2 (en) 2007-09-19 2010-07-20 Asm America, Inc. Stressor for engineered strain on channel
US7897491B2 (en) 2007-12-21 2011-03-01 Asm America, Inc. Separate injection of reactive species in selective formation of films
US7655543B2 (en) 2007-12-21 2010-02-02 Asm America, Inc. Separate injection of reactive species in selective formation of films
US8486191B2 (en) 2009-04-07 2013-07-16 Asm America, Inc. Substrate reactor with adjustable injectors for mixing gases within reaction chamber
US8809170B2 (en) 2011-05-19 2014-08-19 Asm America Inc. High throughput cyclical epitaxial deposition and etch process

Also Published As

Publication number Publication date
KR20010001543A (en) 2001-01-05
WO2000075964A2 (en) 2000-12-14

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