WO2000075985A1 - Method for making an integrated circuit portable device with electric conduction paths - Google Patents

Method for making an integrated circuit portable device with electric conduction paths Download PDF

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Publication number
WO2000075985A1
WO2000075985A1 PCT/FR2000/001264 FR0001264W WO0075985A1 WO 2000075985 A1 WO2000075985 A1 WO 2000075985A1 FR 0001264 W FR0001264 W FR 0001264W WO 0075985 A1 WO0075985 A1 WO 0075985A1
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WO
WIPO (PCT)
Prior art keywords
chip
manufacturing
contact pads
chips
paths
Prior art date
Application number
PCT/FR2000/001264
Other languages
French (fr)
Inventor
Jean-Christophe Fidalgo
Bernard Calvas
Original Assignee
Gemplus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus filed Critical Gemplus
Priority to AU45753/00A priority Critical patent/AU4575300A/en
Publication of WO2000075985A1 publication Critical patent/WO2000075985A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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Definitions

  • the present invention relates to a method of manufacturing electronic devices comprising at least one integrated circuit chip connected to a communication interface through electrical conduction paths.
  • the present invention can be applied to devices comprising a single integrated circuit chip connected to a communication interface, the connection pads of which are not opposite the contact pads of the chip. Electrical conduction paths then allow the connection to be made.
  • the present invention advantageously applies to the manufacture of electronic devices comprising a plurality of integrated circuit chips stacked and connected together by electrical conduction paths. It relates more particularly to portable devices with integrated circuits comprising such a stack connected to communication interfaces such as Donner of connection and / or antenna.
  • These electronic devices constitute portable devices for example, such as smart cards with and / or contactless or electronic tags.
  • the present invention applies to electronic devices such as cameras or stacks of memories used in the aerospace field, or even electronics embedded in vehicles, for example.
  • the invention makes it possible to reduce the dimensions of the device for applications in which the overall dimensions must be controlled.
  • FIG. 1 A conventional method for manufacturing a stack of integrated circuits is illustrated in FIG. 1.
  • the integrated circuit chips 10 are superimposed by bonding the rear face of a chip 10 to the active face of the previous one, the contact pads 11 of each chip 10 remaining free to allow connection by wire wiring 17.
  • connection wires 17 and their protection by depositing resin or the like, further increases the volume of the micromodule obtained.
  • Such a method does not make it possible to obtain a compact integrated circuit stack and the number of circuits to be stacked is necessarily limited as and when stacked.
  • stacking is limited to three levels.
  • FIG. 2 illustrates another known method for manufacturing a stack of integrated circuits.
  • the object of the present invention is to overcome the drawbacks of the prior art for the production of integrated circuit stacks.
  • the present invention provides a method of manufacturing a stack of integrated circuits making it possible to combine reliability of the finished product with simplicity and a reduction in the number of manufacturing steps.
  • the present invention proposes to make openings in the cutting paths of a wafer carrying integrated circuit chips, and to make electrical conduction paths between the contact pads of the chips and a connection point located on the back side of the plate.
  • the invention also makes it possible to connect a single integrated circuit chip to a communication interface of a particular design in which the connection pads are not located opposite the contact pads of the chip. Electrical conduction paths then make it possible to make the connection by connecting the contact pads of the chip to connection points situated opposite the pads of the connection to the communication interface.
  • the present invention more particularly relates to a method of manufacturing a device, characterized in that it comprises the following steps: - supply of at least one integrated circuit chip placed on at least one wafer and surrounded by paths cutting; making openings in the cutting paths crossing the wafer; - Realization of electrical conduction paths covering the side of each opening and extending from a contact pad of a chip adjacent to the opening to a connection point of the chip.
  • the connection points are located on the rear face of the chip.
  • connection points are located on the active face of the chip, the electrical conduction path passing through the rear face of the chip.
  • the method according to the invention further comprises the following steps: individualization of a chip by sawing the cutting paths; connection of the contact pads of the chip to a communication interface by placing the connection points of the chip opposite the connection pads of the communication interface.
  • the method further comprises the following steps: individualization of at least two chips by sawing the cutting cnemms; stacking: individualized chips so as to place the connection points and the contact pads of each chip opposite, - connection of the contact pads of the stacked chips through the electrical conduction cnemms.
  • the method further comprises the following steps: stacking the wafers comprising the integrated circuit chips so as to place the connection points and the contact pads of each chip opposite; connection of the contact pads of the stacked chips through the electrical conduction paths; individualization of the chip stacks by sawing the cutting paths of the overlapping wafers.
  • the connections between the contact pads and the connection points of the stacked chips are made by gluing.
  • the bonding is carried out collectively by thermoactivation.
  • connections between the contact pads and the connection points of the stacked chips are made collectively by thermosonic welding.
  • connections between the contact pads and the connection points of the stacked chips are made collectively by thermocompression.
  • connections between the contact pads and the connection points stacked chips are produced collectively by ultrasonic welding.
  • connections between the contact pads and the connection points of the stacked chips are made collectively by remelting an alloy, previously applied to the electrical conduction paths.
  • the openings are drilled at the intersections of the cutting paths. According to another alternative embodiment, the openings are drilled on the edges of the cutting paths, near the contact pads of the chips.
  • the electrical conduction cnemms are made of metallic material.
  • the electrical conduction paths are made of conductive polymer.
  • the present invention also relates to an electronic device comprising at least one integrated circuit chip, characterized in that the contact pads of the chip are connected to a communication interface by electrical conduction paths carried at least in part by the chip.
  • the invention also applies to an electronic device comprising a stack of at least two integrated circuits, characterized in that the connections between the contact pads of the stacked chips are ensured by electrical contact through electrical conduction paths covering each side of the chip and extending from a contact pad to the rear face of the chip.
  • the stack of integrated circuits is connected to a communication interface through at least one of the electrical conduction cr-emms carried at least in part by the chip.
  • the method according to the invention is simple to implement and makes it possible to obtain compact integrated circuit stacks which may have more than three levels.
  • the use of thin circuit boards will allow excellent compactness of the stack.
  • Such stacks can be transferred to a card holder with ISO standard dimensions, that is to say a thickness of 0.76 mm.
  • the manufacturing method according to the invention has the advantage of allowing a collective connection of the superimposed chips, which leads to a saving of time and a reduction in costs.
  • the collective connection of the chips can be carried out after the individualization of the chips and their stacking or before the individualization by stacking the plates.
  • the method of the invention allows a significant gain in materials.
  • the invention also makes it possible to produce contact deviations on a single chip so as to transfer it directly to a communication interface. communication whatever the reason for the connection periods of the latter.
  • the chip or the stack of chips are also easily connected to the communication interface of the device through the electrical conduction paths previously made.
  • FIG. 1, already described, is a diagram in cross section illustrating a traditional method of manufacturing a stack of integrated circuits
  • FIG. 2, described above, is a diagram in cross section illustrating a known method of manufacturing a stack of integrated circuits
  • Figure 3 is a schematic top view of a portion of an integrated circuit board showing the cutting paths
  • FIG. 4 is a schematic top view of an opening made in the cutting paths according to the method of
  • Figure 5 is a schematic top view illustrating the metallization of the contact pads according to the method of the invention.
  • - Figure 6 is a schematic top view illustrating the sawing of the cutting paths according to the method of the invention;
  • Figure 7 is a sectional view of the metallization of the contact pads according to the method of the invention;
  • Figures 8a and 8b are schematic views of different embodiments of metallizations according to the method of the invention.
  • FIG. 9 schematically illustrates the stack of integrated circuits obtained according to the method of the invention, -
  • Figure 10 schematically illustrates a top view of an alternative embodiment of one invention
  • FIG. 11 is a schematic sectional view of FIG. 10.
  • each circuit chip 10 is framed by cutting paths 2 which will guide the sawing of wafer 1 to individualize the integrated circuit chips.
  • Each chip 10 comprises, on its active face, contact pads 11 capable of establishing electrical contact with another chip and / or with a communication interface.
  • FIG. 4 is a close-up of the intersection A between two cutting paths 2.
  • openings 20 are made in the cutting paths 2. These openings 20 pass through the entire thickness of the wafer 1.
  • the opening 20 is made at the intersection A of the cutting paths 2.
  • openings 20 can be drilled in the edges of the cutting paths 2, preferably near the contact pads 11 of the chips 10.
  • the opening 20 of the wafer can be produced by laser cutting, by micro -.smage by electric discharges, or by high pressure water jet, or by any other means known in the state of the art.
  • the opening has a circular shape centered on the intersection A of the cutting paths 2.
  • the opening 20 is made near the contact pads 11 of the four chips 10 having a corner on the intersection A.
  • FIG. 5 illustrates the step of making the electrical conduction paths.
  • These paths 25 are made of a conductive material such as a metal or a conductive polymer for example. In general, these paths 25 cover the sides of the openings 20 and extend from a contact pad 11 adjacent to an opening 20 to a connection point 12.
  • connection points 12 are located on the rear face of the chip 10 or on its front face. To make a stack of integrated circuits, the connection points are preferably located on the rear face of each chip 10. These electrical conduction paths 25 can be produced according to various known techniques.
  • a conductive material can, for example, be printed on a predetermined area of the wafer by serigraphy or by material jet using a printing head.
  • the paths 25 can also be produced, for example, by chemical deposition of conductive material, by electrolysis, by spraying of vaporized conductive material, or also by vacuum evaporation of conductive material.
  • the chips 10 are then individualized by sawing 21 from the cutting paths 2.
  • Sawing 21 also makes it possible to separate the metallized contact pads 11 from one another so that there is no electrical contact between different chips 10 on the same wafer 1.
  • FIG. 7 illustrates in section the area covered by an electrical conduction path 25. This area extends, in a hook, on the contact pads 11 adjacent to the opening 20, on the sides of the opening 20 and on the rear face of the chips in contact with said opening 20 to reach a connection point 12. An electrical contact is thus established between the contact pads 11 of the chips 10 and the connection points 12 of the respective rear faces.
  • FIGS. 8a and 8b illustrate alternative embodiments of the manufacturing method according to the invention with other formats for cutting openings 20 and electrical conduction paths 25.
  • FIG. 8a illustrates an opening 20 of large format pierced in a cross at the intersection of the paths of ⁇ cut 2, with - .. re electrically conductive zone 25 in an arc broken by sawing 21 of the wafer along the cutting paths 2 so as to dissociate each chip 10 and its contacts 11.
  • Such a variant allows great tolerance in positioning during the stacking of integrated circuit chips.
  • FIG. 8b illustrates a variant in which four small openings 20 have been drilled in the cutting paths 2, near the contact pads 11 of each chip 10.
  • An electrically conductive zone 25 therefore covers a tab extending from each pad of contact 11 when opening 20.
  • openings 20 and paths 25 can be envisaged depending on the size and the location of the contact pads 11 on the chips 10.
  • FIG. 9 illustrates the stacking of integrated circuit chips according to the manufacturing method of the invention.
  • the integrated circuit chips 10, individualized by sawing the wafer along the cutting paths 2 are stacked one on the other so as to place the connection points 12 and the contact pads 11 of each chip 10 facing each other. screw.
  • a plurality of plates 1 can be stacked on each other so as to place the connection points 12 and the contact pads 11 of each chip 10 facing each other.
  • stacks of integrated circuits are individualized by sawing the cutting paths 2 of the overlapping plates 1.
  • the connections between the contact pads 11 of the stacked chips 10 are obtained by bonding or by welding the electrical conduction paths 25 or by any other suitable means.
  • connections are made collectively, on the stacked chips 10, using a heat-activated adhesive and by collectively heating the stack of chips 10.
  • glue for the connection of the paths 25, such as an anisotropic conduction glue, or an isotropic conduction glue, or a non-conductive glue which has a strong shrinkage during its polymerization so as to place the contact pads 11 and the connection points 12 facing each other for mechanical contact.
  • connections are made collectively, on the stacked chips 10.
  • the collective connection can be made by ultrasonic welding.
  • a golden metallization, or alummized, for example, is applied to the electrical conduction paths 25 and the stack of chips is vibrated by ultrasound so as to produce a metallic weld of the contacts 11 and of the metallized connection points 12.
  • connection can also be obtained by thermocompression or by thermosonic compression.
  • the connections of the contact pads 11 with the connection points 12 can be made by refusing a plated alloy such as tin / lead for example, activation of the solder being obtained. by local heating of the plating by means of a beam or a laser fiber for example.
  • Figures 10 and 11 illustrate a possible application of the method according to the present invention.
  • connection pads 12 are located on the acti v e of the chip 10.
  • the electrical conduction paths 25 advantageously make it possible to bring the contact pads 11 respectively to connection points 12 at the side opposite the active face of the chip 10, the paths 25 passing through the rear face of the chip 10.
  • connection points 12 are made on the rear face of the chip 10 as previously described.

Abstract

The invention concerns a method for making an integrated circuit portable device, characterised in that it comprises the following steps: providing at least an integrated circuit chip (10) arranged on at least a wafer (1) and surrounded by scribe lines (2); providing orifices (20) in the scribe lines (2) running through the wafer (1); producing an electric conduction path (25) covering the flank of each orifice (20) and extending from one contact pad (11) of a chip (10) adjacent to the orifice (20) up to a connection point (12).

Description

PROCEDE DE FABRICATION DE DISPOSITIF PORTABLE A CIRCUIT INTEGRE AVEC CHEMINS DE CONDUCTION ELECTRIQUEMETHOD FOR MANUFACTURING PORTABLE DEVICE WITH INTEGRATED CIRCUIT WITH ELECTRICAL CONDUCTION PATHS
La présente invention concerne un procédé de fabrication de dispositifs électroniques comportant au moins une puce de circuit: intégré connectée à une interface de communication à travers des chemins de conduction électrique.The present invention relates to a method of manufacturing electronic devices comprising at least one integrated circuit chip connected to a communication interface through electrical conduction paths.
La présente invention peut s'appliquer à des dispositifs comportant une seule puce de circuit intégré reliée à une interface de communication dont les plages de connexion ne se trouvent pas en vis à vis des plots de contact de la puce. Des chemins de conduction électriques permettent alors de réaliser la connexion.The present invention can be applied to devices comprising a single integrated circuit chip connected to a communication interface, the connection pads of which are not opposite the contact pads of the chip. Electrical conduction paths then allow the connection to be made.
La présente invention s'applique avantageusement à la fabrication de dispositifs électroniques comportant une pluralité de puces de circuit intégré empilées et connectées entre elles par des chemins de conduction électrique. Elle vise plus particulièrement des dispositifs portables à circuits intégrés comportant de tels empilement reliés à des interfaces de communication tels que Donner de connexion et/ou antenne .The present invention advantageously applies to the manufacture of electronic devices comprising a plurality of integrated circuit chips stacked and connected together by electrical conduction paths. It relates more particularly to portable devices with integrated circuits comprising such a stack connected to communication interfaces such as Donner of connection and / or antenna.
Ces dispositifs électroniques constituent des dispositifs portables par exemple, tels que des cartes à puce avec et/ou sans contact ou encore des étiquettes électroniques .These electronic devices constitute portable devices for example, such as smart cards with and / or contactless or electronic tags.
La présente invention s'applique aux appareils électroniques tels que des caméras ou des piles de mémoires utilisées dans le domaine de l'aérospatiale, ou encore de l'électronique embarquée dans des véhicules, par exemple. L'invention permet de réduire les dimensions du dispositif pour des applications dans lesquels l'encombrement doit être maîtrisé.The present invention applies to electronic devices such as cameras or stacks of memories used in the aerospace field, or even electronics embedded in vehicles, for example. The invention makes it possible to reduce the dimensions of the device for applications in which the overall dimensions must be controlled.
Un procédé classique de fabrication d'une pile de circuits intégrés est illustré sur la figure 1.A conventional method for manufacturing a stack of integrated circuits is illustrated in FIG. 1.
Les puces de circuit intégré 10 sont superposées par collage de la face arrière d'une puce 10 sur la face active de la précédente, les plots de contact 11 de chaque puce 10 restant dégagés pour permettre une connexion par câblage fîlaire 17.The integrated circuit chips 10 are superimposed by bonding the rear face of a chip 10 to the active face of the previous one, the contact pads 11 of each chip 10 remaining free to allow connection by wire wiring 17.
Ce procédé présente de nombreuses limites. D'une part, la connexion filaire 17 impose de maintenir les plots de contact 11 dégagés, ce qui entraîne une perte d'espace importante et des risques de pollution accrus.This process has many limitations. On the one hand, the wired connection 17 makes it necessary to keep the contact pads 11 free, which results in a significant loss of space and increased risks of pollution.
D'autre part, l'encombrement des fils de connexion 17 et leur protection, par dépôt de résine ou autre, augmente encore le volume du micromodule obtenu. Un tel procédé ne permet pas d'obtenir une pile de circuits intégrés compacte et le nombre de circuits à empiler est nécessairement limité au fur et à mesure de 1 ' empilement .On the other hand, the size of the connection wires 17 and their protection, by depositing resin or the like, further increases the volume of the micromodule obtained. Such a method does not make it possible to obtain a compact integrated circuit stack and the number of circuits to be stacked is necessarily limited as and when stacked.
En générale, l'empilement est limité à trois niveaux.In general, stacking is limited to three levels.
La figure 2 illustre un autre procédé connu de fabrication de pile de circuits intégrés.FIG. 2 illustrates another known method for manufacturing a stack of integrated circuits.
Deux puces de circuit intégré 10 sont superposées, une puce 10 étant retournée de manière à ce que les plots de contact 11 des faces actives des deux puces 10 soient en vis à vis pour une connexion en " flip chip " qu désigne une technique connue de connexion dans laquelle la puce est retournée. Ce procédé présente néanmoins de nombreux inconvénients .Two integrated circuit chips 10 are superimposed, a chip 10 being turned over so that the contact pads 11 of the active faces of the two chips 10 are facing each other for a "flip chip" connection which is a known technique of connection in which the chip is returned. This process nevertheless has many drawbacks.
Un tel empilement est limité à deux puces de circuit intégré. De plus, la connexion des puces par la technique du " flip chip " est de faible cadence.Such a stack is limited to two integrated circuit chips. In addition, the connection of the chips by the "flip chip" technique is slow.
Le but de la présente invention est de pallier aux inconvénients de l'art antérieur pour la réalisation de piles de circuits intégrés.The object of the present invention is to overcome the drawbacks of the prior art for the production of integrated circuit stacks.
A cet effet, la présente invention propose un procédé de fabrication d'une pile de circuits intégrés permettant d'associer une fiabilité du produit fini avec une simplicité et une réduction du nombre d'étapes de fabrication.To this end, the present invention provides a method of manufacturing a stack of integrated circuits making it possible to combine reliability of the finished product with simplicity and a reduction in the number of manufacturing steps.
En particulier, la présente invention propose de réaliser des ouvertures dans les chemins de découpe d'une plaquette portant des puces de circuit intégré, et de réaliser des chemins de conduction électrique entre les plots de contact des puces et un point de connexion situé sur la face arrière de la plaquette.In particular, the present invention proposes to make openings in the cutting paths of a wafer carrying integrated circuit chips, and to make electrical conduction paths between the contact pads of the chips and a connection point located on the back side of the plate.
Des contacts électriques pourront ainsi être étaαlis entre la face active de la puce et sa face arrière pour un empilement d'une pluralité de puces de circuit .Electrical contacts could thus be established between the active face of the chip and its rear face for stacking a plurality of circuit chips.
En outre l'invention permet également de connecter une unique puce de circuit intégré à une interface de communication de conception particulière dans laquelle les plages de connexion ne se situent pas en vis à vis des plots de contact de la puce. Des chemins de conduction électrique permettent alors de réaliser la connexion en reliant les plots αe contact de la puce à des points de connexion situés en vis à vis des plages αe connexion αe l'interface de communication. La présente invention a plus particulièrement pour objet un procédé de fabrication d'un dispositif, caractérisé en ce qu' il comporte les étapes suivantes : - fourniture d'au moins une puce de circuit intégré disposée sur au moins une plaquette et entourée par des chemins de découpe ; réalisation d'ouvertures dans les chemins de découpe traversant la plaquette ; - réalisation de chemins de conduction électrique couvrant le flanc de chaque ouverture et s'étendant d'un plot de contact d'une puce adjacent à l'ouverture jusqu'à un point de connexion de la puce. Selon une première variante, les points de connexion sont situés sur la face arrière de la puce.In addition, the invention also makes it possible to connect a single integrated circuit chip to a communication interface of a particular design in which the connection pads are not located opposite the contact pads of the chip. Electrical conduction paths then make it possible to make the connection by connecting the contact pads of the chip to connection points situated opposite the pads of the connection to the communication interface. The present invention more particularly relates to a method of manufacturing a device, characterized in that it comprises the following steps: - supply of at least one integrated circuit chip placed on at least one wafer and surrounded by paths cutting; making openings in the cutting paths crossing the wafer; - Realization of electrical conduction paths covering the side of each opening and extending from a contact pad of a chip adjacent to the opening to a connection point of the chip. According to a first variant, the connection points are located on the rear face of the chip.
Selon une seconde variante, les points de connexion sont situés sur la face active de la puce, le chemin de conduction électrique traversant la face arrière de la puce .According to a second variant, the connection points are located on the active face of the chip, the electrical conduction path passing through the rear face of the chip.
Selon un premier mode de réalisation, le procédé selon l'invention comporte en outre les étapes suivantes : individualisation d'une puce par sciage des chemins de découpe ; connexion des plots de contact de la puce à une interface de communication en plaçant les points de connexion de la puce en vis à vis des plages de connexion de l'interface de communication.According to a first embodiment, the method according to the invention further comprises the following steps: individualization of a chip by sawing the cutting paths; connection of the contact pads of the chip to a communication interface by placing the connection points of the chip opposite the connection pads of the communication interface.
Selon un deuxième mode de réalisation, le procédé comporte en outre les étapes suivantes : individualisation d'au moins deux puces par sciaσe des cnemms de découpe ; empilement: des puces individualisées de manière à placer les points de connexion et les plots de contact de cnaque puce en vis à vis ,- connexion des plots de contact des puces empilées à travers les cnemms de conduction électrique . Selon un troisième moαe de réalisation, le procédé comporte en outre les étapes suivantes : empilement des plaquettes comportant les puces de circuit intégré de manière à placer les points de connexion et les plots de contact de chaque puce en vis à vis ; connexion des plots de contact des puces empilées à travers les chemin de conduction électrique ; individualisation des piles de puces par sciage des chemins de découpe des plaquettes superposées .According to a second embodiment, the method further comprises the following steps: individualization of at least two chips by sawing the cutting cnemms; stacking: individualized chips so as to place the connection points and the contact pads of each chip opposite, - connection of the contact pads of the stacked chips through the electrical conduction cnemms. According to a third embodiment, the method further comprises the following steps: stacking the wafers comprising the integrated circuit chips so as to place the connection points and the contact pads of each chip opposite; connection of the contact pads of the stacked chips through the electrical conduction paths; individualization of the chip stacks by sawing the cutting paths of the overlapping wafers.
Selon une caractéristique, les connexions entre les plots de contact et les points de connexion des puces empilées sont réalisées par collage.According to one characteristic, the connections between the contact pads and the connection points of the stacked chips are made by gluing.
Selon une particularité de réalisation, le collage est réalisé collectivement par thermoactivation.According to a particular feature, the bonding is carried out collectively by thermoactivation.
Selon une autre caractéristique, que les connexions entre les plots de contact et les points de connexion des puces empilées sont réalisées collectivement par soudure thermosonique .According to another characteristic, that the connections between the contact pads and the connection points of the stacked chips are made collectively by thermosonic welding.
Selon une autre caractéristique, les connexions entre les plots de contact et les points de connexion des puces empilées sont réalisées collectivement par thermocompression.According to another characteristic, the connections between the contact pads and the connection points of the stacked chips are made collectively by thermocompression.
Selon une autre caractéristique, les connexions entre les plots de contact et les points de connexion des puces empilées sont réalisées collectivement par soudure ultrasomque .According to another characteristic, the connections between the contact pads and the connection points stacked chips are produced collectively by ultrasonic welding.
Selon une autre caractéristique, les connexions entre les plots de contact et les points de connexion des puces empilées sont réalisées collectivement par réfusion d'un alliage, préalablement appliqué sur les chemins de conduction électrique.According to another characteristic, the connections between the contact pads and the connection points of the stacked chips are made collectively by remelting an alloy, previously applied to the electrical conduction paths.
Selon une variante de réalisation, les ouvertures sont percées aux intersections des chemins de découpe. Selon une autre variante de réalisation, les ouvertures sont percées sur les bords des chemins de découpe, à proximité des plots de contact des puces.According to an alternative embodiment, the openings are drilled at the intersections of the cutting paths. According to another alternative embodiment, the openings are drilled on the edges of the cutting paths, near the contact pads of the chips.
Selon une variante, les cnemms de conduction électrique sont réalisés en matériau métallique. Selon une autre variante, les chemins de conduction électrique sont réalisés en polymère conducteur.According to a variant, the electrical conduction cnemms are made of metallic material. According to another variant, the electrical conduction paths are made of conductive polymer.
La présente invention concerne également un dispositif électronique comportant au moins une puce de circuit intégré, caractérisé en ce que les plots de contact de la puce sont reliés à une interface de communication par des chemins de conduction électrique portés au moins en partie par la puce.The present invention also relates to an electronic device comprising at least one integrated circuit chip, characterized in that the contact pads of the chip are connected to a communication interface by electrical conduction paths carried at least in part by the chip.
L'invention s'applique en outre à un dispositif électronique comportant une pile d'au moins deux circuits intégrés, caractérisée en ce que les connexions entre les plots de contact des puces empilées sont assurées par contact électrique à travers des chemins de conduction électrique couvrant chacun le flanc de la puce et s'étendant d'un plot de contact jusque sur la face arrière de la puce.The invention also applies to an electronic device comprising a stack of at least two integrated circuits, characterized in that the connections between the contact pads of the stacked chips are ensured by electrical contact through electrical conduction paths covering each side of the chip and extending from a contact pad to the rear face of the chip.
Selon une caractéristique, la pile de circuits intégrés est connectée à une interface de communication à travers au moins un des cr-emms de conduction électrique portés au moins en partie par la puce.According to one characteristic, the stack of integrated circuits is connected to a communication interface through at least one of the electrical conduction cr-emms carried at least in part by the chip.
Le procédé selon l'invention est simple à mettre en oeuvre et permet d'obtenir des piles de circuits intégrés compactes pouvant avoir plus de trois niveaux.The method according to the invention is simple to implement and makes it possible to obtain compact integrated circuit stacks which may have more than three levels.
En particulier, l'utilisation de plaquettes de circuits fines permettra une excellente compacité de 1 ' empilement . De telles piles peuvent être reportées dans un support de carte aux dimensions standards ISO, soit d'une épaisseur de 0.76 mm.In particular, the use of thin circuit boards will allow excellent compactness of the stack. Such stacks can be transferred to a card holder with ISO standard dimensions, that is to say a thickness of 0.76 mm.
De plus, le procédé de fabrication selon l'invention présente l'avantage de permettre une connexion collective des puces superposées, ce qui entraîne un gain de temps et une réduction des coûts.In addition, the manufacturing method according to the invention has the advantage of allowing a collective connection of the superimposed chips, which leads to a saving of time and a reduction in costs.
La connexion collective des puces peut être réalisée après l'individualisation des puces et leur empilement ou avant l'individualisation en empilant les plaquettes .The collective connection of the chips can be carried out after the individualization of the chips and their stacking or before the individualization by stacking the plates.
En outre, le procédé de l'invention permet un gain de matières important.In addition, the method of the invention allows a significant gain in materials.
De plus, les caractéristiques électriques de la pile de circuits obtenue seront meilleures que celles obtenues par câblage filaire. On obtient en effet des caractéristiques comparables à celles obtenues par une connexion " flip chip " .In addition, the electrical characteristics of the circuit stack obtained will be better than those obtained by wire wiring. Characteristics comparable to those obtained by a "flip chip" connection are indeed obtained.
Dans une variante de réalisation, il est également possible de réaliser une antenne directement sur une face de la puce afin d'obtenir un micro empilement sans contact .In an alternative embodiment, it is also possible to produce an antenna directly on one face of the chip in order to obtain a contactless micro stack.
L' invention permet en outre de réaliser des déviations de contact sur une puce unique de manière à la reporter directement sur une interface de communication quelque soit le motif des plages de connexion de cette dernière.The invention also makes it possible to produce contact deviations on a single chip so as to transfer it directly to a communication interface. communication whatever the reason for the connection periods of the latter.
La puce ou la pile de puces sont en outre facilement connectées à l'interface de communication du dispositif à travers les chemins de conduction électrique précédemment réalisés.The chip or the stack of chips are also easily connected to the communication interface of the device through the electrical conduction paths previously made.
D'autres particularités et avantages de l'invention apparaîtront à la lecture de la description donnée à titre d'exemple illustratif et non limitatif et faite en référence aux figures annexées qui représentent :Other features and advantages of the invention will appear on reading the description given by way of illustrative and nonlimiting example and made with reference to the appended figures which represent:
La figure 1, déjà décrite, est un schéma en coupe transversale illustrant un procédé traditionnel de fabrication de pile de circuits intégrés ;FIG. 1, already described, is a diagram in cross section illustrating a traditional method of manufacturing a stack of integrated circuits;
La figure 2, dé à décrite, est un schéma en coupe transversale illustrant un procédé connu de fabrication de pile de circuits intégrés ;FIG. 2, described above, is a diagram in cross section illustrating a known method of manufacturing a stack of integrated circuits;
La figure 3 est une vue schématique de dessus d'une portion d'une plaquette de circuits intégrés faisant apparaître les chemins de découpe ;Figure 3 is a schematic top view of a portion of an integrated circuit board showing the cutting paths;
La figure 4 est une vue schématique de dessus d'une ouverture pratiquée dans les chemins de découpe selon le procédé deFIG. 4 is a schematic top view of an opening made in the cutting paths according to the method of
1 ' invention ;The invention;
La figure 5 est une vue schématique de dessus illustrant la métallisation des plots de contact selon le procédé de l'invention ; - La figure 6 est une vue schématique de dessus illustrant le sciage des chemins de découpes selon le procédé de l'invention ; La figure 7 est une vue en coupe αe la métallisation des plots de contact selon le procédé de l'invention ;Figure 5 is a schematic top view illustrating the metallization of the contact pads according to the method of the invention; - Figure 6 is a schematic top view illustrating the sawing of the cutting paths according to the method of the invention; Figure 7 is a sectional view of the metallization of the contact pads according to the method of the invention;
Les figures 8a et 8b sont des vues schématiques de différentes variantes de réalisation des métallisations selon le procédé de l'invention ;Figures 8a and 8b are schematic views of different embodiments of metallizations according to the method of the invention;
La figure 9 illustre schématiquement l'empilement des circuits intégrés obtenu selon le procédé de l'invention , -FIG. 9 schematically illustrates the stack of integrated circuits obtained according to the method of the invention, -
La figure 10 illustre schématiquement une vue de dessus d'une variante de réalisation de 1 ' invention ;Figure 10 schematically illustrates a top view of an alternative embodiment of one invention;
La figure 11 est une vue schématique en coupe de la figure 10.FIG. 11 is a schematic sectional view of FIG. 10.
En se référant à la figure 3, qui illustre une portion de plaquette 1 de circuits intégrés, chaque puce de circuit 10 est encadrée par des chemins de découpe 2 qui guideront le sciage de la plaquette 1 pour individualiser les puces de circuit intégré.Referring to Figure 3, which illustrates a portion of wafer 1 of integrated circuits, each circuit chip 10 is framed by cutting paths 2 which will guide the sawing of wafer 1 to individualize the integrated circuit chips.
Chaque puce 10 comprend, sur sa face active, des plots de contact 11 aptes à établir un contact électrique avec une autre puce et/ou avec une interface de communication.Each chip 10 comprises, on its active face, contact pads 11 capable of establishing electrical contact with another chip and / or with a communication interface.
La figure 4 est un gros plan de l'intersection A entre deux chemins de découpe 2.FIG. 4 is a close-up of the intersection A between two cutting paths 2.
Selon une caractéristique essentielle du procédé selon l'invention, des ouvertures 20 sont réalisées dans les chemins de découpe 2. Ces ouvertures 20 traversent toute l'épaisseur de la plaquette 1.According to an essential characteristic of the method according to the invention, openings 20 are made in the cutting paths 2. These openings 20 pass through the entire thickness of the wafer 1.
Selon le mode de réalisation illustré sur la figure 4, l'ouverture 20 est réalisée à l'intersection A des chemins de découpe 2. Selon d'autres modes αe réalisation, des ouvertures 20 peuvent être percées dans les oords des chemins de découpe 2, préférentiellement à proximité des plots de contact 11 des puces 10. L'ouverture 20 de la plaquette peut être réalisée par découpe laser, par micro -.smage par décharges électriques, ou par jet d'eau haute pression, ou encore par tout autre moyen connu dans l'état de la technique. Sur la variante illustrée sur la figure 4, l'ouverture présente une forme circulaire centrée sur l'intersection A des chemins de découpe 2.According to the embodiment illustrated in FIG. 4, the opening 20 is made at the intersection A of the cutting paths 2. According to other embodiments, openings 20 can be drilled in the edges of the cutting paths 2, preferably near the contact pads 11 of the chips 10. The opening 20 of the wafer can be produced by laser cutting, by micro -.smage by electric discharges, or by high pressure water jet, or by any other means known in the state of the art. In the variant illustrated in FIG. 4, the opening has a circular shape centered on the intersection A of the cutting paths 2.
Avantageusement, l'ouverture 20 est réalisée à proximité des plots de contact 11 des quatre puces 10 présentant un coin sur l'intersection A. La figure 5 illustre l'étape de réalisation des chemins de conduction électrique.Advantageously, the opening 20 is made near the contact pads 11 of the four chips 10 having a corner on the intersection A. FIG. 5 illustrates the step of making the electrical conduction paths.
Ces chemins 25 sont réalisés dans un matériau conducteur tel qu'un métal ou un polymère conducteur par exemple. De manière générale, ces chemins 25 couvrent les flancs des ouvertures 20 et s'étendent d'un plot de contact 11 adjacent à une ouverture 20 jusqu'à un point de connexion 12.These paths 25 are made of a conductive material such as a metal or a conductive polymer for example. In general, these paths 25 cover the sides of the openings 20 and extend from a contact pad 11 adjacent to an opening 20 to a connection point 12.
Selon les applications du procédé, les points de connexion 12 se situent sur la face arrière de la puce 10 ou sur sa face avant. Pour réaliser une pile de circuits intégrés, les points de connexions se trouvent préférentiellement sur la face arrière de chaque puce 10. Ces chemins de conduction électrique 25 peuvent être réalisés selon différentes techniques connues.Depending on the applications of the method, the connection points 12 are located on the rear face of the chip 10 or on its front face. To make a stack of integrated circuits, the connection points are preferably located on the rear face of each chip 10. These electrical conduction paths 25 can be produced according to various known techniques.
Une matière conductrice peut, par exemple, être imprimée sur une zone prédéterminée de la plaquette par sérigraphie ou par jet de matière à l'aide d'une tête α' impression .A conductive material can, for example, be printed on a predetermined area of the wafer by serigraphy or by material jet using a printing head.
Les chemins 25 peuvent également être réalisés, par exemple, par dépôt cnimique de matière conductrice, par électrolyse, par pulvérisation de matière conductrice vaporisée, ou encore par évaporation sous vide de matière conductrice.The paths 25 can also be produced, for example, by chemical deposition of conductive material, by electrolysis, by spraying of vaporized conductive material, or also by vacuum evaporation of conductive material.
D'autres techniques de dépôt de matière conductrice peuvent être envisagées par un homme du métier tout en restant dans le cadre de cette invention.Other techniques for depositing conductive material can be envisaged by a person skilled in the art while remaining within the scope of this invention.
Comme illustré sur la figure 6, les puces 10 sont ensuite individualisées par sciage 21 des chemins de découpe 2.As illustrated in FIG. 6, the chips 10 are then individualized by sawing 21 from the cutting paths 2.
Le sciage 21 permet également de dissocier les plots de contact 11 métallisés les uns des autres afin qu'il n'y ait aucun contact électrique entre des puces 10 différentes sur la même plaquette 1.Sawing 21 also makes it possible to separate the metallized contact pads 11 from one another so that there is no electrical contact between different chips 10 on the same wafer 1.
La figure 7 illustre en coupe la zone couverte par un chemin de conduction électrique 25. Cette zone s'étend, en crochet, sur les plots de contact 11 adjacents à l'ouverture 20, sur les flancs de l'ouverture 20 et sur la face arrière des puces en contact avec ladite ouverture 20 pour atteindre un point de connexion 12. Un contact électrique est ainsi établit entre les plots de contact 11 des puces 10 et les points de connexion 12 des faces arrières respectives.FIG. 7 illustrates in section the area covered by an electrical conduction path 25. This area extends, in a hook, on the contact pads 11 adjacent to the opening 20, on the sides of the opening 20 and on the rear face of the chips in contact with said opening 20 to reach a connection point 12. An electrical contact is thus established between the contact pads 11 of the chips 10 and the connection points 12 of the respective rear faces.
Les figures 8a et 8b illustrent des variantes de réalisation du procédé de fabrication selon l'invention avec d'autres formats de découpe d'ouvertures 20 et de chemins de conduction électrique 25.FIGS. 8a and 8b illustrate alternative embodiments of the manufacturing method according to the invention with other formats for cutting openings 20 and electrical conduction paths 25.
La figure 8a illustre une ouverture 20 de grand format percée en croix à l'intersection des chemins de αécoupe 2, avec -..r-e zone électriquement conductrice 25 en arc de cercle rompue par le sciage 21 de la plaquette le long des chemin de découpe 2 de manière à dissocier chaque puce 10 et ses contact 11.FIG. 8a illustrates an opening 20 of large format pierced in a cross at the intersection of the paths of αcut 2, with - .. re electrically conductive zone 25 in an arc broken by sawing 21 of the wafer along the cutting paths 2 so as to dissociate each chip 10 and its contacts 11.
Une telle variante permet une grande tolérance dans le positionnement lors αe l'empilement des puces de circuit intégré.Such a variant allows great tolerance in positioning during the stacking of integrated circuit chips.
La figure 8b illustre une variante dans laquelle quatre petites ouvertures 20 ont été percées dans les chemins de découpe 2 , à proximité des plots de contact 11 de chaque puce 10. Une zone électriquement conductrice 25 couvre donc une languette s'étendant de chaque plot de contact 11 à l'ouverture 20.FIG. 8b illustrates a variant in which four small openings 20 have been drilled in the cutting paths 2, near the contact pads 11 of each chip 10. An electrically conductive zone 25 therefore covers a tab extending from each pad of contact 11 when opening 20.
Dans cette variante le sciage 21 de la plaquette le long des chemins de découpe 2 permettra uniquement d' individualiser les puces 10 sans rompre les chemins de conduction électrique 25 comme c'était le cas dans les autres variantes décrites .In this variant the sawing 21 of the wafer along the cutting paths 2 will only allow the chips 10 to be individualized without breaking the electrical conduction paths 25 as was the case in the other variants described.
D'autre formes de réalisation d'ouvertures 20 et de chemins 25 peuvent être envisagées selon la taille et l'emplacement des plots de contact 11 sur les puces 10.Other embodiments of openings 20 and paths 25 can be envisaged depending on the size and the location of the contact pads 11 on the chips 10.
La figure 9 illustre l'empilement des puces de circuit intégré selon le procédé de fabrication de 1 ' invention. Les puces de circuit intégré 10, individualisées par sciage de la plaquette le long des chemins de découpe 2, sont empilées les unes sur les autres de manière à placer les points de connexion 12 et les plots de contact 11 de chaque puce 10 en vis à vis. Selon un autre mode de réalisation, une pluralité de plaquettes 1 peuvent être empilées les unes sur les autres de manière à placer les points de connexion 12 et les plots de contact 11 de chaque puce 10 en vis à Après connexion des plots de contact 11 entre eux, des piles de circuits intégrés sont individualisées par sciage des chemins de découpes 2 des plaquettes 1 superposées . Les connexions entre les plots de contact 11 des puces 10 empilées sont obtenues par collage ou par soudure des chemins de conduction électrique 25 ou par tout autre moyen adapté .FIG. 9 illustrates the stacking of integrated circuit chips according to the manufacturing method of the invention. The integrated circuit chips 10, individualized by sawing the wafer along the cutting paths 2, are stacked one on the other so as to place the connection points 12 and the contact pads 11 of each chip 10 facing each other. screw. According to another embodiment, a plurality of plates 1 can be stacked on each other so as to place the connection points 12 and the contact pads 11 of each chip 10 facing each other. After connection of the contact pads 11 with each other, stacks of integrated circuits are individualized by sawing the cutting paths 2 of the overlapping plates 1. The connections between the contact pads 11 of the stacked chips 10 are obtained by bonding or by welding the electrical conduction paths 25 or by any other suitable means.
Selon un mode de réalisation préférentiel, les connexions sont effectuées collectivement, sur les puces 10 empilées, en utilisant une colle thermoactivable et en chauffant collectivement la pile de puces 10.According to a preferred embodiment, the connections are made collectively, on the stacked chips 10, using a heat-activated adhesive and by collectively heating the stack of chips 10.
Selon d'autre modes de réalisation, il est envisageable d'utiliser différents types de colle pour la connexion des chemins 25, tel qu'une colle à conduction anisotropique , ou une colle à conduction isotropique, ou une colle non conductrice qui présente un fort retrait lors de sa polymérisation de manière à placer les plots de contact 11 et les points de connexion 12 en vis à vis pour un contact mécanique.According to other embodiments, it is possible to use different types of glue for the connection of the paths 25, such as an anisotropic conduction glue, or an isotropic conduction glue, or a non-conductive glue which has a strong shrinkage during its polymerization so as to place the contact pads 11 and the connection points 12 facing each other for mechanical contact.
Selon un autre mode de réalisation préférentiel, les connexions sont effectuées collectivement, sur les puce 10 empilées. La connexion collective peut être réalisée par soudure ultrasonique . Une métallisation dorée, ou alummisée, par exemple, est appliquée sur les chemins de conduction électrique 25 et la pile de puces est mise en vibration par ultrasons de manière à réaliser une soudure mtermétallique des contacts 11 et des points de connexion 12 métallisés .According to another preferred embodiment, the connections are made collectively, on the stacked chips 10. The collective connection can be made by ultrasonic welding. A golden metallization, or alummized, for example, is applied to the electrical conduction paths 25 and the stack of chips is vibrated by ultrasound so as to produce a metallic weld of the contacts 11 and of the metallized connection points 12.
La connexion collective peut également être obtenue par thermocompression ou par compression thermosonique . Selon d'autre modes de réalisation, les connexions des plots de contact 11 avec les points de connexion 12 peuvent être ootenues par refusicn d'un alliage plaqué tel que de 1 ' étam/plomb par exemple, l'activation de la soudure étant obtenu par chauffage local du plaquage au moyen d'un faisceau ou d'une fibre laser par exemple .Collective connection can also be obtained by thermocompression or by thermosonic compression. According to other embodiments, the connections of the contact pads 11 with the connection points 12 can be made by refusing a plated alloy such as tin / lead for example, activation of the solder being obtained. by local heating of the plating by means of a beam or a laser fiber for example.
Les figures 10 et 11 illustrent une application possible du procédé selon la présente invention.Figures 10 and 11 illustrate a possible application of the method according to the present invention.
Dans une telle application, les plots de connexion 12 sont situés sur la face active de la puce 10. Les chemins de conduction électrique 25 permettent avantageusement d'amener les plots de contact 11 respectivement vers des points de connexion 12 situés sur le côté opposé de la face active de la puce 10, les chemins 25 passant par la face arrière de la puce 10.In such an application, the connection pads 12 are located on the acti v e of the chip 10. The electrical conduction paths 25 advantageously make it possible to bring the contact pads 11 respectively to connection points 12 at the side opposite the active face of the chip 10, the paths 25 passing through the rear face of the chip 10.
Cette application permet essentiellement de réaliser une connexion directe entre la puce 10 et une interface de communication quelque soit le motif des plages de connexion de cette dernière, l'emplacement des points de connexion 12 étant défini de manière à se trouver respectivement en vis à vis des plages de connexion de ladite interface. Une autre application possible du procédé selon l'invention, non illustré, consiste à réaliser les points de connexion 12 sur la face arrière de la puce 10 comme cela a précédemment été décrit.This application essentially makes it possible to make a direct connection between the chip 10 and a communication interface whatever the pattern of the connection pads of the latter, the location of the connection points 12 being defined so as to be respectively opposite connection pads of said interface. Another possible application of the method according to the invention, not illustrated, consists in making the connection points 12 on the rear face of the chip 10 as previously described.
Cependant, plutôt que de réaliser un empilement de puces 10, une unique puce est reportée directement sur une interface de communication. Ce report ne nécessite aucun câblage filaire, ni de retournement de la puce. However, rather than making a stack of chips 10, a single chip is transferred directly to a communication interface. This postponement does not require any wired wiring, nor the flipping of the chip.

Claims

REVEND I C AT I ONS RESELL IC AT I ONS
1. Procédé de fabrication d'un dispositif portable à circuit intégré, caractérisé en ce qu'il comporte les étapes suivantes : - fourniture d'au moins une puce de circuit intégré (10) disposée sur au moins une plaquette (1) et entourée par des chemins de découpe (2) ; réalisation d'ouvertures (20) dans les chemins de découpe (2) traversant la plaquette (1) ; réalisation de chemins de conduction électrique (25) couvrant le flanc de chaque ouverture (20) et s'étendant d'un plot de contact (11) d'une puce (10) adjacent à l'ouverture (20) jusqu'à un point de connexion1. Method of manufacturing a portable integrated circuit device, characterized in that it comprises the following steps: - supply of at least one integrated circuit chip (10) disposed on at least one wafer (1) and surrounded by cutting paths (2); making openings (20) in the cutting paths (2) passing through the wafer (1); production of electrical conduction paths (25) covering the side of each opening (20) and extending from a contact pad (11) of a chip (10) adjacent to the opening (20) up to a connection point
(12) de la puce (10) .(12) of the chip (10).
2. Procédé de fabrication selon la revendication 1, caractérisé en ce que les points de connexion (12) sont situés sur la face arrière de la puce (10) .2. Manufacturing method according to claim 1, characterized in that the connection points (12) are located on the rear face of the chip (10).
3. Procédé de fabrication selon la revendication 1, caractérisé en ce que les points de connexion (12) sont situés sur la face active de la puce (10) , le chemin de conduction électrique (25) traversant la face arrière de la puce ( 10 ) .3. Manufacturing method according to claim 1, characterized in that the connection points (12) are located on the active face of the chip (10), the electrical conduction path (25) passing through the rear face of the chip ( 10).
4. Procédé de fa rication selon l'une des revendications 1 à 3, caractérisé en ce qu'il comporte en outre les étapes suivantes : individualisation d'une puce (10) par sciage des chemins de découpe (2) connexion des plots de contact (111 de la puce (10) à une interface de communication en plaçant les points de connexion (12) de la puce4. Fa rication method according to one of claims 1 to 3, characterized in that it further comprises the following steps: individualization of a chip (10) by sawing the cutting paths (2) connection of the contact pads (111 of the chip (10) to a communication interface by placing the connection points (12) of the chip
(10) en vis à vis des plages de connexion de l'interface de communication.(10) opposite the connection pads of the communication interface.
5. Procédé de fabrication selon la revendication 2, caractérisé en ce qu'il comporte en outre les étapes suivantes : - individualisation d'au moins deux puces5. Manufacturing method according to claim 2, characterized in that it further comprises the following steps: - individualization of at least two chips
(10) par sciage des chemins de découpe (2) ; empilement des puces (10) individualisées de manière à placer les points de connexion (12) et les plots de contact (11) de chaque puce (10)
Figure imgf000017_0001
connexion des plots de contact (11) des puces (10) empilées à travers les chemins de conduction électrique (25) .(10) by sawing the cutting paths (2); stacking of individual chips (10) so as to place the connection points (12) and the contact pads (11) of each chip (10)
Figure imgf000017_0001
connection of the contact pads (11) of the chips (10) stacked through the electrical conduction paths (25).
6. Procédé de fabrication selon la revendication 2, une pluralité de plaquettes (1) comportant chacune une pluralité de puces (10) , caractérisé en ce qu'il comporte en outre les étapes suivantes : empilement des plaquettes (1) comportant les puces (10) de circuit intégré de manière à placer les points de connexion (12) et les plots de contact (11) de chaque puce (10) en vis à
Figure imgf000017_0002
connexion des plots de contact (11) des puces (10) empilées à travers les chemin de conduction électrique (25) ; individualisation des piles de puces (10) par sciage des chemins de découpe (2) des plaquettes (1) superposées. 6. The manufacturing method according to claim 2, a plurality of wafers (1) each comprising a plurality of chips (10), characterized in that it further comprises the following steps: stacking of wafers (1) comprising the chips ( 10) of an integrated circuit so as to place the connection points (12) and the contact pads (11) of each chip (10) opposite
Figure imgf000017_0002
connection of the contact pads (11) of the chips (10) stacked through the electrical conduction paths (25); individualization of the chip stacks (10) by sawing the cutting paths (2) of the overlapping wafers (1).
7. Procédé de fabrication selon l'une quelconque des revendications 5 à 6, caractérisé en ce que les connexions entre les plots de contact (11) et les points de connexion (12) des puces (10) empilées sont réalisées par collage.7. The manufacturing method according to any one of claims 5 to 6, characterized in that the connections between the contact pads (11) and the connection points (12) of the stacked chips (10) are made by bonding.
8. Procédé de fabrication selon la revendication 7, caractérisé en ce que le collage est réalisé collectivement par thermoactivation.8. The manufacturing method according to claim 7, characterized in that the bonding is carried out collectively by thermoactivation.
9. Procédé de fabrication selon l'une quelconque des revendications 5 à 6, caractérisé en ce que les connexions entre les plots de contact (11) et les points de connexion (12) des puces (10) empilées sont réalisées collectivement par soudure thermosonique .9. Manufacturing method according to any one of claims 5 to 6, characterized in that the connections between the contact pads (11) and the connection points (12) of the stacked chips (10) are made collectively by thermosonic welding .
10. Procédé de fabrication selon l'une quelconque des revendications 5 à 6 caractérisé en ce que les connexions entre les plots de contact (11) et les points de connexion (12) des puces (10) empilées sont réalisées collectivement par thermocompression.10. The manufacturing method according to any one of claims 5 to 6 characterized in that the connections between the contact pads (11) and the connection points (12) of the stacked chips (10) are made collectively by thermocompression.
11. Procédé de fabrication selon l'une quelconque des revendications 5à 6 caractérisé en ce que les connexions entre les plots de contact (11) et les points de connexion (12) des puces (10) empilées sont réalisées collectivement par soudure ultrasonique .11. The manufacturing method according to any one of claims 5 to 6 characterized in that the connections between the contact pads (11) and the connection points (12) of the stacked chips (10) are made collectively by ultrasonic welding.
12. Procédé de fabrication selon l'une quelconque des revendications 5 à 6, caractérisé en ce que les connexions entre les plots de contact (11) et les points de connexion (12) des puces (10) empilées sont réalisées collectivement par réfusion d'un alliage, préalablement appliqué sur les cr-emms de conduction électrique (25) .12. The manufacturing method according to any one of claims 5 to 6, characterized in that the connections between the contact pads (11) and the connection points (12) of the stacked chips (10) are made collectively by reflow d 'an alloy, previously applied to the electrical conduction cr-emms (25).
13. Procédé de fabrication selon l'une quelconque des revendications 1 à 12 , caractérisé en ce que les ouvertures (20) sont percées aux intersections des chemins de découpe (2) .13. The manufacturing method according to any one of claims 1 to 12, characterized in that the openings (20) are drilled at the intersections of the cutting paths (2).
14. Procédé de fabrication selon l'une quelconque des revendications 1 à 12 , caractérisé en ce que les ouvertures (20) sont percées sur les bords des chemins de découpe (2) , à proximité des plots de contact (11) des puces (10) .14. The manufacturing method according to any one of claims 1 to 12, characterized in that the openings (20) are drilled on the edges of the cutting paths (2), near the contact pads (11) of the chips ( 10).
15. Procédé de fabrication selon l'une quelconque des revendications 1 à 14 , caractérisé en ce que les chemins de conduction électrique (25) sont réalisés en matériau métallique.15. The manufacturing method according to any one of claims 1 to 14, characterized in that the electrical conduction paths (25) are made of metallic material.
16. Procédé de fabrication selon l'une quelconque des revendications 1 à 14 , caractérisé en ce que les chemins de conduction électrique (25) sont réalisés en polymère conducteur.16. The manufacturing method according to any one of claims 1 to 14, characterized in that the electrical conduction paths (25) are made of conductive polymer.
17. Dispositif électronique comportant au moins une puce de circuit intégré, caractérisé en ce que les plots de contact (11) de la puce (10) sont reliés à une interface de communication par des chemins de conduction électrique (25) portés au moins en partie par la puce (10) .17. Electronic device comprising at least one integrated circuit chip, characterized in that the contact pads (11) of the chip (10) are connected to a communication interface by electrical conduction paths (25) carried at least in part by the chip (10).
18. Dispositif électronique comportant une pile d'au moins deux circuits intégrés, caractérisée en ce que les connexions entre les plots de contact (11) des puces (10) empilées sont assurées par contact électrique à travers αes chemins de conduction électrique (25) couvrant chacun le flanc de la puce18. Electronic device comprising a battery of at least two integrated circuits, characterized in that the connections between the contact pads (11) of the stacked chips (10) are ensured by electrical contact through the electrical conduction paths (25) each covering the flank of the chip
(10) et s'étendant d'un p--ot de contact (11) jusque sur la face arrière de la puce (10) .(10) and extending from a contact point (11) to the rear face of the chip (10).
19 Dispositif électronique selon la revendication19 Electronic device according to claim
18, caractérisé en ce que la pile de circuits intégrés est connectée à une interface de communication à travers au moins un des chemins de conduction électrique (25) portés au moins en partie par la puce18, characterized in that the stack of integrated circuits is connected to a communication interface through at least one of the electrical conduction paths (25) carried at least in part by the chip
(10) .(10).
20. Dispositif électronique selon l'une des revendications 17 ou 19, tel qu'un support à puce, un module électronique, une carte à puce, caractérisé en ce que l'interface de communication est de type avec et/ou sans contact. 20. Electronic device according to one of claims 17 or 19, such as a chip carrier, an electronic module, a chip card, characterized in that the communication interface is of the contact and / or contactless type.
PCT/FR2000/001264 1999-06-04 2000-05-11 Method for making an integrated circuit portable device with electric conduction paths WO2000075985A1 (en)

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