WO2000077831A3 - Methods for regulating surface sensitivity of insulating films in semiconductor devices - Google Patents

Methods for regulating surface sensitivity of insulating films in semiconductor devices Download PDF

Info

Publication number
WO2000077831A3
WO2000077831A3 PCT/US2000/015851 US0015851W WO0077831A3 WO 2000077831 A3 WO2000077831 A3 WO 2000077831A3 US 0015851 W US0015851 W US 0015851W WO 0077831 A3 WO0077831 A3 WO 0077831A3
Authority
WO
WIPO (PCT)
Prior art keywords
deposition
ozone
films
sio2
methods
Prior art date
Application number
PCT/US2000/015851
Other languages
French (fr)
Other versions
WO2000077831A2 (en
Inventor
Sasangan Ramanathan
Joseph Ellul
Asharf R Khan
Hariram Krishnamoorthy
Dilip Vijay
Giovanni Antonio Foggiato
Original Assignee
Quester Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quester Technology Inc filed Critical Quester Technology Inc
Priority to AU54767/00A priority Critical patent/AU5476700A/en
Publication of WO2000077831A2 publication Critical patent/WO2000077831A2/en
Publication of WO2000077831A3 publication Critical patent/WO2000077831A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

Methods are provided for regulating surface sensitivity of the deposition of silicon dioxide films that can permit the deposition of high quality silicon dioxide films for use in shallow trench isolation. By the use of super low ozone concentrations to deposit a seed layer (112a) having low ozone content, the subsequent deposition of high-quality, high ozone films (116) can be facilitated, without the appearance of defects that can appear during conventional high ozone film deposition. Controlling the ozone concentration during seed layer deposition, the thickness of the seed layer, the rates of deposition of the high ozone film, deposition temperature and ozone concentration of the high ozone film, the resulting SiO2 film can exhibit desired properties. Semiconductor thin films according to the methods of this invention can be made thinner than conventional TEOS/ozone films, permitting the manufacture of integrated circuit devices having smaller dimensions. Additionally, methods are presented for increasing the surface sensitivity of deposition of SiO2 films on semiconductor wafers having different materials thereon. By increasing surface sensitivity, differential growth rate of SiO2 on nitride, thermal oxide and silicon can be adjusted to provide increased planarity of the deposited SiO2 layer and can result in reduced dimensions of SiO2 layers to achieve planar surfaces and thereby can decrease manufacturing cost and device size.
PCT/US2000/015851 1999-06-11 2000-06-09 Methods for regulating surface sensitivity of insulating films in semiconductor devices WO2000077831A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU54767/00A AU5476700A (en) 1999-06-11 2000-06-09 Methods for regulating surface sensitivity of insulating films in semiconductor devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13889899P 1999-06-11 1999-06-11
US60/138,898 1999-06-11

Publications (2)

Publication Number Publication Date
WO2000077831A2 WO2000077831A2 (en) 2000-12-21
WO2000077831A3 true WO2000077831A3 (en) 2001-07-05

Family

ID=22484160

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/015851 WO2000077831A2 (en) 1999-06-11 2000-06-09 Methods for regulating surface sensitivity of insulating films in semiconductor devices

Country Status (3)

Country Link
AU (1) AU5476700A (en)
TW (1) TW563223B (en)
WO (1) WO2000077831A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7431967B2 (en) * 2002-09-19 2008-10-07 Applied Materials, Inc. Limited thermal budget formation of PMD layers
US7141483B2 (en) 2002-09-19 2006-11-28 Applied Materials, Inc. Nitrous oxide anneal of TEOS/ozone CVD for improved gapfill
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051380A (en) * 1989-12-27 1991-09-24 Semiconductor Process Laboratory Co., Ltd. Process for producing semiconductor device
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
US5356722A (en) * 1992-06-10 1994-10-18 Applied Materials, Inc. Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity
US5420065A (en) * 1993-05-28 1995-05-30 Digital Equipment Corporation Process for filling an isolation trench
US5458919A (en) * 1987-03-18 1995-10-17 Kabushiki Kaisha Toshiba Method for forming a film on a substrate by activating a reactive gas
US5462899A (en) * 1992-11-30 1995-10-31 Nec Corporation Chemical vapor deposition method for forming SiO2
US5489553A (en) * 1995-05-25 1996-02-06 Industrial Technology Research Institute HF vapor surface treatment for the 03 teos gap filling deposition
US5891810A (en) * 1996-05-16 1999-04-06 Lg Semicon Co., Ltd. Process for supplying ozone (O3) to TEOS-O3 oxidizing film depositing system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5458919A (en) * 1987-03-18 1995-10-17 Kabushiki Kaisha Toshiba Method for forming a film on a substrate by activating a reactive gas
US5051380A (en) * 1989-12-27 1991-09-24 Semiconductor Process Laboratory Co., Ltd. Process for producing semiconductor device
US5356722A (en) * 1992-06-10 1994-10-18 Applied Materials, Inc. Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
US5462899A (en) * 1992-11-30 1995-10-31 Nec Corporation Chemical vapor deposition method for forming SiO2
US5420065A (en) * 1993-05-28 1995-05-30 Digital Equipment Corporation Process for filling an isolation trench
US5489553A (en) * 1995-05-25 1996-02-06 Industrial Technology Research Institute HF vapor surface treatment for the 03 teos gap filling deposition
US5891810A (en) * 1996-05-16 1999-04-06 Lg Semicon Co., Ltd. Process for supplying ozone (O3) to TEOS-O3 oxidizing film depositing system

Also Published As

Publication number Publication date
AU5476700A (en) 2001-01-02
WO2000077831A2 (en) 2000-12-21
TW563223B (en) 2003-11-21

Similar Documents

Publication Publication Date Title
EP1178528B1 (en) Wafer pretreatment to decrease the deposition rate of silicon dioxide on silicon nitride in comparison to its deposition rate on a silicon substrate
US7586177B2 (en) Semiconductor-on-insulator silicon wafer
US5051380A (en) Process for producing semiconductor device
US4504521A (en) LPCVD Deposition of tantalum silicide
US6174808B1 (en) Intermetal dielectric using HDP-CVD oxide and SACVD O3-TEOS
JP2018507562A5 (en)
US6461985B1 (en) Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers
US6407013B1 (en) Soft plasma oxidizing plasma method for forming carbon doped silicon containing dielectric layer with enhanced adhesive properties
US6054735A (en) Very thin PECVD SiO2 in 0.5 micron and 0.35 micron technologies
US6239002B1 (en) Thermal oxidizing method for forming with attenuated surface sensitivity ozone-teos silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
JP3420653B2 (en) Thin film transistor and liquid crystal display device
US6864150B2 (en) Manufacturing method of shallow trench isolation
WO2000077831A3 (en) Methods for regulating surface sensitivity of insulating films in semiconductor devices
US6245691B1 (en) Ozone-teos method for forming with attenuated surface sensitivity a silicon oxide dielectric layer upon a thermally oxidized silicon substrate layer
JPH02191320A (en) Crystal product and its manufacture
US6235608B1 (en) STI process by method of in-situ multilayer dielectric deposition
JPH09223737A (en) Manufacture of semiconductor device
JP4470231B2 (en) Manufacturing method of semiconductor silicon wafer
JPH03139836A (en) Method for piling silicon nitride layer on glass substrate
US5773354A (en) Method of forming SOI substrate
JPH0530052B2 (en)
US6271138B1 (en) Chemical mechanical polish (CMP) planarizing method with enhanced chemical mechanical polish (CMP) planarized layer planarity
JPH021124A (en) Manufacture of dielectric film
JPH07120651B2 (en) Method of forming a device having a silicon oxide region
JPH06216118A (en) Manufacture of semiconductor device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP