WO2001003178A1

WO2001003178A1 - Method for producing an electrode arrangement

Info

Publication number: WO2001003178A1
Application number: PCT/DE2000/002094
Authority: WO
Inventors: Hans-Jörg BEUTEL; Frank Katzenberg; Hubert Schulz; Thomas Hoffmann
Original assignee: Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 1999-07-01
Filing date: 2000-06-26
Publication date: 2001-01-11
Also published as: DE19930104C1

Abstract

The invention relates to a method for producing an electrode arrangement in a substrate (1), whereby individual electrode areas (2a, 2b, 6a, 6b) are arranged at a lateral distance and/or are vertically offset in relation to each other. According to the inventive method, at least one electrically conductive coating (2, 6) is applied to a surface of a substrate (1) in order to form said electrode areas. In another step, a stamping element (3, 7) is applied to the surface in such a way that a lateral distance and/or vertical offsetting occurs between individual electrode areas (2a, 2b, 6a, 6b). The stamping element is subsequently withdrawn, leaving an electrode structure in which individual electrode areas are separated from each other by a lateral distance and/or vertical offsetting. The inventive method makes it possible to produce electrode structures in the micro and namometric range in a surpisingly simple cost-effective manner.

Description

Method of making an electrode assembly

The invention relates to a method for producing an electrode arrangement in a substrate, in which individual electrode regions have a lateral spacing and / or vertical offset from one another, according to the preamble of patent claim 1.

Such an electrode arrangement plays an essential role in the field of nanotechnology, the main area of application of the present method. Nanostructuring of electrode arrangements is used, for example, to produce biochemical sensors, with the aid of which impedimetric molecular binding events such as the hybridization of DNA with special oligonucleotides or the binding of antibodies to antigens can be detected. In a specific application, for example, a substrate with an interdigital electrode arrangement is used. The corresponding oligonucleotides or antigens are bound between the electrodes on the substrate. For the electrical detection of a dielectric change in the binding layer formed by the bound substances between the electrodes caused by a binding event, it must be ensured that the electrical field lines of the electrical field present between the electrodes predominantly in this Bond or interaction layer run. This requires that the ratio of the electrode spacing to the layer thickness of the dielectric is close to or less than one. Since the thickness of the binding layer, which in the present application example is composed of a monolayer of oligonucleotides or antigens oriented perpendicular to the surface, is only a few 100 nm, the electrode spacing must accordingly be selected in the same or a smaller dimension.

Potentiometric, capacitive and impedimetric methods are known for the electrical detection of molecular species or molecular binding events. EP 0710691 Bl and DE 19610115 AI give examples of applications for this.

However, the sensitivity of these methods depends crucially on the electrode spacing of the measuring arrangement used. The electrode arrangements previously used in these methods have distances between the electrodes which are considerably larger than the dimensions of the molecular species to be detected, which are immobilized as a dielectric interaction layer between the electrodes. To improve the sensitivity of detection, methods of microstructuring were therefore used in order to be able to produce electrode structures with smaller mutual spacings between the electrodes. For example, from K. Reimer et al. , Sensors & Actuators A46-47 (1995), pp. 66-70 known to produce the required fine electrode structures with the help of electron beam lithography. Another method for producing nano-structured electrode arrangements is known from M. Paeschke, "Thin-film metal electrodes as electrochemical amplifiers and dielectric transducers", VDI Progress Reports No. 274, in particular p. 37/38. In this technique, the distances between the electrodes are known not produced laterally on a substrate, but by vertical offset of individual electrode areas in the substrate For this purpose, a silicon wafer with a layer structure is provided, in which the structures for the electrodes are first defined by means of photolithography and a subsequent etching step by creating areas of different heights on the surface The height difference of these areas, which corresponds to the later vertical spacing of the electrodes, is predetermined by the thickness of an etched through insulation layer in the layer structure. In a further step, a metallization layer is vapor-deposited onto the surface, which sic h on areas of different heights. This results in different electrode areas on different levels of the structured surface.

This simplified method creates a vertical offset or a distance between the electrodes, which is defined by the layer thickness of the insulator. The electrode structure becomes three-dimensional. An additional lateral structuring of the electrode areas is not necessary, so that the expensive electron beam technology can be avoided. However, the method still requires a complex manufacturing process with several Lithography and etching steps that increase the cost of the electrode assembly.

From DE 41 07 220 AI a thin film sensor for the detection of gases is known, in the trough-shaped

Indentations are etched into a substrate surface into which the electrode structure is introduced. In this way, a thin sensitive layer can be applied essentially flat to the substrate surface provided with the electrodes.

DE 40 13 593 AI describes a thick-film biosensor, which is composed of several layers of a suitable ceramic material. The uppermost layer has several openings, each of which receives partial electrodes applied using thick-film technology.

A further method for producing a microelectrode array for amperometric applications can be found in EP 0 653 629 A2. In this method, openings are made by means of photoablation in a thin layer of insulating material on a substrate, through which the electrodes are accessible. The electrodes can either be formed as an intermediate layer between the thin insulating layer and the substrate, or can be introduced as an electrically conductive paste into the openings of the thin insulating layer.

Finally, EP 0 585 933 A2 discloses a planar electrode arrangement for the electrical measurement of biological activities, in which a close-knit

Electrode array is used on a substrate. The electrodes are deposited using a vapor deposition process with subsequent structuring by photolithography and created an etching technique. An insulating layer is then applied to the electrode structure and locally removed again at the locations of the respective electrodes using an etching technique.

In the main area of application of this type of sensors, the biomedical field, however, disposable products are generally required. For such products, the above manufacturing techniques are very costly processes.

The object of the present invention is to provide a method with which electrode structures, in particular with dimensions in the micrometer and nanometer range, can be implemented in a cost-effective and simple manner.

The object is achieved with the method according to claim 1. Advantageous embodiments of the method are the subject of the dependent claims.

The present invention deviates from the conventional methods of microstructuring and uses mechanical structuring with the aid of an embossing element to produce the distances between the

Electrodes. Surprisingly, it has been shown here that this embossing process can be used in a simple manner to produce, in particular, micro- and nano-structures in which individual electrode regions have a lateral spacing and / or vertical offset from one another, as is the case, for example, with regard to the vertical offset in the arrangement of M. Paeschke, “Thin film metal electrodes as electrochemical amplifiers and dielectric transducers ", VDI Progress Reports No. 274, esp. S. 37/38 is the case.

In the method according to the invention, at least one electrically conductive layer for forming the electrode regions is applied to a surface of a substrate. In a further step, an embossing element is pressed onto the surface, so that there is a lateral distance and / or a vertical offset between individual electrode areas. By subsequently removing the embossing element, an electrode structure is created in which individual electrode areas are offset vertically, i.e. an offset in the direction of the surface normal of the substrate, and / or laterally spaced apart by a gap.

The size of the offset or distance is preferably controlled via the contact pressure of the embossing element and / or the temperature of the substrate. However, a stamp can also be used as the stamping element, in which the height of the stamping structure corresponds to the size of the vertical offset to be produced, so that the stamp is completely pressed on in this case.

The embossing structure or topography of the embossing element is of course chosen in accordance with the desired structuring of the electrode arrangement. In a simple embodiment, the embossing element will have, for example, rectangular plateaus protruding from the base of the embossing element, which have the shape of the electrode areas define that should lie in a different plane after the embossing process than the electrode areas remaining in the original plane. If these plateaus lie in one plane, the vertical offset of individual electrode areas is identical. If the embossing element has plateaus of different heights, then different electrode spacings can be achieved in a single embossing process.

A suitably shaped embossing stamp is used to generate a lateral or horizontal distance between individual electrode regions. For example, depending on the depth of penetration into the material, different distances between the electrode areas can be achieved by an elevation (hereinafter referred to as cutting edge) of the embossing structure that tapers at a certain angle in the embossing direction. By pressing on the embossed structure, the electrode layer is cut through with the cutting edge, the shape of the cutting edge, such as the radius of curvature of the cutting edge or the angle forming the edge, and the depth of penetration determining the extent of the cut. Controlled penetration depths can be achieved in that the cutting edge has only a certain height above the base of the embossing element.

With this technique of creating a lateral distance, the pressure and temperature ranges required for the embossing process are identical or lower than in the case of creating a vertical offset, since less material has to flow overall.

A combination of embossed structures for vertical offset and lateral is also a matter of course Separation possible in an embossing stamp if such electrode structures are to be produced.

In a preferred embodiment, an embossing element with an embossing structure is used in which the contours of the plateaus define an interdigital structure, so that an interdigital electrode arrangement can be produced with the technique according to the invention.

The embossing element itself only has to be produced once, for example using conventional structuring techniques, such as electron beam lithography, and can subsequently be used for the production of a large number of electrode arrangements in series production. In addition, a master can be produced by conventional structuring processes, from which a larger number of embossing dies are reproduced. This can be done, for example, by embossing the master into suitably deformable

Layers (e.g. polymers) and subsequent fixation or transfer of the structure into harder materials can be achieved. This leads to a significant reduction in manufacturing costs compared to the previously known manufacturing technologies for such electrode structures.

With the method, non-planar, three-dimensional nanostructured electrodes with height differences or a mutual offset or distance of a few nanometers down to the micrometer range can be produced without any problems. The production of flat electrode structures with lateral distances in the Nanometer to micrometer range is possible with the method in a very simple way.

The method according to the invention thus enables the production of electrode structures in the micrometer and nanometer range in a surprisingly simple manner and very inexpensively, so that nothing stands in the way of the use of sensors based on this technology as single use products in the biomedical field.

It is not necessary for the embossing element to come into direct contact with the conductive layer. Rather, another layer or layer sequence, for example one, can be applied to the conductive layer before the embossing process is carried out

Insulation layer as long as the desired result of the embossing is still achieved.

It goes without saying that the choice of materials must allow the structure to be embossed.

This applies in particular to the hardness of the embossing element and the elasticity of the layers to be embossed. However, it is not difficult for the person skilled in the art to find suitable material combinations. For example, silicon or Si0 ₂ can be used as the material for the embossing element, since these materials have sufficient hardness and rigidity and temperature resistance, and an embossing element made from them is characterized by a long service life.

Furthermore, the present method is not limited to the stamping of a single electrically conductive layer. Rather, a multi-layer System of alternating electrically conductive and insulating layers can be provided on the substrate or applied thereon. Completely different materials can be used for both the conductive and the insulating layers, depending on the desired function. The subsequent embossing process allows individual areas of this entire layer system to be displaced vertically with respect to one another. For example, a

Electrode region of an initially lying electrically conductive layer comes into contact with a lower lying electrically conductive layer, so that lower lying layer regions can be contacted through the opening created.

In principle, all known coating techniques, such as, for example, spin coating, PVD, CVD or laser ablation, which are suitable for generating or maintaining the various functionalities of the individual layers can be used for the construction of the electrically conductive layer or the multi-layer system ,

A substrate made of plastic, for example, can be used as the carrier for the electrically conductive layer or the layer system.

Likewise, a carrier substrate of any hardness can be used, on which a layer with a lower hardness than that of the at least one electrically conductive layer is applied

Embossing element is applied. The thickness of this layer must be greater than the vertical offset of the electrode areas to be generated. The method according to the invention is illustrated again below using exemplary embodiments in conjunction with the drawings. 1 shows an example for carrying out the method on a single layer;

Figure 2 shows an example of the implementation of the

Process on a multi-layer system; and

FIG. 3 shows an example of different embossing structures that can be used on an embossing stamp.

FIG. 1 shows a substrate 1 with an electrically conductive layer 2 applied thereon to form the electrodes. In this example, a stamp 3 is used which has a topography of the embossing surface in the form of rectangular plateaus 4 which have the same height. By pressing the stamp 3 onto the surface of the substrate 1 with the electrically conductive layer 2, an offset is generated between individual regions of the electrically conductive layer, so that electrode regions 2a and 2b offset vertically with respect to one another are produced.

In the present example, a substrate made of polymethylacrylate (PMMA) was used as substrate 1. Of course, it is also possible to first apply this polymeric carrier material to a harder substrate, for example by means of spin coating on a silicon wafer. The PMMA surface was then vapor-deposited with a 20 nm thick layer 2 of silver as the electrically conductive layer to be structured.

To produce the stamp 3, a silicon wafer in the submicrometer range was structured by means of electron beam lithography with lines at a distance of 500 nm to 2 μm.

This stamp was then embossed with a pressure of approx. 100 * 10 ⁵ Pa and at a temperature of approx. 200 ° C through the metallization layer 2 into the PMMA layer 1. As a result, the metal layer was sheared off at the edges of the structures 4 of the stamp and offset by approximately 100 nm. Depending on the selection of the parameters pressure and temperature, the penetration depth of the stamp and thus the offset of the metallization layer in the depth can be controlled.

FIG. 2 shows a substrate 1 with an applied layer sequence of an electrically conductive first layer 2 to form first electrodes, an insulating intermediate layer 5 and an electrically conductive second layer 6 to form second electrodes. In this example, a stamp 7 is also used, which has a topography of the embossing surface in the form of rectangular plateaus 8, the plateaus in this case having different heights. By pressing the stamp 7 onto the surface of the substrate 1 with the layer sequence, a different offset is generated between individual regions of the layer sequence. In this example, both areas of the first electrodes 2a and 2b and areas of the second electrodes 6a and 6b are also mutually vertical offset so that it is possible to produce a small distance between the first and second electrodes.

In the method according to the invention, the layers subjected to the embossing process are displaced in accordance with the topography of the embossing element in the direction of the surface normal of the layers, so that there is a height offset between individual regions of the electrodes formed by the layers. This

Offset can occur via the topography or the profile of the embossing structures (height and spacing of the structures) of the embossing element, the process parameters (pressure, temperature, time, embossing depth) and the material properties (plasticity, rigidity, etc.) and the thickness of the various layers to be controlled. In this way, electrodes of the same material are separated in a single-layer system. In a multi-layer system, combinations of different electrode systems can also be created by choosing the materials.

Finally, FIG. 3 shows various examples of embossed structures that can be used alone or in combination in the method according to the invention. In addition to the structures in the form of rectangular plateaus 4 already explained in the preceding examples, pointed shapes 9-11 are also shown. A horizontal spacing or a lateral separation between individual electrode regions can be produced by means of these cutting-shaped elevations or cutting edges 9-11, depending on the shape and penetration depth of the latter Structures in the electrically conductive layers and the underlying material depends and can be controlled specifically.

The effect of an embossing process with the cutting edge 9 is shown schematically in the lower area of the figure. In this case, a polymer layer 12 which carries the electrically conductive layer 2 is applied to a substrate 1. By stamping the stamp 13 with the structure 9, a gap 14 of defined width can be made in the electrically conductive

Layer 2 are generated by which the electrode regions are spaced apart.

Such a stamp for cutting through the electrode layers for generating a lateral distance can be produced, for example, by anisotropic wet etching of silicon. With this etching technique, tapered shapes can be easily achieved in the silicon, which act like a cutting tool and when stamped on

Cut or cut the electrode layer.

Claims

claims

1. A method for producing an electrode arrangement in a substrate (1), in which individual electrode regions (2a, 2b, 6a, 6b) are laterally spaced and / or vertically offset from one another, at least one electrically conductive layer (2, 6) being used Formation of the electrode areas is applied to a surface of the substrate (1), characterized in that the lateral distance and / or vertical offset between the individual electrode areas (2a, 2b, 6a, 6b) after the application of the at least one electrically conductive layer (2nd , 6) is produced by pressing an embossing element (3, 7) onto the surface of the substrate (1).

2. The method according to claim 1, characterized in that the size of the distance and / or offset via the contact pressure of the embossing element (3, 7) and / or the temperature of the substrate (1) is controlled.

3. The method according to claim 1 or 2, characterized in that the size of the vertical offset over the height of an embossed structure of the embossing element (3, 7) is set.

, Method according to claim 1 or 2, characterized in that the size of the lateral distance is adjusted via the height and shape of an embossing structure of the embossing element.

5. The method according to any one of claims 1 to 4, characterized in that a plurality of electrically conductive layers (2, 6) spaced apart from one another by insulating intermediate layers are applied to form the electrode regions on the substrate (1).

6. The method according to any one of claims 1 to 5, characterized in that a substrate (1) made of plastic is used.

7. The method according to any one of claims 1 to 5, characterized in that before the application of the at least one electrically conductive layer (2, 6) a layer with a lower hardness than that of the embossing element is applied to the surface of the substrate (1) , the thickness of the layer being greater than the vertical offset of the electrode regions (2a, 2b, 6a, 6b) to be generated.

8. The method according to any one of claims 1 to 7, characterized in that an embossing element (3, 7) made of silicon or Si0 _{2 is} used.

Method according to one of Claims 1 to 8, characterized in that an embossing element (3, 7) with an embossing structure is used which has regions of different heights and / or shapes, so that the individual electrode regions (2a, 2b, 6a, 6b) receive a different vertical offset and / or lateral distance from each other.

10. The method according to any one of claims 1 to 8, characterized in that an embossing element (3, 7) is used with an embossing structure which has the shape of an interdigital structure.

11. The method according to any one of claims 1 to 10, characterized in that the embossing element (3, 7) is pressed on at a temperature which allows plastic deformation and separation of the electrically conductive layer (2, 6).

12. The method according to any one of claims 1 to 11, characterized in that with the embossing element (3, 7) a vertical offset and / or lateral distance of the individual electrode areas (2a, 2b, 6a, 6b) of less than 500 nm is generated ,