WO2001031474A2 - Micro ocontroller with re-programmable flash memory - Google Patents
Micro ocontroller with re-programmable flash memory Download PDFInfo
- Publication number
- WO2001031474A2 WO2001031474A2 PCT/US2000/029639 US0029639W WO0131474A2 WO 2001031474 A2 WO2001031474 A2 WO 2001031474A2 US 0029639 W US0029639 W US 0029639W WO 0131474 A2 WO0131474 A2 WO 0131474A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- program
- logic controller
- programmable logic
- programmable
- program execution
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7814—Specially adapted for real time processing, e.g. comprising hardware timers
Definitions
- the present invention relates to a flash memory and, more particularly, to a reprogrammable flash memory micro controller.
- the flash memory may be configured as a programmable logic controller.
- the controller CPU includes a microprocessor, possibly supplemented with a custom control instruction processor (boolean processor), for execution of the user program under the supervision of an operating system, random access data memory (RAM) for user and operating system data, battery backed RAM or non- volatile EEPROM for storing the user program, and a permanent ROM or EPROM for storage of the operating system software.
- a custom control instruction processor boost converter
- RAM random access data memory
- the controller CPU includes a microprocessor, possibly supplemented with a custom control instruction processor (boolean processor), for execution of the user program under the supervision of an operating system, random access data memory (RAM) for user and operating system data, battery backed RAM or non- volatile EEPROM for storing the user program, and a permanent ROM or EPROM for storage of the operating system software.
- RAM random access data memory
- EEPROM electrically erasable programmable read-only memory
- the user program is typically prepared on a general purpose computer and loaded into the PLC in symbolic form.
- the loading is typically by means of a serial communications protocol, though a removable memory cartridge may sometimes be used to by-pass this step.
- the symbolic code is converted to executable code by a compiler. Included in the system software that must be permanently stored in ROM, there is the actual operating system that coordinates execution, the communications software to support transfer of the user program and data, and the compiler which converts the symbolic user program to executable form.
- the operating system has to coordinate the communications, compilation, and program execution functions. This requires some sophistication of the operating system to respond to communications events, queue/de queue deferred tasks, and manage mode transitions between program mode and run mode.
- the compiler and communications software functions may be quite large, and significantly extend permanent storage requirements beyond that needed for controlling the execution of the user program.
- micro controllers including the data RAM and operating system ROM on a single chip with the microprocessor.
- the user program is contained in an external storage device: battery backed RAM, EPROM, or EEPROM, possibly added to the basic unit as a removable memory cartridge.
- the functions of the programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
- a micro controller incorporating a micro processor, RAM, and re programmable Flash EPROM in a single package implements the logical core of the program execution device.
- the external pins of this package can be largely devoted to the 110 functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor.
- External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
- the communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device.
- This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing.
- the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel.
- the kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
- the block diagram below shows the extreme simplicity of the program execution device. This diagram shows, as non-essential auxiliary features, a watchdog timer function to disable outputs on controller failure and optical isolation of inputs and outputs.
- the communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
- the advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost.
- the burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device.
- the communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.
- Fig. 1 shows the invention.
- the functions of the programmable logic controller are located in physically separable units.
- These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function.
- a micro controller 10 incorporating a micro processor 12, RAM 14, and reprogrammable Flash EPROM 16 in a single package l ⁇ implements the logical core of the program execution device.
- the external pins 20 of this package can be largely devoted to the I/O functions of the programmed control task, and do not need to be utilized for access of external memory devices by the micro processor.
- External memory devices, data / address busses, buffers, etc. are eliminated from the architecture, reducing size and cost of the control function.
- the communication / programming device provides in a separable package all functions required for external communication and conversion of the user program from symbolic form to binary code, and loading of that code into the program execution device.
- This binary code is programmed into the re programmable memory of the program execution device by direct manipulation of the logic controls of the re programmable memory. These controls are carried via dual use pins on the micro controller, which are used for the main mission I/O function of the controller when the user program is executing.
- the binary code loaded into the micro controller includes a compilation of the symbolic user control program with a system support kernel.
- the kernel provides support for time base functions seen as services by the user, watchdog timer maintenance, and re-starting of the user program after each completion of the user program sequence.
- the diagram of Fig. 1 below shows the extreme simplicity, yet novel ingenuity, of the program execution device.
- This diagram shows, as non-essential auxiliary features, a watchdog timer 22 function to disable outputs on controller failure and optical isolation 24 of inputs and outputs.
- the communication / programming device consists of a micro processor or micro controller, together with sufficient RAM and ROM to handle the given tasks, a communications port useable by a general purpose computer, and controlled lines to a programming port which can program the ROM of the program execution device.
- the advantage of this invention is that it minimizes components required to implement the most often used portion of a programmable logic controller, thus leading to lower cost.
- the burden of communications and compilation firmware and storage hardware, which is required only for program development, is excluded from the program execution device.
- the communication and program compilation tools are included in a separate programming device, by which the user may make use of a single instance of the programming device to program a potentially very large number of program execution devices.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00980243A EP1281131A2 (en) | 1999-10-26 | 2000-10-26 | Micro controller with re-programmable flash memory |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16145099P | 1999-10-26 | 1999-10-26 | |
US60/161,450 | 1999-10-26 | ||
US09/697,419 | 2000-10-26 | ||
US09/697,419 US7134118B1 (en) | 2000-10-26 | 2000-10-26 | Re-programmable flash memory micro controller as programmable logic controller |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001031474A2 true WO2001031474A2 (en) | 2001-05-03 |
WO2001031474A3 WO2001031474A3 (en) | 2002-11-21 |
Family
ID=26857839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/029639 WO2001031474A2 (en) | 1999-10-26 | 2000-10-26 | Micro ocontroller with re-programmable flash memory |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1281131A2 (en) |
CN (1) | CN100388262C (en) |
WO (1) | WO2001031474A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003048965A2 (en) * | 2001-11-30 | 2003-06-12 | Infineon Technologies Ag | Baseband chip having an integrated real-time operating system functionality and method for operating a baseband chip |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112650189A (en) * | 2019-10-12 | 2021-04-13 | 中电智能科技有限公司 | Embedded PLC automatic test system and method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0334523A2 (en) * | 1988-03-18 | 1989-09-27 | Fujitsu Limited | Microprocessor |
EP0578361A1 (en) * | 1992-07-08 | 1994-01-12 | Advanced Micro Devices, Inc. | Digital signal processing apparatus |
US5495593A (en) * | 1990-06-29 | 1996-02-27 | National Semiconductor Corporation | Microcontroller device having remotely programmable EPROM and method for programming |
US5566344A (en) * | 1994-12-20 | 1996-10-15 | National Semiconductor Corporation | In-system programming architecture for a multiple chip processor |
US5590373A (en) * | 1994-07-25 | 1996-12-31 | International Business Machines Corporation | Field programming apparatus and method for updating programs in a personal communications device |
EP0797152A1 (en) * | 1996-03-22 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd. | Single-chip microcomputer with memory controller |
US5964890A (en) * | 1997-03-27 | 1999-10-12 | Mitsubishi Electric Semiconductor Software Co., Ltd. | System call issue method and debug system |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US556334A (en) * | 1896-03-17 | Morton e | ||
DE19732324A1 (en) * | 1997-07-28 | 1999-02-04 | Kloeckner Moeller Gmbh | Circuit arrangement and method for memory space management and for processing user programs in small control systems |
-
2000
- 2000-10-26 WO PCT/US2000/029639 patent/WO2001031474A2/en active Application Filing
- 2000-10-26 EP EP00980243A patent/EP1281131A2/en not_active Ceased
- 2000-10-26 CN CNB008149674A patent/CN100388262C/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0334523A2 (en) * | 1988-03-18 | 1989-09-27 | Fujitsu Limited | Microprocessor |
US5495593A (en) * | 1990-06-29 | 1996-02-27 | National Semiconductor Corporation | Microcontroller device having remotely programmable EPROM and method for programming |
EP0578361A1 (en) * | 1992-07-08 | 1994-01-12 | Advanced Micro Devices, Inc. | Digital signal processing apparatus |
US5590373A (en) * | 1994-07-25 | 1996-12-31 | International Business Machines Corporation | Field programming apparatus and method for updating programs in a personal communications device |
US5566344A (en) * | 1994-12-20 | 1996-10-15 | National Semiconductor Corporation | In-system programming architecture for a multiple chip processor |
EP0797152A1 (en) * | 1996-03-22 | 1997-09-24 | Matsushita Electric Industrial Co., Ltd. | Single-chip microcomputer with memory controller |
US5964890A (en) * | 1997-03-27 | 1999-10-12 | Mitsubishi Electric Semiconductor Software Co., Ltd. | System call issue method and debug system |
Non-Patent Citations (4)
Title |
---|
"80C51FA/83C51FA Event-Control CHMOS Single-Chip 8-Bit Microcontroller" INTEL DATA SHEET, February 1995 (1995-02), pages 1-13, XP002188114 * |
See also references of EP1281131A2 * |
STAUDINGER T: "FLASH EPROM CONTROLLER SAB 88C166 SETS NEW STANDARDS FOR REAL-TIME APPLICATIONS" COMPONENTS, SIEMENS AKTIENGESELLSCHAFT. MUNCHEN, DE, vol. 28, no. 4, 1 September 1993 (1993-09-01), pages 15-17, XP000415962 ISSN: 0945-1137 * |
TEO C Y ET AL: "A prototype for an integrated energy automation system" CONFERENCE RECORD OF THE INDUSTRY APPLICATIONS SOCIETY ANNUAL MEETING. SEATTLE, OCT. 7 - 12, 1990, NEW YORK, IEEE, US, vol. 2 MEETING 25, 7 October 1990 (1990-10-07), pages 1811-1818, XP010035015 ISBN: 0-87942-553-9 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003048965A2 (en) * | 2001-11-30 | 2003-06-12 | Infineon Technologies Ag | Baseband chip having an integrated real-time operating system functionality and method for operating a baseband chip |
WO2003048965A3 (en) * | 2001-11-30 | 2004-07-22 | Infineon Technologies Ag | Baseband chip having an integrated real-time operating system functionality and method for operating a baseband chip |
Also Published As
Publication number | Publication date |
---|---|
CN100388262C (en) | 2008-05-14 |
WO2001031474A3 (en) | 2002-11-21 |
EP1281131A2 (en) | 2003-02-05 |
CN1460216A (en) | 2003-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR0147063B1 (en) | Digital computing system with low power mode | |
US6145020A (en) | Microcontroller incorporating an enhanced peripheral controller for automatic updating the configuration date of multiple peripherals by using a ferroelectric memory array | |
US6122748A (en) | Control of computer system wake/sleep transitions | |
EP0977125A1 (en) | Peripheral control processor | |
US7134118B1 (en) | Re-programmable flash memory micro controller as programmable logic controller | |
JPH07504282A (en) | Microcontroller power-up delay device | |
JPS61241841A (en) | Emulator | |
US10002103B2 (en) | Low-pin microcontroller device with multiple independent microcontrollers | |
EP3268871B1 (en) | Low-pin microcontroller device with multiple independent microcontrollers | |
US20210232430A1 (en) | Processor zero overhead task scheduling | |
US6629165B1 (en) | Programmable controller including intelligent module | |
WO1993010501A1 (en) | Microcontroller with fuse-emulating latches | |
EP1281131A2 (en) | Micro controller with re-programmable flash memory | |
US6697686B1 (en) | Circuit configuration and method for storage management and execution of user programs in a small control unit | |
JP4821717B2 (en) | Programmable controller, programmable controller support apparatus, and programmable controller system | |
US20030126484A1 (en) | Reduced power option | |
JP2002342256A (en) | Data processor and method for updating data table | |
JPH08123678A (en) | Memory rewriting device of information processor | |
US6466994B1 (en) | Method and system for programming a system board using a peripheral controller | |
JP2001357023A (en) | Semiconductor integrated circuit and method for writing into nonvolatile memory built therein | |
JPH09146616A (en) | One chip servo controller | |
KR20060087038A (en) | Micro controller and rom data program method thereof | |
KR100506316B1 (en) | Interrupt handling of micro firmware loader on IC bus | |
KR20030064543A (en) | Micro-Computer With Keyboard Controller | |
JPH06139102A (en) | Digital control device and its debugging method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): CN IN JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2000980243 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 008149674 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A3 Designated state(s): CN IN JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
WWP | Wipo information: published in national office |
Ref document number: 2000980243 Country of ref document: EP |
|
NENP | Non-entry into the national phase in: |
Ref country code: JP |