WO2001035462A1 - Metal redistribution layer having solderable pads and wire bondable pads - Google Patents
Metal redistribution layer having solderable pads and wire bondable pads Download PDFInfo
- Publication number
- WO2001035462A1 WO2001035462A1 PCT/US2000/024087 US0024087W WO0135462A1 WO 2001035462 A1 WO2001035462 A1 WO 2001035462A1 US 0024087 W US0024087 W US 0024087W WO 0135462 A1 WO0135462 A1 WO 0135462A1
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- layer
- metal layer
- depositing
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- bond pads
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49139—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture
- Y10T29/4914—Assembling to base an electrical component, e.g., capacitor, etc. by inserting component lead or terminal into base aperture with deforming of lead or terminal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49211—Contact or terminal manufacturing by assembling plural parts with bonding of fused material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T29/49204—Contact or terminal manufacturing
- Y10T29/49208—Contact or terminal manufacturing by assembling plural parts
- Y10T29/49222—Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
Definitions
- the present invention relates generally to semiconductor devices and more specifically to metal redistribution layers.
- solder bump arrays has significantly increased the pinout capability of semiconductor dice by utilizing the surface area of the die itself to provide a field of bond sites.
- a key element of this pinout scheme is the use of a metal redistribution layer.
- This is an interconnect layer disposed atop a finished semiconductor die. Electrical connections from the interconnect layer are made to the underlying die bond pads which are typically disposed about the die periphery.
- the interconnects serve to redistribute the bond pads from the periphery over the surface area of the die, thus permitting higher I/O pinouts out of the die.
- pinout requirements continue to increase, there is a need to combine solder bumping methods with wire binding techniques to provide even greater pinout capability.
- the materials used for each approach are mutually exclusive.
- solder bumps Materials suited for solder bumps have poor mechanical adhesion properties and are thus not suited for wire bonding.
- copper is a highly solderable material, but is a poor choice for wire bonding. The reason is that copper readily forms an oxide layer which exhibits poor bonding properties.
- redistribution metallization which can accommodate both solder bumping and wire bonding. It is desirable to have a process which integrates well with existing redistribution metallization methods and yet provide solder bumps and wire bond structures.
- the redistribution metallization scheme of the present invention includes conventional solder bumps in addition to the presence of new wire bond pads which can serve to relocate the bond pads which exist on the semiconductor die. This improves the connectivity options for the device, especially in flip-chip applications.
- Fabrication of the redistribution metallization in accordance with the invention includes depositing a passivation layer and forming openings to the underlying bond pads as needed. A trimetal layer is then blanket deposited atop the passivation layer and etched to form the necessary redistribution traces. At the same time additional wire bond pads are patterned as well. A second passivation is deposited and etched to expose areas atop the underlying metallization at location where solder bumps will be formed and at locations corresponding to the added wire bond pads. Next, solder bumps are formed. In one embodiment, a subsequent etch step is made to expose an underlying metal layer of the trimetal layer at the locations of the added wire bond pads.
- Fig. 1 is a top view of a typical IC device, showing the underlying wire bond pads and the metal redistribution layer.
- Figs. 2A - 21 show the process steps for producing the redistribution layer in accordance with the invention.
- FIGS. 3A - 3C show perspective views of intermediate results during processing in order to better understand those aspects of the invention.
- a semiconductor device 100 consists of an underlying substrate having a plurality of wire bond pads 102 formed thereon, shown in phantom lines.
- a metallization layer carries a plurality of traces 142 - 148 having first ends which are in electrical contact with the underlying wire bond pads 102. Disposed along these traces are solder bumps 122 and additional wire bond pads 132 - 138. The solder bumps and additional pads are effectively "redistributed" over the surface of the semiconductor device by way of the traces, thus providing higher pinout counts.
- FIG. 2A - 21 show the processing steps of the present invention. These figures are taken from view line 2-2 of Fig. 1 and show how the redistribution metallization is formed. Figure 2A starts off with an essentially finished semiconductor wafer 104.
- the wafer comprises the necessary constituent substrate layer and its associated metal and insulative layers to fully define the circuitry for its intended functionality, including the wire bond I/O pads 102 needed for connection in an IC package.
- a passivation layer 202 of a dielectric material is deposited over the upper surface of wafer 104. Any of a number of insulative materials can be used. For example, photo-definable benzocyclobutane (BCB) was used for layer 202.
- BCB photo-definable benzocyclobutane
- Known photolithographic and etching techniques are used to drop a via 212 to the underlying wire bond pad 102, Fig. 2C.
- a three layer metal structure 240 is blanket deposited over the etched passivation layer 202, Fig.
- each layer is sputtered on one at a time.
- a layer of aluminum 204 is sputtered.
- a nickel target is used to sputter deposit a layer of nickel 206 atop the aluminum layer.
- a copper target is provided to deposit a layer of copper 208 atop the nickel layer.
- the aluminum layer serves as an adhesive layer, while the nickel serves as a barrier layer between the copper and aluminum layers.
- the trimetal layer 240 is then photolithographically processed and etched to define the traces comprising the redistribution layer. Further, in accordance with the invention, the additional wire bond pads 132 - 138 are defined in the trimetal layer.
- the trace 142 and additional pad 132 are indicated by the dashed lines in Fig. 2D.
- the perspective view of Fig. 3A more clearly illustrates this aspect of the invention.
- the illustration in Fig. 3A shows the formation of trace 142 atop passivation layer 202, a first end of which is in electrical contact with underlying pad 102 through via 212.
- the other end of trace 142 terminates in a new wire bond pad 132, also formed atop the passivation layer.
- a second passivation layer 222 is then deposited atop the etched trimetal layer 240, Fig. 2E, to provide a protective seal against moisture and contaminants and to serves as a scratch protection layer.
- the second passivation layer 222 is then etched away to open up solder bump sites 214 through the passivation layer to the trimetal layer.
- pad openings 216 are made through the passivation layer to the trimetal. The pads openings are coincident with the wire bond pads 132 formed in the trimetal.
- 3B shows the wafer at this stage of processing more clearly.
- the trace 142 and added wire bond pad 132 are shown in dashed lines indicating they lie beneath the insulation layer 222. Openings 21 and 216 are shown, exposing the underlying copper layer 208.
- solder bump sites 214 are filled with solder and any appropriate barrier metals to form reliable solder bumps 122 using known C4 (controlled collapse chip construction) techniques or other ball-grid array processing techniques. Recall that copper is very well suited for solder bump formation and so the solder bumps 122 will have a strong mechanical coupling to the underlying redistribution metallization.
- the solder bumped wafer is subjected to a subsequent etch step to remove the copper layer and nickel layer that is exposed through the openings 216.
- a subsequent etch step to remove the copper layer and nickel layer that is exposed through the openings 216.
- This can be accomplished by any of a number of known wet-chemical etch techniques for removing aluminum and nickel.
- the result of the etch step is shown in Fig. 2H where wire bond pad 132 now consists of a single layer of aluminum. It is to the surface of the aluminum layer that wires (e.g. wire 230, Fig. 21) will be bonded in a subsequent wire bonding operation.
- a bottom-most conductive metal adhesion layer 204 can be sputtered onto passivation layer 202.
- Typical adhesion metals include aluminum and titanium-tungsten (TiW) .
- the metal layer is etched to form the desired traces 142 - 148 comprising the redistribution layer and the added wire bond pads 132 - 138.
- a layer of nickel 206 is deposited followed by a layer of gold 208.
- the second passivation layer 222 is then deposited and etched to form openings 214 and 216.
- solder bump 122 is formed, Fig. 2G.
- the subsequent metal etch step shown in Fig. 2H is not needed. The reason is that gold exhibits adequate bonding properties for wire bonding purposes. The upper layer of gold is therefore retained. However, it is noted that gold does not solder well, since gold leaches into the solder during the soldering operation.
- the trimetal layer is gold/nickel/adhesion (AL or TiW)
- a or TiW gold/nickel/adhesion
- An added wire bond pad can simply be placed atop its corresponding underlying wire bond pad.
- bond pad 134 is located atop bond pad 102A.
- This configuration is used when the underlying pad 102A does not need to be relocated.
- Another use arises in flip-chip configurations. A connection from the upper chip can be made to a bond pad on the lower chip to bring out the signal to an external pin.
- solder bump 126 would be coupled to a coincident conductive via on an upper chip providing a connection to pad 136 on the bottom chip by way of trace 146.
- Yet another use might arise in highly complex applications where the circuit density is high.
- pad 102B is routed to an upper chip in flip-chip design via trace 144 and solder bump 124.
- the upper chip carries the signal to solder bump 126 which then continues on to pad 136 via trace 146.
- the invention lies not with the particular patterns possible in the redistribution metallization, but rather in the fact that solder bumps and wire bond pads can be combined to provide additional flexibility in terms of connectivity within a semiconductor device and between two flip-chip connected die, and in the way the redistribution metallization is formed to allow both solder bumps and wire bond pads in the first place.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA002388926A CA2388926A1 (en) | 1999-11-05 | 2000-08-31 | Metal redistribution layer having solderable pads and wire bondable pads |
JP2001537102A JP2003514380A (en) | 1999-11-05 | 2000-08-31 | Metal redistribution layer having solderable pads and wirebondable pads |
EP00961480A EP1228530A1 (en) | 1999-11-05 | 2000-08-31 | Metal redistribution layer having solderable pads and wire bondable pads |
NO20022134A NO20022134L (en) | 1999-11-05 | 2002-05-03 | Metal distribution layer having solderable and wire bondable contact surfaces |
HK03101891.5A HK1049913B (en) | 1999-11-05 | 2003-03-14 | Metal redistribution layer having solderable pads and wire bondable pads |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/434,711 | 1999-11-05 | ||
US09/434,711 US6511901B1 (en) | 1999-11-05 | 1999-11-05 | Metal redistribution layer having solderable pads and wire bondable pads |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001035462A1 true WO2001035462A1 (en) | 2001-05-17 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/024087 WO2001035462A1 (en) | 1999-11-05 | 2000-08-31 | Metal redistribution layer having solderable pads and wire bondable pads |
Country Status (10)
Country | Link |
---|---|
US (3) | US6511901B1 (en) |
EP (1) | EP1228530A1 (en) |
JP (1) | JP2003514380A (en) |
KR (1) | KR100643065B1 (en) |
CN (1) | CN1198337C (en) |
CA (1) | CA2388926A1 (en) |
HK (1) | HK1049913B (en) |
NO (1) | NO20022134L (en) |
TW (1) | TW477051B (en) |
WO (1) | WO2001035462A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US6511901B1 (en) | 2003-01-28 |
KR20020044590A (en) | 2002-06-15 |
EP1228530A1 (en) | 2002-08-07 |
US6762117B2 (en) | 2004-07-13 |
KR100643065B1 (en) | 2006-11-10 |
CA2388926A1 (en) | 2001-05-17 |
NO20022134D0 (en) | 2002-05-03 |
CN1387681A (en) | 2002-12-25 |
TW477051B (en) | 2002-02-21 |
US6577008B2 (en) | 2003-06-10 |
NO20022134L (en) | 2002-05-03 |
JP2003514380A (en) | 2003-04-15 |
US20020025585A1 (en) | 2002-02-28 |
US20030119297A1 (en) | 2003-06-26 |
HK1049913B (en) | 2005-08-05 |
HK1049913A1 (en) | 2003-05-30 |
CN1198337C (en) | 2005-04-20 |
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