WO2001037090A1 - A memory expansion module with stacked memory packages - Google Patents

A memory expansion module with stacked memory packages Download PDF

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Publication number
WO2001037090A1
WO2001037090A1 PCT/US2000/031439 US0031439W WO0137090A1 WO 2001037090 A1 WO2001037090 A1 WO 2001037090A1 US 0031439 W US0031439 W US 0031439W WO 0137090 A1 WO0137090 A1 WO 0137090A1
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WO
WIPO (PCT)
Prior art keywords
memory
memory module
recited
signals
module
Prior art date
Application number
PCT/US2000/031439
Other languages
French (fr)
Inventor
Tayung Wong
John Carrillo
Jay Robinson
Clement Fang
David Jeffrey
Nikhil Vaidya
Nagaraj Mitty
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to JP2001539116A priority Critical patent/JP3999516B2/en
Priority to EP00982130A priority patent/EP1232439B1/en
Priority to DE60037828T priority patent/DE60037828D1/en
Priority to AU19200/01A priority patent/AU1920001A/en
Publication of WO2001037090A1 publication Critical patent/WO2001037090A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1024—Identification of the type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Definitions

  • TITLE A MEMORY EXPANSION MODULE WITH STACKED MEMORY PACKAGES
  • This invention generally relates to memory hardware for computer systems, and more specifically to memory expansion modules for expanding memory in computer systems
  • SIMMs and DIMMs include small, compact circuit boards that are designed to mount easily into an expansion socket mounted on another circuit board, typically a computer motherboard
  • the circuit boards used to implement SIMMs and DIMMs include an edge connector comprising a plurality of contact pads, with contact pads typically being present on both sides of the circuit board
  • opposing contact pads are connected together (l e shorted), and thus carry the same signal while at least some opposing contact pads on DIMMs are not connected, thus allowing different signals to be carried Due to this, higher signal density may be accommodated by DIMMs
  • Memory elements of SIMMs and DIMMs are typically Dynamic Random Access Memory (DRAM) chips
  • DRAM chips store information as a charge on a capacitor, with the charge level representing a logic one or logic zero Since a capacitor charge will dissipate over time, DRAM chips require refresh cycles on a periodic basis
  • RAS row address strobe
  • CAS column address strobe
  • CAS signals, row and column addresses can be time-multiplexed on common signal lines, contact pads, and pms of the address bus This allows a greater number of memory locations that can be addressed without a corresponding increase in the number of required signal lines, contact pads, and pms
  • a RAS signal is asserted on the RAS input of the DRAM, and a row address is forwarded to row decode logic on a memory chip
  • the contents of all locations in the addressed row will then be sent to a column decoder, which is typically a combination multiplexer/demultiplexer
  • a CAS signal is asserted, and a column address is sent to the column decoder
  • the multiplexer in the column decoder will then select the corresponding column from the addressed row, and the data from that specific row/column address is placed on the data bus for used by the computer system
  • a memory module includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system Mounted upon the circuit board is a plurality of stacked memory packages Each stacked memory chip package contains multiple memory chips, or die, withm the package These memory chips are typically Dynamic Random Access Memory (DRAM) In one embodiment, each stacked memory package mcludes two DRAM die
  • the printed circuit board of this embodiment includes 18 locations for mounting the stacked memory packages, resulting in a memory module with a total of 36 memory die
  • at least one buffer (or line driver) chip for driving address and control signals to the plurality of memory die contained withm the stacked memory packages
  • a clock driver chip is also mounted upon the printed circuit board for driving clock signals to the memory chips
  • a storage unit which provides module identification and signal routing information
  • each memory d.e withm each stacked memory package may be individually accessed by a computer system Since the memory die withm the stacked memory packages may be accessed individually, multiple memory banks may be formed with each die withm a given package belonging to a different memory bank In one embodiment, each memory die is a 32M x 8. resulting m a stacked memory package with a capacity of 64M x 8 The total module capacity m this embodiment is 1 gigabyte In general, the memory module is scalable and may be implemented with various amounts of memory capacity
  • the memory expansion module with stacked memory packages and error correction functionality may advantageously allow greater memory capacity
  • the use of stacked memory packages may allow for greater memory capacity without the need for additional circuit board area
  • the use of stacked memory packages with no more than two memory die each may advantageously reduce power consumption and thermal output by the memory module
  • Figure 1 is a block diagram illustrating an embodiment of a computer system having a CPU, a memory controller, a CPU bus, and a plurality of memory modules.
  • Figure 2 is a mechanical drawing of one embodiment of a memory module
  • Figure 3 A is a block diagram illustrating the electrical connections associated with the top side of an embodiment of the memory module
  • Figure 3B is a block diagram illustrating the electrical connections associated with the bottom side of an embodiment of the memory module
  • Figure 4 is a functional block diagram of one embodiment of the memory module
  • Figure 5 is a pm diagram of one embodiment of a stacked memory package
  • Figure 6 is a block diagram of the internal organization of one embodiment of a stacked memory package
  • Figure 7 is a drawing of one embodiment the memory module illustrating the electrical interconnections associated with error correction functions
  • Figure 8 is a table illustrating exemplary entries withm the storage unit correlating connector pms to integrated circuit pms
  • the computer system includes a CPU 101, coupled to a memory controller 102 through a CPU bus 103
  • Memory controller 102 is configured to control communications and data transfers between CPU 101 and memory modules 1000
  • Memory controller 102 is coupled to each of the memory modules 1000 through a memory bus 104
  • Memory bus 104 includes a plurality of signal lines, each of which is associated with a single data bit position
  • the width of memory bus 104 may be any number of bits, typical bus widths include 16 bits, 32 bits, 64 bits, and 128 bits
  • Some embodiments of memory bus 104 may include extra signal lines for bits that may be used by error correction circuitry The bits conveyed by the extra signal lines are typically referred to as check bits
  • one embodiment of a memory bus may be configured to convey 128 data bits and 16 check bits, for a total bus width of 144 bits Error detection and correction is performed by error correction subsystem 106, located withm memory controller 102
  • the memory modules are provided to expand mam memory of computer system 100, and are electrically coupled to memory bus 104 through a set of expansion sockets 105
  • An expansion socket 105 of the embodiment shown is configured to receive an edge connector of a prmted circuit board of a memory module 1000 Moving on to Figure 2, a mechanical drawmg of one embodiment of the memory module is shown
  • Memory module 1000 includes a plurality of stacked memory packages 1002 mounted upon both sides of a printed circuit board 500
  • Memory module 1000 also includes two lme driver chips 1003, one mounted on each side of the printed circuit board
  • clock driver chip 1004 is mounted on the top side of printed circuit board 500
  • a storage unit 1006 is mounted on the bottom side
  • Edge connector 1005 provides electrical contact between the various components of the module and the computer system 100 of Figure 1
  • edge connector 1005 mcludes 232 electrical contacts
  • a majority of opposmg electrical contacts of edge connector 1005 are not electrically connected, making this module a DIMM (dual mime memory module)
  • FIGs 3A and 3B are block diagrams illustrating the electrical connections associated with the top and bottom side, respectively, of one embodiment of the memory module
  • Memory module 1000 includes a plurality of stacked memory packages 1002 mounted upon each side
  • Memory module 1000 also mcludes edge connector 1005 for electrically couplmg memory module 1000 to the memory bus 104 of Figure 1
  • Line driver chip 1003-A in Figure 3 A serves as an address buffer (for address signals), while line driver chip 1003-B in Figure 3B serves as a control buffer (for control signals)
  • Lme driver chip 1003-A is configured to receive address signals from a memory bus of a computer system, via electrical contact pads 1015 and interconnecting signal lines
  • each address signal is split mto two separate signals Those address signals labeled A0(X) are driven to a first memory bank, while those labeled A1(X) are driven to a second memory bank
  • Line driver chip 1003-B is configured to receive various control signals from a memory bus
  • These control signals include chip select signals, CSO and CS1 as shown
  • Other control signals include row address strobe (RAS), column address strobe (CAS), clock enable (CKE), and write enable (WE)
  • clock driver chip 1004 is configured to receive clock signals from a computer system, and to drive these signals to the memory chips of the stacked memory packages 1002
  • clock driver chip 1004 actually receives two differential PECL (pseudo emitter coupled logic) level signals, designated here as CLK+ and CLK- These differential signals are used as inputs to a phase-locked loop (PLL) circuit with the clock driver chip
  • PLL phase-locked loop
  • the output of the PLL is a singular clock signal, which is driven to each of the memory chips withm the stacked memory packages 1002
  • Other embodiments configured to receive a smgular clock signal are possible and contemplated
  • a storage unit 1006 is mounted upon the bottom side of the module
  • storage unit 1006 is a serial EEPROM (electrically erasable read-only memory)
  • Other embodiments may use a flash memory or other type of device to implement storage unit 1006
  • storage unit 1006 performs two functions The first of these functions is module identification, as storage unit 1006 may, m one embodiment, be configured to store a unique serial number for memory module 1000 This serial number may be read by a computer system into which the memory module is inserted Usmg the unique serial number, the module history may be traced from its time of manufacture, mcludmg any failure information
  • the second function of storage unit 1006 is the storage of error correction information
  • the storage unit 1006 of the embodiment shown is configured to store information correlating pms of the connector edge to individual pms of stacked memory packages 1002 Using this information, an error detected by an error correction subsystem may be quickly traced to a specific pm of a specific stacked memory package 1002
  • Memory module 1000 mcludes a plurality of memory d ⁇ el002U and 1002L, wherein each pair of die is part of a stacked memory package 1002 of Figures 2 and 3
  • memory die 1002U and 1002L will be dynamic random access memory (DRAM) chips
  • a first bank and a second bank of memory are present The first bank of memory includes the shown plurality of memory die 1002U, while the second bank includes the shown plurality of memory chips 1002L
  • Each memory die has a data width of 8 bits, and is coupled
  • Two buffers, or lme driver chips 1003 are used to drive address and control signals to the memory die 1002U and 1002L
  • One line driver chip 1003 is used exclusively for address signals
  • Each address signal received by the lme driver chip 1003 is duplicated twice and driven to a stacked memory package 1002
  • a second line driver chip 1003 is used to drive control signals to the memory die 1002U and 1002L withm each stacked memory package m order to control the individual banks of memory
  • Each stacked memory package 1002 is configured to receive a RAS signal (RAS0 or RAS1), a CAS signal (CAS0 or CAS1 and a WE signal (WE0 or WEI)
  • each stacked memory package 1002 is configured to receive control signals CSO, CSl, CKEO, and CKEl
  • clock driver chip 1004 is configured to receive two differential PECL clock signals, and drive a singular clock signal to each of the memory chips, as explained above with reference to Figure 3A
  • FIG. 5 is a pm diagram of one embodiment of a stacked memory package 1002
  • stacked memory package 1002 includes two memory die
  • Each stacked memory package is configured to receive 8 data signals (DQ0-DQ7), 15 address signals (A0-A12 and BAO-BAl), and control signals CSO, CSl,
  • CKEO, CKEl, RAS, CAS, and WE Address signals BA0 and BA1 correspond to address signals A13 and A 14 as shown in Figure 4
  • a limitation of two memory die per stacked memory package is placed upon the various embodiments of the memory module, due to considerations for power consumption and thermal output of the module Stacked packages with only two memory die may consume less power and generate less heat than those containing three or more memory die, while still allowing additional memory capacity without the need for additional circuit area relative to memory packages havmg a single memory die
  • FIG. 6 is a block diagram of the internal organization of one embodiment of a stacked memory package
  • the embodiment shown consists of memory die 1002U and 1002L Address signals A0-A14 are coupled to both memory die, as are control signals CAS, RAS, and WE, and data signals DQ0 - DQ7
  • a clock signal, CLK is also coupled to both memory die
  • Control signals CKEO and CSO are coupled to memory die 1002U, and are asserted durmg read and write operations to this memory die Likewise, control signals CKEl and CSl are coupled to memory die 1002L
  • Memory die 1002U and 1002L are part of a first and a second memory bank, respectively
  • the memory die in this embodiment are 32M x 8 (I e 32 megabytes) each, resulting m a stacked memory package with a capacity of 64 megabytes Using a total of 18 stacked memory packages of this capacity results m a module capacity of one gigabyte
  • FIG. 7 is a drawmg of one embodiment the memory module illustrating the electrical interconnections associated with error correction functions
  • Memory module 1000 mcludes a printed circuit board upon which stacked memory packages 1002 are mounted Each of these packages has a data width of 8 bits, and includes two memory chips (1002U and 1002L from Figures 4 and 6) Depending on the organization of memory module 1000, some of these memory die may be used to store error correction check bits, while others may be used to store data bits
  • Memory module 1000 also includes an edge connector 1005, with a plurality of electrical contact pads 101 A plurality of signal lines 1020 couples the electrical contact pads 1015 to the stacked memory packages 1002 Data signals are conveyed along signal lmes 1020 between the stacked memory packages 1002 and electrical contact pads 1015 Data pm DO of each stacked memory package 1002 is shown coupled to electrical contact pads 1015 by signal lines 1020, with the respective position of the bit in the data word (I e DQ0, DQ16, etc ) shown The most significant bit of the data, DQ143,

Abstract

A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

Description

TITLE: A MEMORY EXPANSION MODULE WITH STACKED MEMORY PACKAGES
BACKGROUND OF THE INVENTION
1 Field of the Invention
This invention generally relates to memory hardware for computer systems, and more specifically to memory expansion modules for expanding memory in computer systems
2 Description of the Related Art
Many modern computer systems allow for memory expansion by way of single mime memory modules (SIMMs) and/or dual mime memory modules (DIMMs) SIMMs and DIMMs include small, compact circuit boards that are designed to mount easily into an expansion socket mounted on another circuit board, typically a computer motherboard The circuit boards used to implement SIMMs and DIMMs include an edge connector comprising a plurality of contact pads, with contact pads typically being present on both sides of the circuit board On SIMMs, opposing contact pads are connected together (l e shorted), and thus carry the same signal while at least some opposing contact pads on DIMMs are not connected, thus allowing different signals to be carried Due to this, higher signal density may be accommodated by DIMMs Memory elements of SIMMs and DIMMs are typically Dynamic Random Access Memory (DRAM) chips
DRAM chips store information as a charge on a capacitor, with the charge level representing a logic one or logic zero Since a capacitor charge will dissipate over time, DRAM chips require refresh cycles on a periodic basis
To access a location m a DRAM, an address must first be applied to the address mputs This address is then decoded, and data from the given address is accessed In modern DRAMs, rows and columns are addressed separately using row address strobe (RAS) and column address strobe (CAS) control signals By using RAS and
CAS signals, row and column addresses can be time-multiplexed on common signal lines, contact pads, and pms of the address bus This allows a greater number of memory locations that can be addressed without a corresponding increase in the number of required signal lines, contact pads, and pms
To address a memory location m a DRAM as described above, a RAS signal is asserted on the RAS input of the DRAM, and a row address is forwarded to row decode logic on a memory chip The contents of all locations in the addressed row will then be sent to a column decoder, which is typically a combination multiplexer/demultiplexer After row addressing is complete, a CAS signal is asserted, and a column address is sent to the column decoder The multiplexer in the column decoder will then select the corresponding column from the addressed row, and the data from that specific row/column address is placed on the data bus for used by the computer system
The demand for more memory m computer systems is ever increasing Advances in software has further driven the demand for greater memory capacity, as complex programs require more memory space with which to operate Along with the demand for greater memory capacity is the need for greater reliability in computer system operation As the capacity of memory modules mcreases so to does the possibility of an error or a failure Tracking errors to their source on a memory module may sometimes be a difficult and time-consuming process Tracing a signal from a contact on an edge connector to a specific pm on a memory device may be time consuming even when accurate schematics are available Furthermore, manually tracing a signal from an edge connector contact to a pm on a memory device may be prone to human error
SUMMARY OF THE INVENTION
The problems outlined above may m large part be solved by a memory expansion module in accordance with the present invention In one embodiment, a memory module includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system Mounted upon the circuit board is a plurality of stacked memory packages Each stacked memory chip package contains multiple memory chips, or die, withm the package These memory chips are typically Dynamic Random Access Memory (DRAM) In one embodiment, each stacked memory package mcludes two DRAM die The printed circuit board of this embodiment includes 18 locations for mounting the stacked memory packages, resulting in a memory module with a total of 36 memory die Also mounted upon the printed circuit board is at least one buffer (or line driver) chip for driving address and control signals to the plurality of memory die contained withm the stacked memory packages A clock driver chip is also mounted upon the printed circuit board for driving clock signals to the memory chips Also mounted on the printed circuit board is a storage unit, which provides module identification and signal routing information In one embodiment, a serial electrically erasable programmable read-only memory (SEEPROM) is used to implement the storage unit Information which correlates individual contact pads of the edge connector to individual pms of the stacked memory packages may be stored m the storage unit Using this information, an error detected by in the memory module may be quickly traced to a specific pm of a stacked memory package
Each memory d.e withm each stacked memory package may be individually accessed by a computer system Since the memory die withm the stacked memory packages may be accessed individually, multiple memory banks may be formed with each die withm a given package belonging to a different memory bank In one embodiment, each memory die is a 32M x 8. resulting m a stacked memory package with a capacity of 64M x 8 The total module capacity m this embodiment is 1 gigabyte In general, the memory module is scalable and may be implemented with various amounts of memory capacity
Thus, m various embodiments, the memory expansion module with stacked memory packages and error correction functionality may advantageously allow greater memory capacity The use of stacked memory packages may allow for greater memory capacity without the need for additional circuit board area The use of stacked memory packages with no more than two memory die each may advantageously reduce power consumption and thermal output by the memory module
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which
Figure 1 is a block diagram illustrating an embodiment of a computer system having a CPU, a memory controller, a CPU bus, and a plurality of memory modules.
Figure 2 is a mechanical drawing of one embodiment of a memory module, Figure 3 A is a block diagram illustrating the electrical connections associated with the top side of an embodiment of the memory module,
Figure 3B is a block diagram illustrating the electrical connections associated with the bottom side of an embodiment of the memory module, Figure 4 is a functional block diagram of one embodiment of the memory module,
Figure 5 is a pm diagram of one embodiment of a stacked memory package,
Figure 6 is a block diagram of the internal organization of one embodiment of a stacked memory package, Figure 7 is a drawing of one embodiment the memory module illustrating the electrical interconnections associated with error correction functions, and, Figure 8 is a table illustrating exemplary entries withm the storage unit correlating connector pms to integrated circuit pms
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail It should be understood, however, that the drawings and description thereto are not intended to limit the mvention to the particular form disclosed, but, on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling with the spirit and scope of the present invention as defined be the appended claims
DETAILED DESCRIPTION OF THE INVENTION
Referring now to Figure 1, an embodiment of a computer system 100 including a plurality of memory modules 1000, as will be described below, is shown The computer system includes a CPU 101, coupled to a memory controller 102 through a CPU bus 103 Memory controller 102 is configured to control communications and data transfers between CPU 101 and memory modules 1000
Memory controller 102 is coupled to each of the memory modules 1000 through a memory bus 104 Memory bus 104 includes a plurality of signal lines, each of which is associated with a single data bit position The width of memory bus 104 may be any number of bits, typical bus widths include 16 bits, 32 bits, 64 bits, and 128 bits Some embodiments of memory bus 104 may include extra signal lines for bits that may be used by error correction circuitry The bits conveyed by the extra signal lines are typically referred to as check bits For example, one embodiment of a memory bus may be configured to convey 128 data bits and 16 check bits, for a total bus width of 144 bits Error detection and correction is performed by error correction subsystem 106, located withm memory controller 102
In the embodiment shown, the memory modules are provided to expand mam memory of computer system 100, and are electrically coupled to memory bus 104 through a set of expansion sockets 105 An expansion socket 105 of the embodiment shown is configured to receive an edge connector of a prmted circuit board of a memory module 1000 Moving on to Figure 2, a mechanical drawmg of one embodiment of the memory module is shown
Memory module 1000 includes a plurality of stacked memory packages 1002 mounted upon both sides of a printed circuit board 500 Memory module 1000 also includes two lme driver chips 1003, one mounted on each side of the printed circuit board In this embodiment, clock driver chip 1004 is mounted on the top side of printed circuit board 500, while a storage unit 1006 is mounted on the bottom side Edge connector 1005 provides electrical contact between the various components of the module and the computer system 100 of Figure 1 In the embodiment shown, edge connector 1005 mcludes 232 electrical contacts Furthermore, a majority of opposmg electrical contacts of edge connector 1005 are not electrically connected, making this module a DIMM (dual mime memory module) Figures 3A and 3B are block diagrams illustrating the electrical connections associated with the top and bottom side, respectively, of one embodiment of the memory module Memory module 1000 includes a plurality of stacked memory packages 1002 mounted upon each side Memory module 1000 also mcludes edge connector 1005 for electrically couplmg memory module 1000 to the memory bus 104 of Figure 1 Edge connector 1005 mcludes a plurality of electrical contacts 1015 for conveying electrical signals between memory module 1000 and the memory bus As m Figure 2, a majority of opposing contacts in the embodiment shown are not electrically connected, making the module a DIMM
On each side of memory module 1000 is mounted a line driver (or buffer) chip 1003 Line driver chip 1003-A in Figure 3 A serves as an address buffer (for address signals), while line driver chip 1003-B in Figure 3B serves as a control buffer (for control signals) Lme driver chip 1003-A is configured to receive address signals from a memory bus of a computer system, via electrical contact pads 1015 and interconnecting signal lines In the embodiment shown, each address signal is split mto two separate signals Those address signals labeled A0(X) are driven to a first memory bank, while those labeled A1(X) are driven to a second memory bank Line driver chip 1003-B is configured to receive various control signals from a memory bus These control signals include chip select signals, CSO and CS1 as shown Other control signals (not shown) include row address strobe (RAS), column address strobe (CAS), clock enable (CKE), and write enable (WE)
The top side of the module also mcludes clock driver chip 1004 Clock driver chip 1004 is configured to receive clock signals from a computer system, and to drive these signals to the memory chips of the stacked memory packages 1002 In the embodiment shown, clock driver chip 1004 actually receives two differential PECL (pseudo emitter coupled logic) level signals, designated here as CLK+ and CLK- These differential signals are used as inputs to a phase-locked loop (PLL) circuit with the clock driver chip The output of the PLL is a singular clock signal, which is driven to each of the memory chips withm the stacked memory packages 1002 Other embodiments configured to receive a smgular clock signal (rather than multiple differential clock signals) are possible and contemplated
A storage unit 1006 is mounted upon the bottom side of the module In the embodiment shown, storage unit 1006 is a serial EEPROM (electrically erasable read-only memory) Other embodiments may use a flash memory or other type of device to implement storage unit 1006 In the embodiment shown, storage unit 1006 performs two functions The first of these functions is module identification, as storage unit 1006 may, m one embodiment, be configured to store a unique serial number for memory module 1000 This serial number may be read by a computer system into which the memory module is inserted Usmg the unique serial number, the module history may be traced from its time of manufacture, mcludmg any failure information
The second function of storage unit 1006 is the storage of error correction information In particular, the storage unit 1006 of the embodiment shown is configured to store information correlating pms of the connector edge to individual pms of stacked memory packages 1002 Using this information, an error detected by an error correction subsystem may be quickly traced to a specific pm of a specific stacked memory package 1002 Turning now to Figure 4, a functional block diagram of one embodiment of the memory module is shown Memory module 1000 mcludes a plurality of memory dιel002U and 1002L, wherein each pair of die is part of a stacked memory package 1002 of Figures 2 and 3 Typically, memory die 1002U and 1002L will be dynamic random access memory (DRAM) chips In the embodiment shown, a first bank and a second bank of memory are present The first bank of memory includes the shown plurality of memory die 1002U, while the second bank includes the shown plurality of memory chips 1002L Each memory die has a data width of 8 bits, and is coupled
Figure imgf000007_0001
Two buffers, or lme driver chips 1003 are used to drive address and control signals to the memory die 1002U and 1002L One line driver chip 1003 is used exclusively for address signals Each address signal received by the lme driver chip 1003 is duplicated twice and driven to a stacked memory package 1002 A second line driver chip 1003 is used to drive control signals to the memory die 1002U and 1002L withm each stacked memory package m order to control the individual banks of memory Each stacked memory package 1002 is configured to receive a RAS signal (RAS0 or RAS1), a CAS signal (CAS0 or CAS1 and a WE signal (WE0 or WEI) In addition, each stacked memory package 1002 is configured to receive control signals CSO, CSl, CKEO, and CKEl Also shown in Figure 4 is clock driver chip 1004, which is configured to receive two differential PECL clock signals, and drive a singular clock signal to each of the memory chips, as explained above with reference to Figure 3A
Figure 5 is a pm diagram of one embodiment of a stacked memory package 1002 In the embodiment shown, stacked memory package 1002 includes two memory die Each stacked memory package is configured to receive 8 data signals (DQ0-DQ7), 15 address signals (A0-A12 and BAO-BAl), and control signals CSO, CSl,
CKEO, CKEl, RAS, CAS, and WE Address signals BA0 and BA1 correspond to address signals A13 and A 14 as shown in Figure 4 In general, a limitation of two memory die per stacked memory package is placed upon the various embodiments of the memory module, due to considerations for power consumption and thermal output of the module Stacked packages with only two memory die may consume less power and generate less heat than those containing three or more memory die, while still allowing additional memory capacity without the need for additional circuit area relative to memory packages havmg a single memory die
Figure 6 is a block diagram of the internal organization of one embodiment of a stacked memory package The embodiment shown consists of memory die 1002U and 1002L Address signals A0-A14 are coupled to both memory die, as are control signals CAS, RAS, and WE, and data signals DQ0 - DQ7 A clock signal, CLK, is also coupled to both memory die Control signals CKEO and CSO are coupled to memory die 1002U, and are asserted durmg read and write operations to this memory die Likewise, control signals CKEl and CSl are coupled to memory die 1002L Memory die 1002U and 1002L are part of a first and a second memory bank, respectively The memory die in this embodiment are 32M x 8 (I e 32 megabytes) each, resulting m a stacked memory package with a capacity of 64 megabytes Using a total of 18 stacked memory packages of this capacity results m a module capacity of one gigabyte
Figure 7 is a drawmg of one embodiment the memory module illustrating the electrical interconnections associated with error correction functions Memory module 1000 mcludes a printed circuit board upon which stacked memory packages 1002 are mounted Each of these packages has a data width of 8 bits, and includes two memory chips (1002U and 1002L from Figures 4 and 6) Depending on the organization of memory module 1000, some of these memory die may be used to store error correction check bits, while others may be used to store data bits Memory module 1000 also includes an edge connector 1005, with a plurality of electrical contact pads 101 A plurality of signal lines 1020 couples the electrical contact pads 1015 to the stacked memory packages 1002 Data signals are conveyed along signal lmes 1020 between the stacked memory packages 1002 and electrical contact pads 1015 Data pm DO of each stacked memory package 1002 is shown coupled to electrical contact pads 1015 by signal lines 1020, with the respective position of the bit in the data word (I e DQ0, DQ16, etc ) shown The most significant bit of the data, DQ143, is coupled to pm D7 of a stacked memory package 1002 In this embodiment, 16 check bits are used to protect each data block of 128 bits, with each check word associated with one data block only As previously stated, some memory die of the stacked memory packages 1002 may be used exclusively to store check bits m this embodiment Each of these memory die may store four check bits of each check word In the embodiment shown, each check word is 16 bits, and protects a data block of 128 bits These check bits are accessed through a plurality of pms designated CBWX[y z] For example, CBW1 [3 0] shown in the drawing represents four pms of a stacked memory package 1002 through which check bits 0 through 3 of check word #1 are accessed Similarly, CBW2[7 4] represents those pms through which check bits 4 through 7 of check word #2 are accessed Each of these pms is connected to a respective signal line Representative signal lines are shown in the drawmg as CBW1 through CBW4 In general, these signal lines are routed on the printed circuit board m such a manner that physically adjacent memory cells within each memory die store check bits corresponding to different check words Figure 8 is a table illustrating exemplary entries withm the storage unit correlating connector pms to integrated circuit pms In the table shown, each connector pad of an edge connector (such as edge connector 1005 of Figures 3 A and 3B) is associated with a pm of an integrated circuit package (such as the stacked memory packages 1002 of Figures 3A and 3B) For example, connector pad #1 is associated with integrated circuit Ul, pm 5 (Ul 5) Similarly, connector pad #5 is associated with integrated circuit Ul, pm 9 Most if not all connector pads may be associated with at least one pm of one integrated circuit In many cases, certain connector pads may be associated with a plurality of integrated circuit pms Such connector pads may include those that carry address signals and enable signals (e g chip enable and write enable signals)
While the present mvention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited Any \ aπations, modifications, additions, and improvements to the embodiments described are possible These variations, modifications, additions, and improvements may fall withm the scope of the inventions as detailed withm the following claims

Claims

WHAT IS CLAIMED IS:
1 A memory module compπsmg a printed circuit board mcludmg a connector edge adapted for insertion withm a socket of a computer system, a plurality of stacked memory packages mounted upon said printed circuit board, each of said stacked memory packages mcludmg a first memory die and a second memory die, and wherein said first memory die of each of said stacked memory packages forms a portion of a first bank of memory and said second memory die of each of said stacked memory packages forms a portion of a second bank of memory, a clock driver chip, a storage unit for providing module identification and error correction check bit information, and, at least one lme driver chip configured to drive control signals and/or address signals
2 The memory module as recited in claim 1 , wherein said edge connector includes a plurality of electrical contact pads for conveying electrical signals
3 The memory module as recited m claim 2, wherem said edge connector has 232 of said electrical contact pads
4 The memory module as recited in claim 2, wherein said connector edge includes contact pads for receiving control signals, said control signals compπsmg at least one row address strobe (RAS) signal, at least one column address strobe (CAS) signal, at least one write enable (WE) signal, at least one clock enable (CKE) signal, and a least one chip select (CS) signal
5 The memory module as recited m claim 2, wherein said electrical signals include a plurality of address signals, and wherem said plurality of address signals form an address bus
6 The memory module as recited m claim 5, wherem said address bus is 14 bits wide
7 The memory module as recited in claim 2, wherem said electrical signals include a plurality of data signals, and wherein said plurality of data signals form a data path
8 The memory module as recited m claim 6, wherein said data path is 144 bits wide
9 The memory module as recited m claim 1, wherem said memory module is configured for use m a system having an error correction subsystem, said error correction subsystem configured to generate a plurality of check words corresponding to a plurality of data blocks 10 The memory module as recited m claim 2, wherem said storage unit is configured to store signal lme routing information which correlates each of said contact pads of said edge connector to a pm of a said stacked memory package
11 The memory module as recited in claim 1 , wherein said storage unit is configured to store module identification information
12 The memory module as recited m claim 11, wherem said storage unit is a serial electrically erasable programmable read-only memory (SEEPROM)
13 The memory module as recited in claim 1, wherem said first memory die and said second memory die are dynamic random access memory (DRAM) chips
14 The memory module as recited in claim 1, wherem said memory module is a dual-mhne memory module (DIMM)
15 The memory module as recited in claim 1, wherem said memory module has a memory capacity of one gigabyte
16 The memory module as recited in claim 1, wherem each of said stacked memory packages includes two memory die
17 A memory module compπsmg a printed circuit board including a plurality of signal lines for conveying electrical signals and a connector edge adapted for msertion withm a socket of a computer system, said edge connector having a plurality of contact pads for conveying said electrical signals between said memory module and a memory bus, a plurality of stacked memory packages, each havmg two memory die, mounted upon said printed circuit board, each of said stacked memory packages havmg a plurality of signal pms, a clock driver chip, a storage unit for storing module identification and information which correlates said electrical contact pads to said signal pms, and, at least one lme driver chip for dπvmg electrical signals to said stacked memory packages
8 The memory module as recited m claim 17, wherem said electrical signals include a plurality of control signals, a plurality of data signals, and a plurality of address signals
9 The memory module as recited in claim 18, wherem said plurality of data signals form a data path, said
Figure imgf000010_0001
The memory module as recited m claim 18, wherem said plurality of address signals form an address bus, said address bus 14 bits wide
The memory module as recited m claim 18, wherem said control signals include two column address strobe (CAS) signals, two row address strobe (RAS) signals, two write enable (WE) signals, two chip select (CS) signals, and two clock enable (CKE) signals
The memory module as recited m claim 17, wherem said memory module is a Dual Inline Memory Module (DIMM)
The memory module as recited in claim 17, wherein said memory die are synchronous dynamic random access memory (SDRAM) chips
The memory module as recited in claim 17m wherem said memory module has 232 of said contact pads
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Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271539A2 (en) * 2001-06-29 2003-01-02 Hewlett-Packard Company Memory device
EP1475836A1 (en) * 2003-05-08 2004-11-10 Infineon Technologies AG Circuit module having interleaved groups of circuit chips
DE102004025556A1 (en) * 2004-05-25 2005-12-22 Infineon Technologies Ag Electronic memory device, has interface unit that connects memory cell fields with respective external circuit units, and switching unit for switching external data line to memory field or system information memory unit
WO2010062655A3 (en) * 2008-10-28 2010-08-12 Micron Technology, Inc. Error correction in multiple semiconductor memory units
EP2458505A1 (en) * 2006-02-09 2012-05-30 Google Inc. Memory circuit system and method
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8949519B2 (en) 2005-06-24 2015-02-03 Google Inc. Simulating a memory circuit
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method

Families Citing this family (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2804266B1 (en) * 2000-01-20 2002-04-26 Auteuil Participation Et Conse METHOD AND SYSTEM FOR BROADCASTING DATA
US20030090879A1 (en) * 2001-06-14 2003-05-15 Doblar Drew G. Dual inline memory module
KR100468761B1 (en) * 2002-08-23 2005-01-29 삼성전자주식회사 Semiconductor memory system having memory module connected to devided system bus
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US8250295B2 (en) * 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
US7234081B2 (en) * 2004-02-04 2007-06-19 Hewlett-Packard Development Company, L.P. Memory module with testing logic
KR100593439B1 (en) * 2004-02-24 2006-06-28 삼성전자주식회사 Memory module and signal line placement method
US7532537B2 (en) * 2004-03-05 2009-05-12 Netlist, Inc. Memory module with a circuit providing load isolation and memory domain translation
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7046538B2 (en) * 2004-09-01 2006-05-16 Micron Technology, Inc. Memory stacking system and method
KR100564631B1 (en) * 2004-09-09 2006-03-29 삼성전자주식회사 Memory module with function for detecting command signal error
US7200021B2 (en) * 2004-12-10 2007-04-03 Infineon Technologies Ag Stacked DRAM memory chip for a dual inline memory module (DIMM)
US7266639B2 (en) * 2004-12-10 2007-09-04 Infineon Technologies Ag Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
JP4309368B2 (en) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 Semiconductor memory device
US7339840B2 (en) * 2005-05-13 2008-03-04 Infineon Technologies Ag Memory system and method of accessing memory chips of a memory system
US20060277355A1 (en) * 2005-06-01 2006-12-07 Mark Ellsberry Capacity-expanding memory device
US7590796B2 (en) * 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US7386656B2 (en) * 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8090897B2 (en) * 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
WO2007002324A2 (en) * 2005-06-24 2007-01-04 Metaram, Inc. An integrated memory core and memory interface circuit
US7580312B2 (en) * 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8041881B2 (en) * 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US20080126690A1 (en) * 2006-02-09 2008-05-29 Rajan Suresh N Memory module with memory stack
US7472220B2 (en) * 2006-07-31 2008-12-30 Metaram, Inc. Interface circuit system and method for performing power management operations utilizing power management signals
US7392338B2 (en) * 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
DE112006002300B4 (en) * 2005-09-02 2013-12-19 Google, Inc. Device for stacking DRAMs
KR100712540B1 (en) * 2005-12-13 2007-04-27 삼성전자주식회사 Memory module including memory chip block
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US20080028137A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and Apparatus For Refresh Management of Memory Modules
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7724589B2 (en) * 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US7840732B2 (en) * 2006-09-25 2010-11-23 Honeywell International Inc. Stacked card address assignment
DE102006051514B4 (en) * 2006-10-31 2010-01-21 Qimonda Ag Memory module and method for operating a memory module
US7344410B1 (en) 2006-12-19 2008-03-18 International Business Machines Corporation Blade server expansion
US8143720B2 (en) * 2007-02-06 2012-03-27 Rambus Inc. Semiconductor module with micro-buffers
US20080239852A1 (en) * 2007-03-28 2008-10-02 Reza Jazayeri Test feature to improve DRAM charge retention yield
US7545698B2 (en) * 2007-06-28 2009-06-09 Intel Corporation Memory test mode for charge retention testing
US8209479B2 (en) * 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US7584308B2 (en) * 2007-08-31 2009-09-01 International Business Machines Corporation System for supporting partial cache line write operations to a memory module to reduce write data traffic on a memory channel
US8086936B2 (en) * 2007-08-31 2011-12-27 International Business Machines Corporation Performing error correction at a memory device level that is transparent to a memory channel
US7840748B2 (en) * 2007-08-31 2010-11-23 International Business Machines Corporation Buffered memory module with multiple memory device data interface ports supporting double the memory capacity
US7899983B2 (en) 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7865674B2 (en) * 2007-08-31 2011-01-04 International Business Machines Corporation System for enhancing the memory bandwidth available through a memory module
US7861014B2 (en) * 2007-08-31 2010-12-28 International Business Machines Corporation System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
US7818497B2 (en) * 2007-08-31 2010-10-19 International Business Machines Corporation Buffered memory module supporting two independent memory channels
US8082482B2 (en) * 2007-08-31 2011-12-20 International Business Machines Corporation System for performing error correction operations in a memory hub device of a memory module
US8019919B2 (en) * 2007-09-05 2011-09-13 International Business Machines Corporation Method for enhancing the memory bandwidth available through a memory module
US7558887B2 (en) * 2007-09-05 2009-07-07 International Business Machines Corporation Method for supporting partial cache line read and write operations to a memory module to reduce read and write data traffic on a memory channel
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7925826B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequency
US8140936B2 (en) * 2008-01-24 2012-03-20 International Business Machines Corporation System for a combined error correction code and cyclic redundancy check code for a memory channel
US7770077B2 (en) * 2008-01-24 2010-08-03 International Business Machines Corporation Using cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem
US7925825B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to support a full asynchronous interface within a memory hub device
US7930469B2 (en) 2008-01-24 2011-04-19 International Business Machines Corporation System to provide memory system power reduction without reducing overall memory system performance
US7930470B2 (en) * 2008-01-24 2011-04-19 International Business Machines Corporation System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controller
US7925824B2 (en) * 2008-01-24 2011-04-12 International Business Machines Corporation System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequency
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8787060B2 (en) 2010-11-03 2014-07-22 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8417870B2 (en) * 2009-07-16 2013-04-09 Netlist, Inc. System and method of increasing addressable memory space on a memory board
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
US10236032B2 (en) * 2008-09-18 2019-03-19 Novachips Canada Inc. Mass data storage system with non-volatile memory modules
KR20100041515A (en) * 2008-10-14 2010-04-22 삼성전자주식회사 Method for testing a solid state drive having a removable auxiliary test terminals
US8674482B2 (en) * 2008-11-18 2014-03-18 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Semiconductor chip with through-silicon-via and sidewall pad
US8046628B2 (en) 2009-06-05 2011-10-25 Micron Technology, Inc. Failure recovery memory devices and methods
WO2010144624A1 (en) * 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
JP5521424B2 (en) * 2009-07-28 2014-06-11 セイコーエプソン株式会社 Integrated circuit device, electronic device, and method of manufacturing electronic device
JP2011048756A (en) * 2009-08-28 2011-03-10 Toshiba Corp Memory module
CN102955497A (en) * 2011-08-18 2013-03-06 鸿富锦精密工业（深圳）有限公司 Mainboard provided with solid-state drive
KR101917192B1 (en) 2012-03-12 2018-11-12 삼성전자주식회사 Nonvolatile memory device and reading method of nonvolatile memory device
CN110428855B (en) 2013-07-27 2023-09-22 奈特力斯股份有限公司 Memory module with local synchronization
US9128834B2 (en) 2013-09-24 2015-09-08 International Business Machines Corporation Implementing memory module communications with a host processor in multiported memory configurations
KR102254100B1 (en) * 2015-01-05 2021-05-20 삼성전자주식회사 Memory Device, Memory System and Operating Method of Memory Device
CN106557130B (en) * 2015-12-31 2023-11-24 深圳市嘉合劲威电子科技有限公司 Memory module and electronic device using same
KR102440182B1 (en) * 2016-04-11 2022-09-06 에스케이하이닉스 주식회사 Semiconductor package with optionally activating CE pads
WO2019066937A1 (en) * 2017-09-29 2019-04-04 Intel Corporation High density die package configuration on system boards

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0744748A2 (en) * 1995-05-15 1996-11-27 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US5661677A (en) * 1996-05-15 1997-08-26 Micron Electronics, Inc. Circuit and method for on-board programming of PRD Serial EEPROMS
EP0813204A2 (en) * 1992-05-19 1997-12-17 Sun Microsystems, Inc. Single in-line memory module

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890004820B1 (en) * 1984-03-28 1989-11-27 인터내셔널 비지네스 머신즈 코포레이션 Stacked double density memory module using industry standard memory chips
US5138438A (en) * 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
SG52794A1 (en) * 1990-04-26 1998-09-28 Hitachi Ltd Semiconductor device and method for manufacturing same
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
KR100209782B1 (en) * 1994-08-30 1999-07-15 가나이 쓰도무 Semiconductor device
US5513135A (en) * 1994-12-02 1996-04-30 International Business Machines Corporation Synchronous memory packaged in single/dual in-line memory module and method of fabrication
KR100204753B1 (en) * 1996-03-08 1999-06-15 윤종용 Loc type stacked chip package
US5831890A (en) * 1996-12-16 1998-11-03 Sun Microsystems, Inc. Single in-line memory module having on-board regulation circuits
US5867448A (en) * 1997-06-11 1999-02-02 Cypress Semiconductor Corp. Buffer for memory modules with trace delay compensation
JP3937265B2 (en) 1997-09-29 2007-06-27 エルピーダメモリ株式会社 Semiconductor device
US5956233A (en) * 1997-12-19 1999-09-21 Texas Instruments Incorporated High density single inline memory module
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6324071B2 (en) 1999-01-14 2001-11-27 Micron Technology, Inc. Stacked printed circuit board memory module

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0813204A2 (en) * 1992-05-19 1997-12-17 Sun Microsystems, Inc. Single in-line memory module
EP0744748A2 (en) * 1995-05-15 1996-11-27 Silicon Graphics, Inc. High memory capacity DIMM with data and state memory
US5661677A (en) * 1996-05-15 1997-08-26 Micron Electronics, Inc. Circuit and method for on-board programming of PRD Serial EEPROMS

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271539A2 (en) * 2001-06-29 2003-01-02 Hewlett-Packard Company Memory device
KR20030003054A (en) * 2001-06-29 2003-01-09 휴렛-팩커드 컴퍼니(델라웨어주법인) Method for reducing the number of interconnects to the pirm memory module
EP1271539A3 (en) * 2001-06-29 2004-06-23 Hewlett-Packard Company Memory device
CN100382199C (en) * 2003-05-08 2008-04-16 因芬尼昂技术股份公司 Circuit module having interleaved groups of circuit chips
US6917100B2 (en) 2003-05-08 2005-07-12 Infineon Technologies Ag Circuit module having interleaved groups of circuit chips
EP1475836A1 (en) * 2003-05-08 2004-11-10 Infineon Technologies AG Circuit module having interleaved groups of circuit chips
DE102004025556A1 (en) * 2004-05-25 2005-12-22 Infineon Technologies Ag Electronic memory device, has interface unit that connects memory cell fields with respective external circuit units, and switching unit for switching external data line to memory field or system information memory unit
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8949519B2 (en) 2005-06-24 2015-02-03 Google Inc. Simulating a memory circuit
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
EP2458505A1 (en) * 2006-02-09 2012-05-30 Google Inc. Memory circuit system and method
EP2706461A1 (en) * 2006-02-09 2014-03-12 Google Inc. Memory circuit system and method
EP3276495A1 (en) * 2006-02-09 2018-01-31 Google LLC Memory circuit system and method
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US8799743B2 (en) 2008-10-28 2014-08-05 Micron Technology, Inc. Error correction in multiple semiconductor memory units
WO2010062655A3 (en) * 2008-10-28 2010-08-12 Micron Technology, Inc. Error correction in multiple semiconductor memory units
US10019310B2 (en) 2008-10-28 2018-07-10 Micron Technology, Inc. Error correction in multiple semiconductor memory units

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JP3999516B2 (en) 2007-10-31
AU1920001A (en) 2001-05-30
ATE384293T1 (en) 2008-02-15
EP1232439B1 (en) 2008-01-16
KR100626223B1 (en) 2006-09-20
KR20020070979A (en) 2002-09-11
DE60037828D1 (en) 2008-03-06
EP1232439A1 (en) 2002-08-21
JP2003515216A (en) 2003-04-22
US6683372B1 (en) 2004-01-27

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