WO2001044900A2 - Branch-else-return instruction - Google Patents
Branch-else-return instruction Download PDFInfo
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- WO2001044900A2 WO2001044900A2 PCT/EP2000/012441 EP0012441W WO0144900A2 WO 2001044900 A2 WO2001044900 A2 WO 2001044900A2 EP 0012441 W EP0012441 W EP 0012441W WO 0144900 A2 WO0144900 A2 WO 0144900A2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
Definitions
- This invention relates to the field of processing systems, and in particular to a processor for use in a cryptographic system
- a compliant CD-recorder will recognize this "copy-never” notation and will not create a copy of this copy. If the material is copied by a non-compliant recorder, it will not contain the appropriate cryptographic item, and a compliant recorder or playback device will not record or render this copied material.
- Standards have also been adopted for encrypting, signing, and authenticating transmitted content material, such as e-mail documents and attachments.
- the content material may be encrypted, and/or a cryptographically secure item may be attached to the content material that identifies the source of the content material.
- the secure item is attached, or "bound", to the material in such a manner that a decryption of the secure item will identify whether the content material has been modified since it was originally transmitted.
- Every compliant audio or video recording or playback device including both stationary and portable devices, must contain a means for processing or exchanging keys or other secure items, and generally must contain a cryptographic signing or verification device, or both.
- Every e-mail transmission or reception device including multi-functioned devices such as cell-phones, will be expected to contain a signing or verification device, or both.
- a processing device that facilitates cryptographic signing, verification, and key processing in a variety of systems.
- a custom designed circuit may be the least costly embodiment of a device that implements an encryption or decryption process for digital signing, verification and other authentication tasks, the evolving nature of cryptography introduces the risk that the embodied algorithm will become obsolete.
- a general-purpose programmable processor will allow the embodied algorithm to change as cryptographic techniques change, but will not necessarily be economically feasible for inclusion in every device that requires cryptographic capabilities.
- a low-cost general-purpose processor may not achieve the performance goals expected on a real-time authentication process, for example, and auxiliary devices or a higher-speed processor may be required, at an increased cost. Even if the cost objectives can be met by a low-cost processor and auxiliary devices, the physical constraints of the containing system, such as a cell phone, may preclude the use of these auxiliary devices.
- processor architecture and instruction set that is particularly well suited for cryptographic processing.
- a variety of techniques are employed to minimize the complexity of the design and to minimize the complexity of the interconnections within the device, thereby reducing the surface area required, and associated costs.
- a variety of techniques are also employed to ease the task of programming the processor for cryptographic processes, and to optimize the efficiency of instructions that are expected to be commonly used in the programming of such processes.
- a single-port random-access memory (RAM) is used for operand storage, few data busses and registers are used in the data-path, and the instruction set is optimized for parallel operations within instructions.
- a simplified arithmetic unit is provided that efficiently supports the functions typically required for cryptographic operations with minimal overhead.
- a microcode-mapped instruction set is utilized in a preferred embodiment to facilitate multiple parallel operations in each instruction cycle and to provide direct processing control with minimal overhead.
- FIG. 1 illustrates an example block diagram of a data path architecture for a cryptographic processing system in accordance with this invention.
- FIG. 2 illustrates an example pair of instruction set formats for a cryptographic processing system in accordance with this invention.
- FIG. 3 illustrates an example block diagram of a control path architecture for a cryptographic processing system in accordance with this invention.
- FIG. 4 illustrates an example block diagram of a microinstruction mapping for a cryptographic processor in accordance with this invention.
- reference numerals between 100 and 199 refer to items introduced in FIG. 1; reference numerals between 200 and 299 refer to items introduce in FIG. 2; reference numerals between 300 and 399 refer to items introduced in FIG. 3, and reference numerals between 400 and 499 refer to items introduced in FIG. 4.
- This invention is based on the observation that cryptographic operations, such as digital signing and verification, public-private key exchange processes, and so on, typically involve large data variables, but relatively simple arithmetic operations.
- a common 4 algorithm for authentication systems is Digital Signature Algorithm (DSA).
- Another common algorithm that has been proposed as a standard (ANSI X9.62) for digital signing and verification is the Elliptic Curve Digital Signature Algorithm (ECDSA).
- ECDSA Digital Transmission Content Protection system
- DTCP Digital Transmission Content Protection system
- the ECDSA is particularly well suited for a low-cost embodiment, because the use of elliptical curves involves the simple mathematical operations of addition, subtraction, multiplication, and inversion.
- the size of the data variable used for digital signing and verification is large, typically 160 or 320 bits wide.
- a 32-bit wide data word size is used in a preferred embodiment, to evenly divide the data item into five or ten words.
- the selected data word size is a design tradeoff: a larger word size requires additional wiring and routing, and a smaller word size requires additional word operations per data item. Recognizing that a wide data word incurs significant wiring and routing overhead, the data flow and control structure in accordance with this invention is significantly limited compared to conventional processing systems.
- a single ROM for instructions and constants and a single RAM for variables are preferred, to minimize circuit complexity and routing.
- the data constants are preferably the same size as the data word, and are preferably stored in the same ROM as the instructions, the instruction word size in a preferred embodiment is equal to the data word size.
- FIG. 1 illustrates an example block diagram of a data flow architecture 100 of a processing system in accordance with this invention.
- the processing system is optimized for minimal routing complexity, as compared to conventional 32-bit processing systems.
- the arithmetic-unit (AU) 110 comprises merely an adder 112 and two pre-op devices 114, 116.
- This simplicity provides a consistency of operation that facilitates parallel operations.
- the memory 120 is a single port RAM with a minimal output fanout. This minimal fanout also provides a consistency of operation that facilitates parallel operations, as well as providing a minimization of data routing paths.
- the registers 130, 140 are configured with a single input, from the output 111 of the AU 110, and limited output.
- the contents of the address registers 130 for example, are provided solely for addressing the RAM 120, and cannot be provided as an input to the NU 110, or any other processing devices, as would typically be common in a conventional processor design.
- the registers 140 do not provide an output per se, but are used, as discussed further below, to provide condition bits for controlling repetitive operations, such as multiplication. This restricted use of registers 130, 140 minimizes the routing of interconnections required for each register, and allows the registers 130, 140 to be optimally sized for the function served.
- the address registers 140 need only be wide enough to span the address range of the memory 120, while the scan registers 140 need only be wide enough to contain the relevant control flags.
- FIG. 2 illustrates two example instruction formats 201 , 202 in accordance with this invention.
- the instruction formats 201, 202 have a large number of common instruction fields.
- a preferred embodiment of an instruction set comprising 32 bits for each instruction includes the use of multiple fields within each instruction, discussed below, to effect parallel operations within each instruction. These multiple fields would not be available in a conventional narrow-word instruction set embodiment that is configured to support the relatively few instruction types, or would be infeasible for inclusion in a wide- word instruction set embodiment that is configured to support a large number of instruction types.
- the instruction format field 210 identifies the particular format used for the instruction, and provides the distinction between the illustrated formats 201, 202 and others. In a preferred embodiment, three bits are provided, thereby supporting up to eight different formats. In accordance with this invention, the eight different formats will exhibit a strong correlation of instruction bits, to simplify the decoding of instruction fields. Select fields are common to each of the different formats, so that commonly utilized parallel operations can be performed regardless of the format type. For example, in a preferred embodiment, the fields 230, and 240 are common to each format type, so that the operation implied by the value in each field 230, and 240, the control and selection of a memory access, can be effected during each instruction cycle, regardless of the particular instruction that is being performed.
- the "k follows" field 212 is used to signal that the following "instruction" contains a constant, or data- item, k.
- the use of this field 212 provides at least two advantages: it allows the constant k that is contained in the next instruction to occupy the entire instruction word size (in a preferred embodiment, 32 bits), and, it allows this value k that is contained in the next instruction to be loaded into the register rO at the next instruction cycle.
- a bit is typically set aside in both the instruction word and the constant word to distinguish between the two, thereby limiting the size of the constant word to one bit less than the full instruction width.
- alternative formats are provided that contain a "constant" field within the instruction; in these formats, the constant k that is provided is less than 32 bits, and the unspecified higher-order bits associated with a 32-bit constant value of k are either zero-filled or sign-extended, depending upon the particular format.
- These foreshortened values of k are typically provided as offset values for computing a memory address relative to a base address, or as a distance value for a relative branch instruction, specifying how far to branch from the current instruction location to reach the next intended instruction.
- the "update flags" field 214 is used to identify whether or not to modify the condition flags associated with the processing system when this instruction is executed.
- Copending U.S. patent application "Branch Instructions with Decoupled Condition and Address", serial number 09/466,405, filed 17.12.1999, incorporated by reference herein, discloses the decoupling of condition evaluations from branch instructions, and other conditional instructions, including the express identification of when condition flags should be saved for subsequent use in a conditional instruction.
- the conventional system flags 118 of FIG. 1, such as carry, zero, and even, and other condition flags, discussed below, are saved, and not updated until another instruction contains an affirmative value in field 214.
- the "memory access control" field 230 determines whether the memory 120 is accessed, and if so, whether it is accessed for a read operation or a write operation.
- the memory 120 is a single port memory, and the fanout of the memory 120 is limited, thereby allowing for a relatively simple memory access control.
- the field 230 is common to all instructions, thereby allowing for a memory read or write in parallel with any other instruction.
- the "address select" field 240 determines which input to the selector 180 is used to address the memory 120.
- the selected address may be an indirect address location IDA 185, the output 111 of the AU 110, an external address extA 188, or one of the address registers 130.
- a memory select operation can be effected in parallel with any other instruction. It is also significant to note that there is no register element between the memory 120 and the AU 110, as would typically be found in a conventional processing system, thereby allowing the AU 110 to access memory items directly, without an intermediate "load register" instruction.
- the "addressed register change" field 242 operates in conjunction with the address select field 240, and allows for incrementing or decrementing the addressed register during the same instruction cycle that the memory contents at the incremented or decremented address is provided to the AU 1 10.
- the addressed register change field 242 in a preferred embodiment of this invention includes states that effect the circular increment and decrement functions for each of the address registers 130, as determined by the address select field 240.
- the ability to circularly increment an address provides the contents of the circularly incremented address to an AU, perform an arithmetic operation on the contents, store the result in a destination register (discussed below), and circularly increment another register (discussed below), all within a single instruction cycle, is particularly well suited for cryptographic and other applications involving multi-word data items.
- the external address extA 188 allows an external processor to access the RAM 120 substantially independent of the processing system 100. That is, in a preferred embodiment of this invention, for example, a host system can be given access to the RAM 120 by setting the address select field to an appropriate value that selects the extA 188 input for addressing the RAM 120. The host system can then load data directly into the RAM 120, to the location addressed by extA 188, via the extDI input 187.
- This input data could be, for example, a hash value that is bound to an electronic document or ticket and a key that is used to encrypt this hash value to form a digital signature associated with the document or ticket.
- the processing system 100 After loading the hash value and key, the processing system 100 regains access to the RAM, performs the appropriate cryptographic function to provide a corresponding digital signature, which will be located in the RAM 120.
- the host system is then again provided direct access to the RAM 120 via extA 188, whereupon the host system reads the digital signature from the RAM 120, from each location addressed by extA 188, via the data out port extDO 186. That is, in accordance with this aspect of the invention, by providing an external addressing access to the RAM 120, the processing system 100 need not directly support memory transfer functions.
- the next four fields, "right operand pre-op" 250, “left operand pre-op” 252, "adder function” 260, and "nd select” 262 control the operation of the AU 110 and associated components register rO 150 and selector 160.
- the left operand pre-op field 252 determines whether an addressed item in the memory 120 is to be used directly; if not, a zero is provided as the left operand input to the AU 110.
- the nd select field 262 determines whether the output 111 of the AU 110, or a constant k 165, is provided as an input to the register rO 150.
- the right operand pre-op field 250 determines whether and how the contents of the register rO 150 is provided as the right input to the AU 110.
- the right operand pre-op field 250 provides for a direct communication of the contents of the register rO 150 to the adder 112 (a "null" pre-operation), a left and right shifting of the contents of the register rO 150, or an inversion of the contents of the register rO 150, as a parallel operation during the execution of the instruction. As the name of the field implies, this parallel operation is performed before the arithmetic operation specified in the instruction.
- the right operand pre- op field 250 also allows for a zero value to be supplied as the right input to the adder 112, thereby facilitating a transfer of a value md from the RAM 120 to another location in RAM 120, or to one of the registers 130, 140, 150.
- the adder function field 260 determines whether the addition of the left and right input to the AU includes an addition of a carry value, or an inverted carry, or a constant 1.
- the combination of pre-op functions 114 and 116 and the adder function 112 provides for monadic as well as dyadic addition functions, as well as subtraction, and multiplication and division by two.
- the ability to shift a prior result and add it to another operand with the carry bit within a single instruction cycle, as provided by the fields 250, 252, and 260 in accordance with this invention, is particularly well suited for the multiplication processes that are common in the field of cryptography, and other applications involving the multiplication of multi-word data items.
- the "destination register” field 270 identifies where the result 11 1 of the operation at the AU 110 is routed. As noted above, to minimize routing complexity in a preferred embodiment, the fanout of the output 111 of the AU 110 is limited to the registers 130, 140, and to the input register rO 150 associated with the AU 110.
- the update register change field 282 defines yet another parallel operation that can be effected during the processing of the instruction.
- the update register change field 282 is similar to the addressed register change field 242, in that it can effect an increment or decrement to the update register that is identified by the update register field 280, including a circular pointer increment or decrement operation.
- the instruction format 201 facilitates the execution of multiple operations in parallel during the execution of a single instruction that utilizes this format to perform a primary function, for example, an arithmetic operation.
- Alternative instruction formats, identified by the instruction format field 210, provide for other primary functions, while facilitating parallel operations.
- the instruction format 202 of FIG. 2 illustrates an example format that is used in a preferred embodiment for a branch or call operation in parallel with other auxiliary operations.
- the fields 212, 214, 230, and 240 are common to all instructions in a preferred embodiment, and as illustrated in FIG. 2, the fields 250, 252, 260, and 262 are common between the formats 201 and 202.
- the above referenced operations associated with fields 212, 214, 230, 240, 250, 252, 260 and 262 are performed at the same time that a branch or call operation is performed.
- condition field 220 and associated "invert condition” field 222, are used to determine which of two subsequent locations will be used to provide the next instruction to be executed. That is, if the condition 220 is in a first state, the program proceeds from a first address, otherwise it proceeds from a second address; the invert condition field 222 determines whether the aforementioned first state corresponds to a "true” or a "false” state. As illustrated in FIG. 2, the condition field 220 in a preferred embodiment utilizes six bits; thereby, up to 64 different conditions can be tested.
- one of the conditions of field 220 in accordance with this invention includes a data-item-equals-zero condition, and another condition corresponds to a data-item-equals-one condition.
- the data-item-equals- zero condition is set to true when each of the data words corresponding to a multiple- word data item equals zero
- the data-item-equals-one condition is set to true when each of the data words corresponding to a multiple- word data item equals zero except the least significant data word, which contains a value of one.
- condition items include the state of particular bits in the scan registers 140, such as the least-significant and most-significant bits of each word stored in the scan registers 140, thereby facilitating efficient multiplication operations of multi-word multiplicands.
- Other condition items include the status of the address pointers that are used to select the address registers 130, to facilitate the identification of the beginning and end of a multi-word processing operation.
- providing up to 64 different conditions within a branch or call instruction provides for an efficient and effective means for controlling and optimizing complex iterative operations, such as the multiplication of multi-word operands, as typically performed in cryptographic operations.
- the "next instruction" field 290 controls the program flow by controlling the address from which each next instruction is provided to the processing system.
- FIG. 3 illustrates an example block diagram of a control path architecture 300 for a processing system in accordance with this invention.
- Each instruction 331 is provided to the processing system from a memory, illustrated in FIG. 3 as a ROM 330.
- the sequence of instruction- addresses 371 determines the sequence of individual instructions 331 that are provided to the processing system.
- the instructions 331 are formatted as discussed above with regard to FIG. 2.
- the program counter 310 contains the current instruction-address 371, and the selectors 340, 350, and 370 and adder 360 determine the address of the next instruction, based on the state of the next instruction field 290, as discussed below.
- the second and third determinations ii and iii are each a conventional conditioned branch. If the condition is true (or if the condition is false and the "invert condition" field 222 is affirmative), the program counter pc is set to a specified address k, or to a determined address rO (contained in register rO 150 of FIG. 1); otherwise, it is advanced by one.
- the fourth determination iii is a conventional conditional call, wherein if the condition is true, the next sequential instruction address, pc+1, is pushed onto the stack 320, and the program counter is set to the specified address k.
- the fifth determination v is a conventional conditional return, wherein if the condition is true, the prior pushed next sequential address after a call is popped off the stack 320 and placed into the program counter.
- the sixth determination vi is a conventional relative branch instruction, wherein a constant (positive or negative) is added to the current program counter to determine the address of the next instruction. Note that a single adder 360 handles both the program counter increment operation as well as the calculation of relative branch addresses.
- the instruction set includes a "Branch If, Else Return” instruction, wherein if the condition is true, the program branches to the specified or relative address, but if the condition is false, the program returns from a subroutine call by popping the return address off the stack.
- An "Else Return" construct within a conditional statement is particularly effective and efficient in subroutines that perform iterative operations, wherein the same instruction is used to branch to an address to effect the next iteration or to return when the iterations have been completed.
- Other variations of techniques for determining a subsequent next instruction will be evident to one of ordinary skill in the art in view of this disclosure.
- FIG. 4 illustrates an example block diagram of a processor 400 that represents an effective and efficient structure for providing the features and capabilities discussed above.
- processing circuitry 450 operates in response to a microcode instruction 455 that comprises control bits 455b that control each switch and state device within the processing circuitry 450. That is, for example, the processing circuitry 450 typically comprises a state machine and the microcode instruction 455 provide the input stimuli to this state machine that controls the transition to the next state as well as controlling the production of an output from this state machine.
- the microcode instruction 455, for example, contains a control bit that will determine whether the selector 160 of FIG.
- 1 is set to provide the constant k 455a that is also contained in the microcode instruction 455, or the output result 111 of the arithmetic unit AU 110, to the register rO 150. It also contains a set of control bits that determines which address input is selected by the selector 180 to address the RAM 120, a set of control bits that determines the operation performed by the pre-op device 116, a control bit that determines the operation performed by the pre-op device 114, and so on. It will be recognized that the aforementioned fields within the instruction formats 201, 202 correspond substantially to these microcode control bits 455b.
- the fields of the instruction formats 201, 202 are provided that substantially correspond to select elements of a microcode instruction 455 thereby facilitating a direct control of the underlying processing circuitry 450 with minimal overhead.
- the control fields 410 of an instruction 331 are provided as input to a format mapper and default device 440 that maps each control field 410 of the instruction 331 to a corresponding control element in the microcode 455.
- a format mapper and default device 440 maps each control field 410 of the instruction 331 to a corresponding control element in the microcode 455.
- both the constant k 455a and the control bits 455b affect the operation and result provided by the processing circuitry 450, and are included in the definition of a control element of the microcode 455.
- the mapper/default device 440 comprises a plurality of selectors 441-449 that route each bit of the control field 410 to a corresponding control bit 455b, depending upon the given format 210 of the instruction 331. That is, for example, in FIG. 2, the different instruction formats 201 and 202 include different fields (242, 280, 282) and (290, 220) in the bit positions 23-31 of the instruction. The mapper/default device 440 routes the different fields from the same bit position of an instruction to different control elements of the microcode instruction, depending upon the format 210 of the instruction 331.
- the mapper/default device 440 appropriately controls the control elements of the microcode instruction 455 in the absence of a mapped field from the instruction 331, by providing default control values for each control element 455. That is, for example, the example instruction formats 201, 202 do not include a constant field for setting the value of k 455a in the microcode instruction 455.
- the default interpretation for the absence of a specified constant field in an instruction 331 in a preferred embodiment is a null operation. That is, in the absence of a specified constant value, the value k 455a remains the same.
- the type mapper 430 is illustrated as receiving the format field 210 of the instruction 331 as a control input only.
- the type mapper/default device 440 is configured to route the entire instruction 331 to the constant k segment 455a of the microcode instr ⁇ ction 455 whenever the previous instruction contains an affirmative k-follows field 212.)
- the output of the multiplexer/selector associated with each control element 455 is dependent upon the content of the format field 210, and the inputs are dependent upon the available default options.
- one or more format types (not illustrated) of a preferred embodiment contain a constant field that is less than the full width of the instruction word.
- the corresponding multiplexers 441-449 are configured to select either a zero value or a sign- extended value to place in each of the unspecified higher-order bit locations of the constant k 455a.
- the constant field in the instruction contains six bits
- the upper twenty- six bits of the 32-bit constant k 455a may be set to a default value of zero, or to a default value that is equal to the most significant bit of the specified six bits (sign-extended value), depending upon the particular format type.
- the control bits 455b are also provided default values, in most cases a null operation.
- a default value or condition for each control element of the microcode instruction 455 can be any value or condition, but in a preferred embodiment, the default values and conditions are chosen to be those that would be consistent with an assumed value by one of ordinary skill in the art. That is, for example, the zero-ing of higher order bits when a shortened data constant is provided, and the sign- extension of higher order bits when an address offset is provided, would be assumed to be proper defaults by one of ordinary skill in the art. In like manner, the default condition of the set of control bits corresponding to the next instruction field 290 of format 202 would be assumed to correspond to an advancement of the program counter by one instruction.
- the default interpretation module 440 sets the appropriate control elements in the macroinstruction 455 corresponding to the absent field 290 such that the selectors 340, 350, and 370 are set to select the appropriate inputs to effect an increment of the program counter 310, thereby providing a consistent, predictable, and logical effect in the absence of an explicit instruction field.
- a condition element can be defined that identifies the most-significant non-zero word in a data item, to facilitate the control of multiword operations such as multiplication and addition.
- the indirect address pointer, IDA 185 in FIG. 1 can be a predetermined address, such as address 0, of the RAM 120, so as to minimize the circuitry and time required to access an indirect address.
- the data items that are addressed by the address registers 130 may be constrained to lie within a specified area of the memory 120, so that the registers 120 can be of the minimum width required to span the addresses within this specified area, using for example an offset base address, rather than a width required to span the entire memory 120.
- the principles presented herein are particularly well suited for cryptography applications, the techniques and structures presented in this disclosure can be applied to processing systems that are customized for other applications, particularly those that utilize wide data-items and or employ relatively simple but repetitive operations.
- the example embodiments are illustrated herein in a minimalist form, to achieve a low production cost, additional capabilities can be added to improve performance or to ease the programming task.
- the examples provided in the figures are presented for illustration purposes.
- a single port RAM 120 is illustrated in FIG. 1, which provides for a minimal routing and interconnect area for addressing the RAM 120.
- a multiport RAM such as a two or three port RAM, and an associated format type to accommodate the multiple addressing capabilities, would provide for multiple memory accesses in the same instruction cycle, a preset of memory addresses before the memory access, and so on, by employing the principles presented above.
- Other system configuration, application, and optimization techniques will be evident to one of ordinary skill in the art, in view of this invention, and are within the spirit and scope of the following claims.
Abstract
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP00983265A EP1236077B1 (en) | 1999-12-17 | 2000-12-07 | Branch-else-return instruction |
JP2001545927A JP2003517671A (en) | 1999-12-17 | 2000-12-07 | Simple algorithm crypto engine |
DE60033961T DE60033961T2 (en) | 1999-12-17 | 2000-12-07 | BRANCH AND BACKUP COMMAND |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/466,392 | 1999-12-17 | ||
US09/466,392 US7032100B1 (en) | 1999-12-17 | 1999-12-17 | Simple algorithmic cryptography engine |
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WO2001044900A2 true WO2001044900A2 (en) | 2001-06-21 |
WO2001044900A3 WO2001044900A3 (en) | 2002-07-11 |
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PCT/EP2000/012441 WO2001044900A2 (en) | 1999-12-17 | 2000-12-07 | Branch-else-return instruction |
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US (1) | US7032100B1 (en) |
EP (1) | EP1236077B1 (en) |
JP (1) | JP2003517671A (en) |
KR (1) | KR100760371B1 (en) |
DE (1) | DE60033961T2 (en) |
TW (1) | TW505839B (en) |
WO (1) | WO2001044900A2 (en) |
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US7653602B2 (en) | 2003-11-06 | 2010-01-26 | Visa U.S.A. Inc. | Centralized electronic commerce card transactions |
US11132691B2 (en) | 2009-12-16 | 2021-09-28 | Visa International Service Association | Merchant alerts incorporating receipt data |
US8429048B2 (en) | 2009-12-28 | 2013-04-23 | Visa International Service Association | System and method for processing payment transaction receipts |
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Also Published As
Publication number | Publication date |
---|---|
EP1236077B1 (en) | 2007-03-14 |
EP1236077A2 (en) | 2002-09-04 |
KR100760371B1 (en) | 2007-09-20 |
DE60033961T2 (en) | 2007-12-06 |
WO2001044900A3 (en) | 2002-07-11 |
JP2003517671A (en) | 2003-05-27 |
TW505839B (en) | 2002-10-11 |
KR20010102201A (en) | 2001-11-15 |
DE60033961D1 (en) | 2007-04-26 |
US7032100B1 (en) | 2006-04-18 |
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