WO2001056154A2

WO2001056154A2 - Digital filter

Info

Publication number: WO2001056154A2
Application number: PCT/DE2001/000258
Authority: WO
Inventors: Jain Raj Kumar; Low Seo How
Original assignee: Infineon Technologies Ag
Priority date: 2000-01-28
Filing date: 2001-01-19
Publication date: 2001-08-02
Also published as: WO2001056154A3; DE10003700A1

Abstract

A digital filter is disclosed, which is characterised, in that at least one of the multipliers in sequential multiplication procedures and/or at least one of the adders in sequential adding procedures, may be fed data representing various variables or constants and/or the results from sequential multiplication or adding processes may be differently further processed. Said digital filter may be produced at minimal outlay.

Description

description

Digital filter

The present invention relates to a device according to the preamble of claim 1, i. H. a digital filter with one or more multipliers and / or adders.

Such a filter is, for example, a so-called Butterworth IIR filter.

When using

as the transfer function of a second degree digital IIR filter, and with

bio = i2 = 1

and

bn = -2

a fourth degree Butterworth IIR filter can be performed by the transfer function

1-2 + z -2 1-2 - -l1 J +. _z-2

H (z) = Cθ ^• Cl - - 'C ₂

1 + an z ^"1 + ai2 z ² 1 + a2i z + a22 z ²

characterize and implement by the arrangement shown in Figure 2. The arrangement according to FIG. 2 comprises multipliers Ml to M9, adders AI to A8, delay elements Dl to D4, and quantizing devices Ql to Q3.

In the example under consideration, the signals to be filtered comprise 16 bits and, after five zeros have been added after their least significant bit, are input into the filter arrangement via an input connection I. The result of the filtering is a 16-bit signal which is output from an output connection 0 of the filter arrangement.

The filter arrangement according to FIG. 2 results from the standard implementation of the predetermined transfer function in hardware. Therefore, and because it can also be easily understood from FIG. 2, how the input signals are processed in the filter arrangement, a further explanation of the filter arrangement according to FIG. 2 is omitted.

For the sake of completeness, it should be pointed out

- that the information contained in the blocks representing the multipliers Ml to M9 indicate the value by which the data supplied to the respective multipliers are multiplied,

- that the numbers indicate, in addition to the connecting lines between the individual filter arrangement units, the number of bits which comprise the values transferred via the respective connecting lines, and

- That the information contained in the blocks representing the quantization devices Q1 to Q3 indicate the numbers of the bits that let the respective quantization devices pass (the other bits are cut off). Filtering carried out by the filter arrangement according to FIG. 2 leads exactly to the desired result (to the result defined by the transfer function). However, the practical implementation of the filter arrangement requires a very high outlay: in the example considered, a total of 9 multipliers, 8 adders, 4 delay elements and 3 quantization units are required.

Digital filters can also be software, i.e. by executing an appropriate program on a program-controlled unit such as a microprocessor, a microcontroller or a signal processor. Since the filtering to be carried out usually has to be carried out in real time, the program-controlled units used for the filtering must have a very high computing power, as a result of which this possibility of filter implementation is also associated with a very high outlay.

The same applies to digital filters other than the Butterworth IIR filter mentioned.

The present invention is therefore based on the object of developing the digital filter in accordance with the preamble of claim 1 in such a way that it can be implemented with minimal effort.

This object is achieved according to the invention by a digital filter which has the features claimed in the characterizing part of patent claim 1.

The digital filter according to the invention is characterized in that at least one of the existing multipliers can be supplied with data representing different variables or constants during successive multiplication processes and / or that the results of successive multiplication processes are processed differently and / or that at least one of the in front- existing adders can be supplied with data representing different variables or constants during successive addition processes and / or that the results of successive addition processes are processed differently.

This makes it possible to use the existing multipliers and / or adders for different multiplications. It is therefore not necessary to provide a separate multiplier or adder for each of the multiplications and / or additions to be carried out for filtering; the existing multipliers or adders can be used (if the filtering is carried out by a sequence of worksteps comprising several work steps) for several of the multiplications or additions to be carried out during the filtering.

As a result, a digital filter designed as claimed manages with considerably fewer multipliers and adders than is the case with digital filters constructed in a conventional manner. Digital filters can thus be implemented with minimal effort.

Advantageous developments of the invention can be found in the subclaims, the following description, and the figures.

The invention is explained in more detail below using an exemplary embodiment with reference to the figures. Show it

1 shows the digital filter described in more detail below, and

FIG. 2 shows a digital filter implemented in a conventional manner. The digital filter described below is a fourth degree Butterworth IIR filter. However, it should already be pointed out at this point that the special features of the digital filter described below also apply to any other digital filter, ie also to filters that are not Butterworth-IIR filters and / or are not fourth-degree filters Can come into play.

The digital filter described is distinguished, inter alia, by the fact that at least one of the existing multipliers can be supplied with data representing different variables or constants during successive multiplication processes and / or that the results of successive multiplication processes are processed differently and / or that At least one of the existing adders can be supplied with data representing different variables or constants during successive addition processes and / or the results of successive addition processes can be processed differently.

A digital filter that has these properties is shown in FIG.

The filter shown in FIG. 1 comprises memory devices S101 to S109, adders A101 to A103, multipliers M101 and M102, and multiplexers MUX101 to MUX107.

The input and output signals of the filter components mentioned comprise certain numbers of bits, which are specified below. However, there is no restriction to the numbers mentioned.

The adder A101 adds the 22-bit output signal of the multiplexer MUX103 and the 23-bit one

Output signal of the multiplexer M104 and outputs a result of 23 bits add_out; the adder A102 adds that Output signal of the multiplier M102 and the 36-bit value stored in the memory device S107 and outputs a 36-bit result mac_out; and the adder A103 adds the 1-bit output of the multiplexer M106 and the 27-bit output of the multiplexer M107 and outputs a 27-bit result.

The multiplier M101 multiplies the 21-bit output signal of the multiplexer MUX101 by the constant -2 and outputs a 22-bit result. This multiplication can be carried out by a shift operation and a subsequent negation of the result, so that the multiplier M101 does not really have to be implemented by a multiplier. The multiplier M102 multiplies the 23-bit output signal of the multiplexer M105 and the 12-bit output signal of the memory device S105.

The multiplexer MUX101 receives as input signals the data, each comprising 21 bits, stored in the memory devices S101 and S103 and outputs one of these signals to the multiplier M101 and to the multiplexers MUX103 and MUX105; the multiplexer MUX102 receives as input signals the data, each comprising 21 bits, stored in the memory devices S102 and S104 and outputs one of these signals to the multiplexers MUX104 and MUX105; the multiplexer MUX103 receives as input signals the 21-bit output signal of the multiplexer MUX101 and the 22-bit output signal of the multiplier M101 and outputs one of these signals to the adder A101; the multiplexer MUX104 receives as input signals the 21-bit output signal of the multiplexer MUX102 and the 23-bit data stored in the memory device S106, and outputs one of these signals to the adder A101; the multiplexer MUX105 receives as input signals the 23-bit output signal add_out of the adder A101, the 21st Output bits of the multiplexers MUX101 and MUX102 comprising bits, and the 16-bit input signal of the arrangement, and outputs a signal to the multiplier M102; the multiplexer MUX106 receives as input signals the sign bit of the output signal of the adder A102 and the constant value "1", and outputs one of these signals to the adder A103; the multiplexer MUX107 receives as input signals bits 9 to 35 of the output signal of adder A102, which comprises a total of 36 bits, and bits 10 to 35 of the value comprising 36 bits stored in memory device S107, and outputs one of these signals to adder AI03.

An intermediate result comprising 21 bits, hereinafter referred to as xll, is stored in the storage device S101; an intermediate result comprising 21 bits, hereinafter referred to as xl2, is stored in the memory device S102; An intermediate result comprising 21 bits, hereinafter referred to as x21, is stored in the memory device S103; an intermediate result comprising 21 bits, hereinafter referred to as x22, is stored in the memory device S104; The constants cO, -al2, -all, cl, -a22, -a21, and c2 of the transfer function implemented by the arrangement are stored in the memory device S105. an intermediate result comprising 23 bits, hereinafter referred to as tmp (the output signal add_out of the adder A101) is stored in the memory device S106; A 36-bit intermediate result (hereinafter referred to as acc) (the output signal mac_out of the adder A102) is stored in the memory device S107; an intermediate result comprising 27 bits, hereinafter referred to as satl (the output signal of the adder A103) is stored in the storage device S108; and in the memory device S109 a 26-bit intermediate result, hereinafter referred to as sat3 (the most significant 26 bits of the total 27-bit output signal of the adder A103) is stored. The storage device S108 is connected to the storage devices S101 and S103 and can transfer the data stored therein. In addition, the storage devices S1OL and S102 and the storage devices S103 and S104 are also connected to one another; as a result, the storage device S101 can transmit data to the storage device S102, and the storage device S103 can transmit data to the storage device S104.

The signal input to be filtered comprises 16 bits and is input via an input connection I, which, as already mentioned above, is connected to one of the input connections of the multiplexer M105; the result output of the filtering also comprises 16 bits and is output via an output connection 0, which is also the output connection of the memory device S109.

In the example under consideration, the output signals are generated in 8 successive steps (per output signal), the individual steps each taking one clock period and comprising the following operations:

Step 1: write the storage device S107 (acc) with the value 0;

- Carrying out the calculation input * cO + acc by the multiplier M102 and the adder A102 and outputting the result mac_out from the adder AI02;

Step 2: - write mac_out into the storage device S107 (acc);

- Carrying out the calculation (xl2 * (-al2)) + acc by the multiplier M102 and the adder AI02 and output of the result mac_out from the adder AI02;

Step 3: - write mac_out into the storage device S107 (acc);

- Carrying out the calculation

(xll * (-all)) + acc by the multiplier M102 and ^" the adder A102 and writing the result mac_out into the storage device S108 (satl);

- Execution of the calculation xl2 - (2 * xll) by the multiplier M101 and the adder AI01 and output of the result add_out from the

Adder A101;

Step 4: write the storage device S107 (acc) with the value 0; - Writing the storage device S102 (xl2) with the content of the storage device SlOl (xll);

- Describing the storage device SlOl (xll) with the content of the storage device S108 (satl);

- writing add_out into the memory device S106 (tmp);

- Carrying out the calculation

((tmp + xll) * cl) + acc by the adder A101, the multiplier M102 and the adder AI02 and outputting the result mac_out from the adder A102;

Step 5: - write mac_out into the storage device S107 (acc);

- Carrying out the calculation

(x22 * (-a22)) + acc by the multiplier M102 and the adder AI02 and output of the result mac_out from the adder AI02;

Step 6: write mac_out into the storage device S107 (acc); Carrying out the calculation

(x21 * (-a21)) + acc. by the multiplier Ml02 and the adder A102 and writing the result mac_out into the storage device S108 (satl); Performing the calculation x22 - (2 * x21) by the multiplier M101 and the adder AlOl and outputting the result add_out from the adder AlOl;

Step 7: write the storage device S107 (acc) with the value 0; - writing to the storage device S104 (x22) with the content of the storage device S103 (x21);

- Describing the storage device S103 (x21) with the content of the storage device S108 (satl);

- writing add_out into the memory device S106 (tmp);

- Carrying out the calculation

((tmp + x21) * c2) + acc by the adder AlOl, the multiplier

M102, and adder A102 and output of the result mac_out from adder A102;

Step 8: writing mac_out into the storage device S107 (acc); - Describe the storage device S109 (sat3) with the content of the storage device S107

(acc);

- Output of the content of the memory device S109 (sat3) to the output terminal 0 of the filter arrangement.

The control of the arrangement of Figure 1 such that it repeats (for each input ^ ^'signal which is supplied to it, and for each output signal, which has to generate them) executes the above-described steps performed by a in the figure 1 Control unit not shown. To control the arrangement, this control unit only has to ensure

the multiplexers are controlled in such a way that the filter arrangement components are supplied with the data required in each case at the correct times and in the correct sequence,

- the adders and the multipliers are started at the right times, and

- Describe and read out the memory devices as specified in the description of steps 1 to 8.

A filter arrangement constructed and controlled as described provides exactly the same results as a filter arrangement realized in a conventional manner (for example in the manner of FIG. 2). As can be seen easily, however, the arrangement described has a considerably simpler structure: it requires only one multiplier and three adders; in contrast, a total of nine multipliers and eight adders must be provided in the conventionally implemented arrangement according to FIG. 2.

The drastic reduction in multipliers is particularly advantageous. Because multipliers are As is well known, it is particularly complex to implement and also requires a particularly large amount of space.

On the other hand, the additional elements that must be provided in the arrangement described in order to use the existing adders and multipliers more efficiently through multiple use thereof, that is to say the multiplexers and the control unit for controlling the arrangement shown in FIG. 1 can be implemented without any significant effort ,

The control processes to be carried out by the control unit are extremely simple. Therefore, and because the operations to be carried out in steps 1 to 8 are not tied to conditions and do not have to be modified for other reasons, the control unit can be implemented by a simply constructed logic. The entire filter arrangement can thus be implemented using a small and easily assembled state machine.

In order to achieve a particularly simple construction of the filter arrangement, it also proves to be advantageous if, in the transfer function which the filter arrangement in question has to have, of the constants occurring therein, which in the example under consideration a .., b ..., and c. are, certain constants are brought to easily manageable values (preferably ± 1 or ± 2 ") by appropriately determining the respective other constants, as was practiced in the present case for the constants bio, n and bι _2. As a result, the multipliers, which would normally have to be provided to take into account the relevant constants, can be omitted or can be replaced by simple other devices (for example a shift register).

Despite the advantages mentioned, the filter arrangement described does not work more slowly, but rather even faster than conventional filters, regardless of whether the conventional filters are implemented in terms of hardware or software are; The filtering to be carried out is also carried out in conventional filter devices in more or less many successive steps.

A digital filter constructed as described can thus be implemented with considerably less effort without accepting disadvantages than a digital filter constructed in a conventional manner.

LIST OF REFERENCE NUMBERS

Ax adder acc intermediate result add_out output signal of AlOl ax constants ex constants

Dx delay element

I input connection of the filter arrangement max_out output signal from A102

Mx multiplier

MUXx multiplexer

0 Output connection of the filter arrangement

Qx quantization devices Sx storage devices satl intermediate result sat3 intermediate result tmp intermediate result xx intermediate result

Claims

claims

1. A digital filter with one or more multipliers and / or adders, characterized in that at least one of the existing multipliers (Mx) can be supplied with data representing different variables or constants during successive multiplication processes and / or that the results of successive multiplication processes differ are further processed and / or that at least one of the existing adders (Ax) can be supplied with data representing different variables or constants during successive addition processes and / or that the results of successive addition processes are processed differently.

2. Digital filter according to claim 1, so that the data representing different variables or constants is fed to the input connections of the multipliers (Mx) and / or adders (Ax) using multiplexers (MUXx).

3. Digital filter according to claim 1 or 2, characterized in that the supply of the data representing different variables or constants to the input connections of the multipliers (Mx) and / or adders (Ax) is carried out in that a memory device (S105) is used as the data source , in which data representing several variables or constants can be stored, and which is constructed and / or controlled in such a way that successively output data are different data representing variables or constants.

4. Digital filter according to claim 3, characterized in that the storage device (S105) is formed by a storage device which automatically outputs the stored data in a predetermined order.

5. Digital filter according to one of the preceding claims, characterized in that the digital filter is designed to carry out a filtering, in which a sequence of worksteps comprising a plurality of worksteps is repeatedly carried out, and in that the multipliers (Mx) and adders (Ax) , to which data representing different variables or constants can be fed during successive multiplication or addition processes, can carry out multiplication or addition in several or all steps.

6. Digital filter according to one of the preceding claims, d a d u r c h g e k e n n z e i c h n e t that the digital filter is formed by a state machine.