WO2001075895A3 - Elimination of precharge operation in synchronous flash memory - Google Patents
Elimination of precharge operation in synchronous flash memory Download PDFInfo
- Publication number
- WO2001075895A3 WO2001075895A3 PCT/US2001/010038 US0110038W WO0175895A3 WO 2001075895 A3 WO2001075895 A3 WO 2001075895A3 US 0110038 W US0110038 W US 0110038W WO 0175895 A3 WO0175895 A3 WO 0175895A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- flash memory
- elimination
- synchronous flash
- precharge operation
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/229—Timing of a write operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001573487A JP3773846B2 (en) | 2000-03-30 | 2001-03-30 | Synchronous flash memory that eliminates the need for precharge processing |
AU2001247871A AU2001247871A1 (en) | 2000-03-30 | 2001-03-30 | Elimination of precharge operation in synchronous flash memory |
DE1269472T DE1269472T1 (en) | 2000-03-30 | 2001-03-30 | SAVING THE PRECHARGE STEP IN A SYNCHRONOUS FLASH MEMORY |
EP01920861A EP1269472A2 (en) | 2000-03-30 | 2001-03-30 | Elimination of precharge operation in synchronous flash memory |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19350600P | 2000-03-30 | 2000-03-30 | |
US60/193,506 | 2000-03-30 | ||
US09/568,935 | 2000-05-11 | ||
US09/568,935 US6314049B1 (en) | 2000-03-30 | 2000-05-11 | Elimination of precharge operation in synchronous flash memory |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001075895A2 WO2001075895A2 (en) | 2001-10-11 |
WO2001075895A3 true WO2001075895A3 (en) | 2002-03-21 |
Family
ID=26889062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/010038 WO2001075895A2 (en) | 2000-03-30 | 2001-03-30 | Elimination of precharge operation in synchronous flash memory |
Country Status (7)
Country | Link |
---|---|
US (2) | US6314049B1 (en) |
EP (1) | EP1269472A2 (en) |
JP (1) | JP3773846B2 (en) |
KR (1) | KR100438635B1 (en) |
AU (1) | AU2001247871A1 (en) |
DE (1) | DE1269472T1 (en) |
WO (1) | WO2001075895A2 (en) |
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US20020132617A1 (en) * | 2001-01-05 | 2002-09-19 | Nuss Randall S. | Method and apparatus for providing virtual frequency identifiers for internet radio |
JP4569915B2 (en) * | 2000-08-11 | 2010-10-27 | エルピーダメモリ株式会社 | Semiconductor memory device |
US6580659B1 (en) * | 2000-08-25 | 2003-06-17 | Micron Technology, Inc. | Burst read addressing in a non-volatile memory device |
US6865702B2 (en) * | 2001-04-09 | 2005-03-08 | Micron Technology, Inc. | Synchronous flash memory with test code input |
JP4109841B2 (en) * | 2001-06-19 | 2008-07-02 | 株式会社東芝 | Semiconductor integrated circuit device and semiconductor equipment system |
US6560161B1 (en) | 2001-08-30 | 2003-05-06 | Micron Technology, Inc. | Synchronous flash memory command sequence |
US6870770B2 (en) | 2001-12-12 | 2005-03-22 | Micron Technology, Inc. | Method and architecture to calibrate read operations in synchronous flash memory |
US6671212B2 (en) * | 2002-02-08 | 2003-12-30 | Ati Technologies Inc. | Method and apparatus for data inversion in memory device |
US6721227B2 (en) * | 2002-02-11 | 2004-04-13 | Micron Technology, Inc. | User selectable banks for DRAM |
US7035753B2 (en) * | 2002-03-20 | 2006-04-25 | Infineon Technologies Ag | Method and apparatus for placing an integrated circuit into a default mode of operation |
US7251711B2 (en) | 2002-05-28 | 2007-07-31 | Micron Technology, Inc. | Apparatus and methods having a command sequence |
US6751139B2 (en) | 2002-05-29 | 2004-06-15 | Micron Technology, Inc. | Integrated circuit reset circuitry |
US7007133B2 (en) * | 2002-05-29 | 2006-02-28 | Micron Technology, Inc. | Synchronous memory open page register |
KR100464034B1 (en) * | 2002-07-19 | 2005-01-03 | 엘지전자 주식회사 | Method for clock synchronizing |
JP4111789B2 (en) | 2002-09-13 | 2008-07-02 | 富士通株式会社 | Semiconductor memory device control method and semiconductor memory device |
JP2004185686A (en) | 2002-11-29 | 2004-07-02 | Toshiba Corp | Semiconductor storage device |
US6870774B2 (en) * | 2002-12-10 | 2005-03-22 | Micron, Technology, Inc. | Flash memory architecture for optimizing performance of memory having multi-level memory cells |
JP4472701B2 (en) * | 2004-07-29 | 2010-06-02 | スパンション エルエルシー | Nonvolatile storage device information setting method, nonvolatile storage device, and system equipped with the same |
US20060095622A1 (en) * | 2004-10-28 | 2006-05-04 | Spansion, Llc | System and method for improved memory performance in a mobile device |
US7336558B2 (en) * | 2004-11-02 | 2008-02-26 | Samsung Electronics Co., Ltd. | Semiconductor memory device with reduced number of pads |
US20060143330A1 (en) * | 2004-12-23 | 2006-06-29 | Oliver Kiehl | Method for data transmit burst length control |
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JPWO2007116487A1 (en) * | 2006-03-31 | 2009-08-20 | 富士通株式会社 | MEMORY DEVICE, ERROR CORRECTION SUPPORT METHOD, ITS SUPPORT PROGRAM, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC DEVICE |
EP2003567B1 (en) * | 2006-03-31 | 2012-02-15 | Fujitsu Ltd. | Memory apparatus, its control method, its control program, memory card, circuit board, and electronic device |
JPWO2007116486A1 (en) * | 2006-03-31 | 2009-08-20 | 富士通株式会社 | MEMORY DEVICE, ITS CONTROL METHOD, CONTROL PROGRAM, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC DEVICE |
US7849302B2 (en) | 2006-04-10 | 2010-12-07 | Apple Inc. | Direct boot arrangement using a NAND flash memory |
US7292487B1 (en) * | 2006-05-10 | 2007-11-06 | Micron Technology, Inc. | Independent polling for multi-page programming |
JP5209619B2 (en) * | 2006-07-07 | 2013-06-12 | エス. アクア セミコンダクター, エルエルシー | Memory with front-end precharge |
KR101364443B1 (en) * | 2007-01-31 | 2014-02-17 | 삼성전자주식회사 | Memory system, memory controller and memory for the same, and method of constructing signal of the same |
US7729191B2 (en) * | 2007-09-06 | 2010-06-01 | Micron Technology, Inc. | Memory device command decoding system and memory device and processor-based system using same |
JP2012203919A (en) | 2011-03-23 | 2012-10-22 | Toshiba Corp | Semiconductor memory device and control method therefor |
KR20130032505A (en) * | 2011-09-23 | 2013-04-02 | 에스케이하이닉스 주식회사 | Semiconductor system |
US9740485B2 (en) | 2012-10-26 | 2017-08-22 | Micron Technology, Inc. | Apparatuses and methods for memory operations having variable latencies |
US9754648B2 (en) | 2012-10-26 | 2017-09-05 | Micron Technology, Inc. | Apparatuses and methods for memory operations having variable latencies |
US9734097B2 (en) * | 2013-03-15 | 2017-08-15 | Micron Technology, Inc. | Apparatuses and methods for variable latency memory operations |
US9727493B2 (en) | 2013-08-14 | 2017-08-08 | Micron Technology, Inc. | Apparatuses and methods for providing data to a configurable storage area |
US10365835B2 (en) | 2014-05-28 | 2019-07-30 | Micron Technology, Inc. | Apparatuses and methods for performing write count threshold wear leveling operations |
KR20180049502A (en) | 2016-11-03 | 2018-05-11 | 삼성전자주식회사 | Semiconductor memory devices and methods of operating semiconductor memory devices |
US11581053B2 (en) | 2020-08-06 | 2023-02-14 | Micron Technology, Inc. | Memory device test mode access |
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US5745428A (en) * | 1995-07-14 | 1998-04-28 | Cirrus Logic, Inc. | Pipelined address memories, and systems and methods using the same |
US6031770A (en) * | 1997-08-22 | 2000-02-29 | Micron Technology, Inc. | Synchronous memory with programmable read latency |
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-
2000
- 2000-05-11 US US09/568,935 patent/US6314049B1/en not_active Expired - Lifetime
-
2001
- 2001-03-30 EP EP01920861A patent/EP1269472A2/en not_active Ceased
- 2001-03-30 AU AU2001247871A patent/AU2001247871A1/en not_active Abandoned
- 2001-03-30 WO PCT/US2001/010038 patent/WO2001075895A2/en active IP Right Grant
- 2001-03-30 DE DE1269472T patent/DE1269472T1/en active Pending
- 2001-03-30 JP JP2001573487A patent/JP3773846B2/en not_active Expired - Fee Related
- 2001-03-30 KR KR10-2002-7013094A patent/KR100438635B1/en not_active IP Right Cessation
- 2001-07-31 US US09/919,327 patent/US6496444B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US5745428A (en) * | 1995-07-14 | 1998-04-28 | Cirrus Logic, Inc. | Pipelined address memories, and systems and methods using the same |
US6031770A (en) * | 1997-08-22 | 2000-02-29 | Micron Technology, Inc. | Synchronous memory with programmable read latency |
Non-Patent Citations (1)
Title |
---|
See also references of EP1269472A2 * |
Also Published As
Publication number | Publication date |
---|---|
DE1269472T1 (en) | 2003-08-14 |
KR100438635B1 (en) | 2004-07-02 |
KR20020087113A (en) | 2002-11-21 |
EP1269472A2 (en) | 2003-01-02 |
US6314049B1 (en) | 2001-11-06 |
AU2001247871A1 (en) | 2001-10-15 |
WO2001075895A2 (en) | 2001-10-11 |
JP2003529882A (en) | 2003-10-07 |
US6496444B2 (en) | 2002-12-17 |
US20020006074A1 (en) | 2002-01-17 |
JP3773846B2 (en) | 2006-05-10 |
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