WO2002003320A1 - Electronically manipulated smartcard generating user comprehendible output - Google Patents

Electronically manipulated smartcard generating user comprehendible output Download PDF

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Publication number
WO2002003320A1
WO2002003320A1 PCT/US2001/017043 US0117043W WO0203320A1 WO 2002003320 A1 WO2002003320 A1 WO 2002003320A1 US 0117043 W US0117043 W US 0117043W WO 0203320 A1 WO0203320 A1 WO 0203320A1
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WIPO (PCT)
Prior art keywords
layer
smartcard
monocrystalline
compound semiconductor
substrate
Prior art date
Application number
PCT/US2001/017043
Other languages
French (fr)
Inventor
James A. Coffing
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Motorola, Inc.
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Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Priority to AU2001274971A priority Critical patent/AU2001274971A1/en
Publication of WO2002003320A1 publication Critical patent/WO2002003320A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • RF radio frequency
  • FIGs. 1, 2, 3, 9, 10 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention.
  • FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of illustrative semiconductor material manufactured in accordance with what is shown herein.
  • TEM Transmission Electron Micrograph
  • FIG. 6 is an x-ray diffraction taken on an illustrative semiconductor structure manufactured in accordance with what is shown herein.
  • FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer.
  • FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer.
  • FIGs. 11-15 include illustrations of cross-sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein.
  • FIGs. 16-22 include illustrations of cross-sectional views of a portion of another integrated circuit that includes a semiconductor laser and a MOS transistor in accordance with what is shown herein.
  • FIG. 23 illustrates one way that a device structure 50 can be incorporated in a smartcard according to an aspect of the present invention.
  • FIG. 24 shows an electronic chip reader that may be used to communicate with a smartcard according to an aspect of the invention.
  • FIG. 25 depicts a smartcard of the present invention with a display on which text, graphics and or pictorial data may be provided.
  • FIG. 26 shows a smartcard that includes a light emitting diode according to an aspect of the invention.
  • FIG. 27 illustrates a smartcard that is capable of generating audible output, according to an aspect of the invention.
  • FIG. 28 depicts a smartcard that is capable of generating vibration output, according to an aspect of the invention.
  • FIG. 29 shows a smartcard that is capable of communication with a portable device, such as another smartcard, according to an aspect of the invention.
  • FIG. 30 illustrates a smartcard that includes data communication activators and associated light emitting diodes.
  • the present invention involves semiconductor structures of particular types.
  • these semiconductor structures are sometimes referred to as "composite semiconductor structures" or “composite integrated circuits” because they include two (or more) significantly different types of semiconductor devices in one integrated structure or circuit.
  • one of these two types of devices may be silicon-based devices such as CMOS devices, and the other of these two types of devices may be compound semiconductor devices such GaAs devices.
  • Illustrative composite semiconductor structures and methods for making such structures are disclosed in Ramdani et al. U.S. patent application No. 09/502,023, filed February 10, 2000, which is hereby incorporated by reference herein in its entirety. Certain material from that reference is substantially repeated below to ensure that there is support herein for references to composite semiconductor structures and composite integrated circuits.
  • Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material.
  • monocrystalline shall have the meaning commonly used within the semiconductor industry.
  • the term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry.
  • structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24.
  • Structure 20 may also include a template layer 30 between accommodating buffer layer 24 and compound semiconductor layer 26.
  • template layer 30 helps to initiate the growth of compound semiconductor layer 26 on accommodating buffer layer 24.
  • Amorphous intermediate layer 28 helps to relieve the strain in accommodating buffer layer 24 and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer 24.
  • Substrate 22 in accordance with one embodiment, is a monocrystalline semiconductor wafer, preferably of large diameter.
  • the wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of
  • Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like.
  • substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate 22.
  • amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer 24 by the oxidation of substrate 22 during the growth of layer 24.
  • Amorphous intermediate layer 28 serves to relieve strain that might otherwise occur in monocrystalline accommodating buffer layer 24 as a result of differences in the lattice constants of substrate 22 and buffer layer 24.
  • lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by amorphous intermediate layer 28, the strain may cause defects in the crystalline structure of accommodating buffer layer 24. Defects in the crystalline structure of accommodating buffer layer 24, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26.
  • Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with underlying substrate 22 and with overlying compound semiconductor material 26.
  • the material could be an oxide or nitride having a lattice structure matched to substrate 22 and to the subsequently applied semiconductor material 26.
  • Materials that are suitable for accommodating buffer layer 24 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide.
  • nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for accommodating buffer layer 24.
  • Most of these materials are insulators, although strontium ruthenate, for example, is a conductor.
  • these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
  • Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide.
  • the thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 2 .
  • layer 28 has a thickness in the range of approximately 0.5-5 nm.
  • the compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds.
  • FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment. Structure 40 is similar to the previously described semiconductor structure 20 except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26.
  • additional buffer layer 32 is positioned between the template layer 30 and the overlying layer 26 of compound semiconductor material.
  • Additional buffer layer 32 formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of accommodating buffer layer 24 cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer 26.
  • FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention.
  • Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38.
  • amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above.
  • Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer.
  • the accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer.
  • Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate.
  • layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing—e.g., compound semiconductor layer 26 formation.
  • semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32.
  • layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials.
  • semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
  • semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38.
  • compound semiconductor material e.g., a material discussed above in connection with compound semiconductor layer 26
  • a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26.
  • the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
  • the layer formed on substrate 22, whether it includes only accommodating buffer layer 24, accommodating buffer layer 24 with amorphous intermediate or interface layer 28, or an amorphous layer such as layer 36 formed by annealing layers 24 and 28 as described above in connection with FIG. 3, may be referred to generically as an "accommodating layer.”
  • monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
  • Silicon substrate 22 can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm.
  • accommodating buffer layer 24 is a monocrystalline layer of Sr z Ba ⁇ - z Ti0 3 where z ranges from 0 to 1 and amorphous intermediate layer 28 is a layer of silicon oxide (SiO x ) formed at the interface between silicon substrate 22 and accommodating buffer layer 24. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer
  • Accommodating buffer layer 24 can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer 24 thick enough to isolate compound semiconductor layer 26 from substrate 22 to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed.
  • the amorphous intermediate layer 28 of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
  • compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) haying a thickness of about 1 nm to about 100 micrometers ( ⁇ m) and preferably a thickness of about 0.5 ⁇ m to 10 ⁇ m. The thickness generally depends on the application for which the layer is being prepared.
  • a template layer 30 is formed by capping the oxide layer. Template layer 30 is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers 30 of Ti-As or Sr- Ga-0 have been shown to successfully grow GaAs layers 26.
  • monocrystalline substrate 22 is a silicon substrate as described above.
  • Accommodating buffer layer 24 is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer 28 of silicon oxide formed at the interface between silicon substrate 22 and accommodating buffer layer 24.
  • Accommodating buffer layer 24 can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr0 3 , BaZr0 3 , SrHf0 3 , BaSn0 3 or BaHf0 3 .
  • a monocrystalline oxide layer of BaZr0 can grow at a temperature of about 700 degrees C.
  • the lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate 22 silicon lattice structure.
  • An accommodating buffer layer 24 formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials 26 in the indium phosphide (InP) system.
  • the compound semiconductor material 26 can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 ⁇ m.
  • InP indium phosphide
  • InGaAs indium gallium arsenide
  • AlInAs aluminum indium arsenide
  • AlGalnAsP aluminum gallium indium arsenic phosphide
  • a suitable template 30 for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P) , strontium-oxygen- arsenic (Sr-O-As) , strontium-oxygen-phosphorus (Sr-O-P) , barium- oxygen-arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen-phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials.
  • a barium zirconate accommodating buffer layer 24 the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template 30.
  • a monocrystalline layer 26 of the compound semiconductor material from the indium phosphide system is then grown on template layer 30.
  • the resulting lattice structure of the compound semiconductor material 26 exhibits a 45 degree rotation with respect to the accommodating buffer layer 24 lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
  • a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate 22.
  • the substrate 22 is preferably a silicon wafer as described above.
  • a suitable accommodating buffer layer 24 material is Sr x Ba ! _ x Ti0 3 , where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm.
  • the II-VI compound semiconductor material 26 can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) .
  • a suitable template 30 for this material system includes 1-10 monolayers of zinc-oxygen
  • a template 30 can be, for example, 1-10 monolayers of strontium- sulfur (Sr-S) followed by the ZnSeS.
  • Example 4 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2.
  • Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1.
  • an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material.
  • Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP) , an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice.
  • buffer layer 32 includes a GaAs x P !
  • buffer layer 32 includes an In y Ga ! -y P superlattice, wherein the value of y ranges from 0 to 1.
  • the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material.
  • the compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner.
  • the superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm.
  • the template for this structure can be the same of that described in example 1.
  • buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm.
  • a template layer of either germanium-strontium (Ge-Sr) or germanium- titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer.
  • the formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium.
  • the monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
  • buffer layer 32 is inserted between accommodating buffer layer 24 and overlying monocrystalline compound semiconductor material layer 26.
  • Buffer layer 32 a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) .
  • buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. Buffer layer 32 preferably has a thickness of about 10-30 nm.
  • Varying the composition of buffer layer 32 from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material 24 and the overlying layer 26 of monocrystalline compound semiconductor material.
  • Such a buffer layer 32 is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
  • Substrate material 22, template layer 30, and monocrystalling compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
  • Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) .
  • amorphous layer 36 may include a combination of SiOx and SrzBal-z Ti03 (where z ranges from 0 to 1) ,which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
  • amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
  • Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24.
  • layer 38 includes the same materials as those comprising layer 26.
  • layer 38 also includes GaAs.
  • layer 38 may include materials different from those used to form layer 26.
  • layer 38 is about 1 monolayer to about 100 nm thick.
  • substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate.
  • the crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation.
  • accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation.
  • the lattice constants of accommodating buffer layer 24 and monocrystalline substrate 22 must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved.
  • the terms "substantially equal” and “substantially matched” mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
  • FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal .
  • Curve 42 illustrates the boundary of high crystalline quality material.
  • the area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved.
  • substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate.
  • Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material 24 by 45° with respect to the crystal orientation of the silicon substrate wafer 22.
  • a silicon oxide layer in this example serves to reduce strain in the titanate monocrystalline layer 24 that might result from any mismatch in the lattice constants of the host silicon wafer 22 and the grown titanate layer 24.
  • layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation.
  • the lattice constant of layer 26 differs from the lattice constant of substrate 22.
  • accommodating buffer layer 24 must be of high crystalline quality.
  • substantial matching between the crystal lattice constant of the host crystal, in this case, monocrystalline accommodating buffer layer 24, and grown crystal 26 is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of grown crystal 26 with respect to the orientation of host crystal 24.
  • grown crystal 26 is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and accommodating buffer layer 24 is monocrystalline Sr x Ba ⁇ . -x Ti0 3 , substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of grown layer 26 is rotated by 45° with respect to the orientation of the host monocrystalline oxide 24.
  • host material 24 is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and compound semiconductor layer 26 is indium phosphide or gallium indium arsenide or aluminum indium arsenide
  • substantial matching of crystal lattice constants can be achieved by rotating the orientation of grown crystal layer 26 by 45° with respect to host oxide crystal 24.
  • a crystalline semiconductor buffer layer 32 between host oxide 24 and grown compound semiconductor layer 26 can be used to reduce strain in grown monocrystalline compound semiconductor layer 26 that might result from small differences in lattice constants. Better crystalline quality in grown monocrystalline compound semiconductor layer 26 can thereby be achieved.
  • the following example illustrates a process, in accordance with one embodiment, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3.
  • the process starts by providing a monocrystalline semiconductor substrate 22 comprising silicon or germanium.
  • semiconductor substrate 22 is a silicon wafer having a (100) orientation.
  • Substrate 22 is preferably oriented on axis or, at most, about 0.5° off' axis.
  • At least a portion of semiconductor substrate 22 has a bare surface, although other portions of the substrate, as described below, may encompass other structures.
  • the term "bare" in this context means that the surface in the portion of substrate 22 has been cleaned to remove any oxides, contaminants, or other foreign material.
  • bare silicon is highly reactive and readily forms a native oxide.
  • the term "bare" is intended to encompass such a native oxide.
  • a thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process.
  • the native oxide layer In order to epitaxially grow a monocrystalline oxide layer 24 overlying monocrystalline substrate 22, the native oxide layer must first be removed to expose the crystalline structure of underlying substrate 22. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention.
  • MBE molecular beam epitaxy
  • the native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus.
  • the substrate 22 is then heated to a temperature of about 750°C to cause the strontium to react with the native silicon oxide layer.
  • the strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface.
  • the resultant surface which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon.
  • the ordered 2x1 structure forms a template for the ordered growth of an overlying layer 24 of a monocrystalline oxide.
  • the template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer 24.
  • the native silicon oxide can be converted and the surface of substrate 22 can be prepared for the growth of a monocrystalline oxide layer 24 by depositing an alkali earth metal oxide, such as strontium oxide or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate 22 surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer 24.
  • an alkali earth metal oxide such as strontium oxide or barium oxide
  • the substrate is cooled to a temperature in the range of about 200-800°C and a layer 24 of strontium titanate is grown on the template layer by molecular beam epitaxy.
  • the MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources.
  • the ratio of strontium and titanium is approximately 1:1.
  • the partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value.
  • the overpressure of oxygen causes the growth of an amorphous silicon oxide layer 28 at the interface between underlying substrate 22 and the growing strontium titanate layer 24.
  • the growth of silicon oxide layer 28 results from the diffusion of oxygen through the growing strontium titanate layer 24 to the interface where the oxygen reacts with silicon at the surface of underlying substrate 22.
  • the strontium titanate grows as an ordered monocrystal 24 with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of underlying substrate 22. Strain that otherwise might exist in strontium titanate layer 24 because of the small mismatch in lattice constant between silicon substrate 22 and the growing crystal 24 is relieved in amorphous silicon oxide intermediate layer 28.
  • the monocrystalline strontium titanate is capped by a template layer 30 that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material 26.
  • the MBE growth of strontium titanate monocrystalline layer 24 can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen.
  • arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As.
  • FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention.
  • Single crystal SrTi03 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch.
  • GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
  • FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24.
  • the peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated.
  • the structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer 32 deposition step.
  • Buffer layer 32 is formed overlying template layer 30 before the deposition of monocrystalline compound semiconductor layer 26. If buffer layer 32 is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template 30 described above.
  • buffer layer 32 is a layer of germanium
  • the process above is modified to cap strontium titanate monocrystalline layer 24 with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium.
  • the germanium buffer layer 32 can then be deposited directly on this template 30.
  • Structure 34 may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above.
  • the accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36.
  • Layer 26 is then subsequently grown over layer 38.
  • the anneal process may be carried out subsequent to growth of layer 26.
  • layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 1 to about 10 minutes.
  • suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention.
  • laser annealing or "conventional" thermal annealing processes in the proper environment
  • an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process.
  • the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
  • layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
  • FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3.
  • TEM Transmission Electron Micrograph
  • a single crystal SrTi03 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above.
  • GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
  • FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22.
  • the peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous .
  • the process described above illustrates a process for forming a semiconductor structure including a silicon substrate 22, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer 26 by the process of molecular beam epitaxy.
  • the process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like.
  • CVD chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • MEE migration enhanced epitaxy
  • ALE atomic layer epitaxy
  • PVD physical vapor deposition
  • CSSD chemical solution deposition
  • PLD pulsed laser deposition
  • monocrystalline accommodating buffer layers 24 such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown.
  • other III-V and II-VI monocrystalline compound semiconductor layers 26 can be deposited overlying monocrystalline oxide accommodating buffer layer 24.
  • Each of the variations of compound semiconductor materials 26 and monocrystalline oxide accommodating buffer layer 24 uses an appropriate template 30 for initiating the growth of the compound semiconductor layer.
  • accommodating buffer layer 24 is an alkaline earth metal zirconate
  • the oxide can be capped by a thin layer of zirconium.
  • the deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively.
  • monocrystalline oxide accommodating buffer layer 24 is an alkaline earth metal hafnate
  • the oxide layer can be capped by a thin layer of hafnium.
  • hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer 26, respectively.
  • strontium titanate 24 can be capped with a layer of strontium or strontium and oxygen
  • barium titanate 24 can be capped with a layer of barium or barium and oxygen.
  • Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template 30 for the deposition of a compound semiconductor material layer 26 comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
  • FIG. 9 illustrates schematically, in cross section, a device structure 50 in accordance with a further embodiment.
  • Device structure 50 includes a monocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer.
  • Monocrystalline semiconductor substrate 52 includes two regions, 53 and 54.
  • An electrical semiconductor component generally indicated by the dashed line 56 is formed, at least partially, in region 53.
  • Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit .
  • electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited.
  • the electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry.
  • a layer of insulating material 58 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 56.
  • Insulating material 58 and any other layers that may have been formed or deposited during the processing of semiconductor component 56 in region 53 are removed from the surface of region 54 to provide a bare silicon surface in that region.
  • bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface.
  • a layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 54 and is reacted with the oxidized surface to form a first template layer (not shown) .
  • a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer.
  • the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form monocrystalline barium titanate layer.
  • the partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer.
  • the oxygen diffusing through the barium titanate reacts with silicon at the surface of region 54 to form an amorphous layer of silicon oxide on second region 54 and at the interface between silicon substrate 52 and the monocrystalline oxide.
  • Layers 60 and 62 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • the step of depositing the monocrystalline oxide layer is terminated by depositing a second template layer 60, which can be 1-10 monolayers of titanium, barium, barium and oxygen, or titanium and oxygen.
  • a layer 66 of a monocrystalline compound semiconductor material is then deposited overlying second template layer 64 by a process of molecular beam epitaxy. The deposition of layer 66 is initiated by depositing a layer of arsenic onto template 64. This initial step is followed by depositing gallium and arsenic to form monocrystalline gallium arsenide 66.
  • strontium can be substituted for barium in the above example.
  • a semiconductor component is formed in compound semiconductor layer 66.
  • Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices .
  • Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT) , high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials.
  • HBT heterojunction bipolar transistor
  • a metallic conductor schematically indicated by the line 70 can be formed to electrically couple device 68 and device 56, thus implementing an integrated device that includes at least one component formed in silicon substrate 52 and one device formed in monocrystalline compound semiconductor material layer 66.
  • illustrative structure 50 has been described as a structure formed on a silicon substrate 52 and having a barium (or strontium) titanate layer 60 and a gallium arsenide layer 66 , similar devices can be fabricated using other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure.
  • FIG. 10 illustrates a semiconductor structure 72 in accordance with a further embodiment.
  • Structure 72 includes a monocrystalline semiconductor substrate 74 such as a monocrystalline silicon wafer that includes a region 75 and a region 76.
  • An electrical component schematically illustrated by the dashed line 78 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry.
  • a monocrystalline oxide layer 80 and an intermediate amorphous silicon oxide layer 82 are formed overlying region 76 of substrate 74.
  • a template layer 84 and subsequently a monocrystalline semiconductor layer 86 are formed overlying monocrystalline oxide layer 80.
  • an additional monocrystalline oxide layer 88 is formed overlying layer 86 by process steps similar to those used to form layer 80, and an additional monocrystalline semiconductor layer 90 is formed overlying monocrystalline oxide layer 88 by process steps similar to those used to form layer 86.
  • at least one of layers 86 and 90 are formed from a compound semiconductor material. Layers 80 and 82 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • a semiconductor component generally indicated by a dashed line 92 is formed at least partially in monocrystalline semiconductor layer 86.
  • semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, by monocrystalline oxide layer 88.
  • monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor.
  • monocrystalline semiconductor layer 86 is formed from a group III-V compound and semiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials.
  • an electrical interconnection schematically illustrated by the line 94 electrically interconnects component 78 and component 92. Structure 72 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials .
  • the illustrative composite semiconductor structure or integrated circuit 102 shown in FIGs. 6-10 includes a compound semiconductor portion 1022, a bipolar portion 1024, and a MOS portion 1026.
  • a p-type doped, monocrystalline silicon ' substrate 110 is provided having a compound semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026.
  • the monocrystalline silicon substrate 110 is doped to form an N + buried region 1102.
  • a lightly p-type doped epitaxial monocrystalline silicon layer 1104 is then formed over the buried region 1102 and the substrate 110.
  • a doping step is then performed to create a lightly n-type doped drift region 1117 above the N + buried region 1102.
  • the doping step converts the dopant type of the lightly p-type epitaxial layer within a section of the bipolar region 1024 to a lightly n-type monocrystalline silicon region.
  • a field isolation region 1106 is then formed between the bipolar portion 1024 and the MOS portion 1026.
  • a gate dielectric layer 1110 is formed over a portion of the epitaxial layer 1104 within MOS portion 1026, and the gate electrode 1112 is then formed over the gate dielectric layer 1110.
  • Sidewall spacers 1115 are formed along vertical sides of the gate electrode 1112 and gate dielectric layer 1110.
  • a p-type dopant is introduced into the drift region 1117 to form an active or intrinsic base region 1114.
  • An n-type, deep collector region 1108 is then formed within the bipolar portion 1024 to allow electrical connection to the buried region 1102.
  • Selective n-type doping is performed to form N + doped region s 1116 and the emitter region 1120.
  • N + doped r egions 1116 are formed within layer 1104 along adjacent sides of the gate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor.
  • the N + doped regions 1116 and emitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed.
  • a p-type doped region is formed to create the inactive or extrinsic base region 1118 which is a P + doped region (doping concentration of at least 1E19 atoms per cubic centimeter) .
  • processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers.
  • the formation of the device up to this point in the process is performed using conventional steps. As illustrated, a standard N- channel MOS transistor has been formed within the MOS region 1026, and a vertical NPN bipolar transistor has been formed within the bipolar portion 1024. As of this point, no circuitry has been formed within the compound semiconductor portion 1022.
  • All of the layers that have been formed during the processing of the bipolar and MOS portions of the integrated circuit are now removed from the surface of compound semiconductor portion 1022.
  • a bare silicon surface is thus provided for the subsequent processing of this portion, for example in the manner set forth above.
  • An accommodating buffer layer 124 is then formed over the substrate 110 as illustrated in FIG. 12.
  • the accommodating ' buffer layer will form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface in portion 1022.
  • the portion of layer 124 that forms over portions 1024 and 1026 may be polycrystalline or amorphous because it is formed over a material that is not monocrystalline, and therefore, does not nucleate monocrystalline growth.
  • the accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers. In one particular embodiment, the accommodating buffer layer is approximately 5-15 nm thick.
  • an amorphous intermediate layer 122 is formed along the uppermost silicon surfaces of the integrated circuit 102. This amorphous intermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm.
  • a template layer 126 is then formed and has a thickness in a range of approximately one to ten monolayers of a material .
  • the material includes titanium- arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGS. 1-5.
  • Layers 122 and 124 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • a monocrystalline compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 (or over the amorphous accommodating layer if the annealing process described above has been carried out) as shown in FIG. 13.
  • the portion of layer 132 that is grown over portions of layer 124 that are not monocrystalline may be polycrystalline or amorphous.
  • the monocrystalline compound semiconductor layer can be formed by a number of methods and typically includes a material such as gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compound semiconductor materials as previously mentioned.
  • the thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-500 nm.
  • each of the elements within the template layer are also present in the accommodating buffer layer 124, the monocrystalline compound semiconductor material 132, or both. Therefore, the delineation between the template layer 126 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between the accommodating buffer layer 124 and the monocrystalline compound semiconductor layer 132 is seen.
  • TEM transmission electron microscopy
  • sections of the compound semiconductor layer 132 and the accommodating buffer layer 124 are removed from portions overlying the bipolar portion 1024 and the MOS portion 1026 as shown in FIG. 14.
  • an insulating layer 142 is then formed over the substrate 110.
  • the insulating layer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5.
  • a transistor 144 is then formed within the monocrystalline compound semiconductor portion 1022.
  • a gate electrode 148 is then formed on the monocrystalline compound semiconductor layer 132.
  • Doped regions 146 are then formed within the monocrystalline compound semiconductor layer 132.
  • the transistor 144 is a metal-semiconductor field-effect transistor -(MESFET) . If the MESFET is an n-type MESFET, the doped regions 146 and monocrystalline compound semiconductor layer 132 are also n-type doped. If a p-type MESFET were to be formed, then the doped regions 146 and monocrystalline compound semiconductor layer 132 would have just the opposite doping type. The heavier doped (N + ) regions 146 all ow ohmic contacts to be made to the monocrystalline compound semiconductor layer 132. At this point in time, the active devices within the integrated circuit have been formed.
  • This particular embodiment includes an n-type
  • MESFET a vertical NPN bipolar transistor, and a planar n-channel MOS transistor.
  • transistors including P- channel MOS transistors, p-type vertical bipolar transistors, p- type MESFETs, and combinations of vertical and planar transistors, can be used.
  • other electrical components such as resistors, capacitors, diodes, and the like, may be formed in one or more of the portions 1022, 1024, and 1026.
  • An insulating layer 152 is formed over the substrate 110.
  • the insulating layer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 15.
  • a second insulating layer 154 is then formed over the first insulating layer 152. Portions of layers 154, 152, 142, 124, and 122 are removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 154 to provide the lateral connections between the contacts.
  • interconnect 1562 connects a source or drain region of the n-type MESFET within portion 1022 to the deep collector region 1108 of the NPN transistor within the bipolar portion 1024.
  • the emitter region 1120 of the NPN transistor is connected to one of the doped regions 1116 of the n-channel MOS transistor within the MOS portion 1026.
  • the other doped region 1116 is electrically connected to other portions of the integrated circuit that are not shown.
  • a passivation layer 156 is formed over the interconnects 1562, 1564, and 1566 and insulating layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within the integrated circuit 102 but. are not illustrated in the FIGs. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections .between the various components within the integrated circuit 102.
  • active devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within bipolar portion into the compound semiconductor portion 1022 or the MOS portion 1024. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit .
  • an integrated circuit can be formed such that it includes an optical laser in a compound semiconductor portion and an optical interconnect (waveguide) to a MOS transistor within a Group IV semiconductor region of the same integrated circuit.
  • FIGs. 16-22 include illustrations of one embodiment .
  • FIG. 16 includes an illustration of a cross-section view of a portion of an integrated circuit 160 that includes a monocrystalline silicon wafer 161.
  • An amorphous intermediate layer 162 and an accommodating buffer layer 164 similar to those previously described, have been formed over wafer 161.
  • Layers 162 and 164 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
  • the layers needed to form the optical laser will be formed first, followed by the layers needed for the MOS transistor.
  • the lower mirror layer 166 includes alternating layers of compound semiconductor materials.
  • the first, third, and fifth films within the optical laser may include a material such as gallium arsenide, and the second, fourth, and sixth films within the lower mirror layer 166 may include aluminum gallium arsenide or vice versa.
  • Layer 168 includes the active region that will be used for photon generation.
  • Upper mirror layer 170 is formed in a similar manner to the lower mirror layer 166 and includes alternating films of compound semiconductor materials.
  • the upper mirror layer 170 may be p-type doped compound semiconductor materials
  • the lower mirror layer 166 may be n- type doped compound semiconductor materials.
  • Another accommodating buffer layer 172 is formed over the upper mirror layer 170.
  • the accommodating buffer layers 164 and 172 may include different materials. However, their function is essentially the same in that each is used for making a transition between a compound semiconductor layer and a monocrystalline Group IV semiconductor layer.
  • Layer 172 may be subject to an annealing process as described above in connection with FIG. 3 to form an amorphous accommodating layer.
  • a monocrystalline Group IV semiconductor layer 174 is formed over the accommodating buffer layer 172.
  • the monocrystalline Group IV semiconductor layer 174 includes germanium, silicon germanium, silicon germanium carbide, or the like.
  • the MOS portion is processed to form electrical components within this upper monocrystalline Group IV semiconductor layer 174.
  • a field isolation region 171 is formed from a portion of layer 174.
  • a gate dielectric layer 173 is formed over the layer 174, and a gate electrode 175 is formed over the gate dielectric layer 173.
  • Doped regions 177 are source, drain, or source/drain regions for the transistor 181, as shown.
  • Sidewall spacers 179 are formed adjacent to the vertical sides of the gate electrode 175.
  • Other components can be made within at least a part of layer 174. These other components include other transistors (n-channel or p- channel) , capacitors, transistors, diodes, and the like.
  • a monocrystalline Group IV semiconductor layer is epitaxially grown over one of the doped regions 177.
  • An upper portion 184 is P+ doped, and a lower portion 182 remains substantially intrinsic (undoped) as illustrated in FIG. 17.
  • the layer can be formed using a selective epitaxial process .
  • an insulating layer (not shown) is formed over the transistor 181 and- the field isolation region 171.
  • the insulating layer is patterned to define an opening that exposes one of the doped regions 177.
  • the selective epitaxial layer is formed without dopants.
  • the entire selective epitaxial layer may be intrinsic, or a p-type dopant can be added near the end of the formation of the selective epitaxial layer.
  • a doping step may be formed by implantation or by furnace doping. Regardless how the P+ upper portion 184 is formed, the insulating layer is then removed to form the resulting structure shown in FIG. 17.
  • the next set of steps is performed to define the optical laser 180 as illustrated in FIG. 18.
  • the field isolation region 171 and the accommodating buffer layer 172 are removed over the compound semiconductor portion of the integrated circuit. Additional steps are performed to define the upper mirror layer 170 and active layer 168 of the optical laser 180.
  • the sides of the upper mirror layer 170 and active layer 168 are substantially coterminous .
  • Contacts 186 and 188 are formed for making electrical contact to the upper mirror layer 170 and the lower mirror layer 166, respectively, as shown in FIG. 18.
  • Contact 186 has an annular shape to allow light (photons) to pass out of the upper mirror layer 170 into a subsequently formed optical waveguide.
  • An insulating layer 190 is then formed and patterned to define optical openings extending to the contact layer 186 and one of the doped regions 177 as shown in FIG. 19.
  • the insulating material can be any number of different materials, including an oxide, nitride, oxynitride, low-k dielectric, or any combination thereof.
  • a higher refractive index material 202 is then formed within the openings to fill them and to deposit the layer over the insulating layer 190 as illustrated in FIG. 20.
  • “higher” is in relation to the material of the insulating layer 190 (i.e., material 202 has a higher refractive index compared to the insulating layer 190) .
  • a relatively thin lower refractive index film (not shown) could be formed before forming the higher refractive index material 202.
  • a hard mask layer 204 is then formed over the high refractive index layer 202. Portions of the hard mask layer 204, and high refractive index layer 202 are removed from portions overlying the opening and to areas closer to the sides of FIG. 15.
  • a deposition procedure (possibly a dep-etch process) is performed to effectively create sidewalls sections 212.
  • the sidewall sections 212 are made of the same material as material 202.
  • the hard mask layer 204 is then removed, and a low refractive index layer 214 (low relative to material 202 and layer 212) is formed over the higher refractive index material 212 and 202 and exposed portions of the insulating layer 190.
  • the dash lines in FIG. 21 illustrate the border between the high refractive index materials 202 and 212. This designation is used to identify that both are made of the same material but are formed at different times .
  • a passivation layer 220 is then formed over the optical laser 180 and MOSFET transistor 181.
  • interconnects can include other optical waveguides or may include metallic interconnects .
  • other types of lasers can be formed.
  • another type of laser can emit light (photons) horizontally instead of vertically. If light is emitted horizontally, the MOSFET transistor could be formed within the substrate 161, and the optical waveguide would be reconfigured, so that the laser is properly coupled (optically connected) to the transistor.
  • the optical waveguide can include at least a portion of the accommodating buffer layer. Other configurations are possible.
  • the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like
  • the Group IV semiconductor can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits.
  • a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer.
  • the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II- VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters.
  • a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material.
  • an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily, compared to the relatively smaller and more fragile, conventional compound semiconductor wafers.
  • the present invention includes a contactless smartcard 250 that is capable of generating output, in a format that can be comprehended by a user, in response to manipulation of the data that is stored on an embedded microchip.
  • the integrated circuits (ICs) that are provided in currently available smartcards are typically formed from silicon wafers. While ICs that are formed from silicon and other such monocrystalline semiconductors readily generate thermal energy, a significant amount of externally supplied power would have to be supplied to allow such devices to generate optical output. In fact, the amount of power that would have to be supplied to enable an IC formed from a monocrystalline substrate to generate optical output exceeds that which can be efficiently supplied through RF transmission to a smartcard. Thus, a battery, or other power source that would significantly increase the size of the smartcard, would have to be supplied in order to enable the card to generate optical output .
  • ICs that are formed from compound semiconductors, notably Group III-V compound semiconductors, can generate optical output without supplying external power.
  • compound semiconductors are not used in smartcards because it is very expensive to form ICs from compound semiconductor wafers.
  • a device structure 50 such as that described above with reference to FIG. 9, can be used to combine monocrystalline semiconductors and compound semiconductors in a single IC, and thereby provide inexpensive electrical components that generate optical output.
  • smartcard 250 incorporates the device structure 50 previously illustrated in FIG. 9.
  • smartcard 250 includes an electronic chip 240 with electronic circuitry 256, which is embedded in region 253 of monocrystalline substrate 252.
  • Electronic chip 240 includes an accommodating layer 260 and a compound semi-conductor layer 266.
  • Accommodating layer 260 is positioned between substrate 252 and compound semiconductor layer 266.
  • accommodating layer 260 may include a monocrystalline accommodating buffer layer, a monocrystalline accommodating buffer layer with an amorphous intermediate or interface layer, or an amorphous layer formed by annealing layers.
  • chip 240 also includes an indicator 268, which is configured to generate output in response to receipt, transmission, storage, processing or other manipulation of the electronic data that is stored on and/or processed by circuitry 256 on electronic chip 240.
  • indicator 268 is formed in compound semi-conductor layer 266 and is electrically coupled to circuitry 256 via conductor 270.
  • Electronic chip 240 may be configured to manipulate electronic data in response to communication between smartcard 250 and an externally located reader 200, such as that illustrated in FIG. 24. Reader 200 will often include a kiosk, terminal or other publicly accessible device. It may include a display screen 210 and/or an identifiable communications region 212, next to which smartcard 250 should be placed in order to communicate with chip reader 200.
  • chip reader 200 is a smartcard reader, readily available in the art.
  • smartcard 250 communicates with the smartcard reader while it is within a predetermined distance from communications region 212.
  • Circuitry 256 manipulates stored electronic data in response to this communication, and indicator 268 generates output in response to the manipulation of this electronic data.
  • indicator 268 generates visually readable output. This visually readable output is preferably optical output and it may be modulated optical output.
  • indicator 268 may include an associated display device for displaying text, graphical, and/or pictorial data.
  • Indicator 268 may, for example, include a display device such as a light emitting diode (LED) .
  • LED light emitting diode
  • Smartcards are currently being used to pay fares in public transportation systems.
  • a cardholder may pass a smartcard 250 near a reader 200 to have the appropriate fare deducted as he boards a bus or train.
  • indicator 268 may display a phrase on the face of the card that indicates that a fare has been received, or it may display a numerical value such as a dollar amount that has been paid and/or a dollar amount that remains on the user's card.
  • Smartcards 250 are also being used to access bank accounts and other financial information.
  • stock symbols or other personalized data that pertains to the cardholder's financial holdings may be stored on circuitry 256.
  • the cardholder may pass a smartcard 250 near a reader 200 to obtain, for example, a graph that displays the performance of one or more of her stock holdings over the course of a given period of time.
  • Smartcards 250 may also be used to conduct banking transactions.
  • a menu screen could be displayed on smartcard 250 when it is near reader 200 to present the cardholder with a list of transactions that could be conducted.
  • the display could include a touch screen that allows the cardholder to customize interactions with a reader 200 that is located, for example, in an automated teller machine that is connected to the bank's computer network.
  • the cardholder could touch one portion of the screen to transfer funds between, for example, a checking account and a savings account, touch another portion of the screen to pay a credit card balance, and touch still another portion of the screen to purchase stocks or mutual funds.
  • indicator 268 will preferably display text, graphics or pictorial data that will inform the cardholder that the appropriate transaction has taken place.
  • indicator 268 may include a light emitting diode (LED) , which may be located on the surface, edge, or other location on smartcard 250.
  • LED light emitting diode
  • Smartcard readers can usually only communicate with smartcards when they are inside a predetermined read field. If the card is inadvertently removed from this field, no data will be transferred.
  • the embodiment of the invention shown in FIG. 26 may be most useful when the cardholder needs only to know that data is being communicated. Thus, a smartcard with an LED may be used to inform the cardholder that the card has been placed close enough to the reader to carry out the desired transaction.
  • a smartcard 250 that includes LEDs may communicate with a reader 200 that has a very extensive range, to prevent the cardholder from venturing beyond a certain distance from the reader. While under such circumstances, it may not be necessary to pinpoint the cardholder's exact location, illumination (or termination of illumination) of the LED could warn the cardholder when he has wandered outside of the designated region.
  • visually readable data may be generated by a printer, plotter or other device that is capable of visual communication without the use of optics. In such embodiments, a hard copy of the data may be provided on paper, plastic, cardstock or similar media.
  • indicator 268 may also produce non- visual forms of output.
  • indicator 268 may generate an audible output in response to the manipulation of electronic data. Examples of such audible outputs include voice data as well as beeps, rings and other audible sounds.
  • smartcard 250 may have a speaker that includes a transducer formed in compound semiconductor layer 266.
  • a circuit that generates such an audible output may be linked to electronic chip 240 via a photodiode, photodetector or other photoconductive device.
  • an indicator 268 that causes at least a portion of the smartcard 250 to vibrate in response to the manipulation of electronic data on component 256 may be provided.
  • These embodiments may include a piezoelectric device linked to an accommodating layer made, for example, from barium titanate or strontium barium titanate.
  • These embodiments of the invention preferably also include an amplifier, which may enhance the ability to detect such vibration.
  • indicator 268 may be capable of generating multiple types of data, and that a single smartcard 250 may generate visual as well as audible and/or vibration output.
  • a reader 200 is embedded in a portable device, such as another smartcard, and two or more smartcards 250 can communicate with each other.
  • This other smartcard may be another smartcard 250 that incorporates the hybrid, monocrystalline semiconductor- compound semiconductor technology of device structure 50, or it may be a currently available smartcard with an electronic chip that is formed from a monocrystalline substrate, as illustrated in FIG. 23.
  • smartcard 250 may engage in either bidirectional or unidirectional communication.
  • a unidirectional communication embodiment of the invention may include a smartcard 250 that contains medical records.
  • the data stored on such a smartcard 250 could be viewed, updated or otherwise manipulated by authorized medical personnel during visits to a doctor's office using the associated LED or other display such as those described above, or via a connected computer monitor or other large display. These records could then be transmitted to another smartcard to enable a cardholder to carry such information with him.
  • Such a scheme would allow persons that are acutely ill or that otherwise need to provide fast and full access to their medical records to supply them to medical emergency personnel or to other persons that require such information.
  • the emergency personnel could simply pass the cardholder's smartcard next to a reader in order to access, update or otherwise manipulate the information.
  • the smartcard that is transported by the cardholder in the above example could be a presently available smartcard that does not provide user comprehendible output .
  • the authorized medical personnel that prepares the card may, for example, use smartcard 250 on which the medical records are stored to ensure that the appropriate data transfer has taken place.
  • the emergency or other personnel may confirm that a valid data transfer has taken place using reader 200 provided with smartcard 250 that is located in a first aid kit, ambulance, hospital emergency room or doctor's office.
  • the smartcard that is carried by the cardholder may also incorporate the technology of the present invention. Thus, it could provide some indication that data is communicated from one smartcard to another.
  • communication from one smartcard 250 to another smartcard is accomplished via a laser output 274 from indicator 268, and in the preferred embodiment, the laser output is modulated.
  • At least one activator 272 (e.g., a switch) is located on a surface of smartcard 250, ' and is used to initiate communication between circuitry 256 and reader 200.
  • Activators 272 will preferably be pressure sensitive contact points, but they may be any device that can trigger the communication of electronic data on demand by a cardholder. Thus, when activators 272 are provided, it may not be necessary to bring smartcard 250 next to electronic reader 200 to initiate data communication.
  • one or more LEDs 276, each of which is associated with an activator 272 may also be located on the surface of smartcard 250.
  • each activator 272 may initiate the communication of a different type of data. For example, when smartcard 250 is used to conduct banking activities, one activator 272 may cause a checking account balance to be displayed, while a second activator 272 is used to initiate the transfer of funds from a checking account to a savings account. Under such circumstances, the LED 276 that is adjacent to the respective activator 272 will preferably illuminate when the transaction takes place or as soon as it has been completed.
  • a portable wallet in which smartcard 250 may be stored when the smartcard is not communicating with card reader 200 is provided.
  • Such a wallet may be charged via a connection to a power supply.
  • the wallet can transmit additional energy to smartcard 250 while the card is not being used. This additional energy can then be stored in the smartcard for later use.
  • device structure 50 of FIG. 9 has been used to describe these embodiments of the invention, it will be appreciated that other embodiments may include additional semiconductor and oxide layers as illustrated in FIG. 10. It is intended to embrace all such alternative embodiments, and not to limit the invention to those embodiments of the invention that have been described here.
  • the terms "comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Abstract

A smartcard (250) that is capable of generating output in a form that is comprehendible by a cardholder is incorporated in a device that includes electronic circuitry (256) which is embedded in a monocrystalline substrate (252). The smartcard also includes a monocrystalline accommodating layer (260) positioned between the monocrystalline substrate (252) and a compound semi-conductor layer (266). The compound semiconductor layer (266) has an indicator (268) fashioned therein to provide a user interface. Use of the invention provides for an inexpensive way to create electrical components that generate optical output.

Description

ELECTRONICALLYMANIPULATED SMARTCARD GENERATINGUSERCOMPREHENDIBLE OUTPUT
Background of the Invention Smartcards are becoming increasingly popular. While such devices are very useful, one disadvantage in using them is that there is currently no way for the cardholder to tell, from the card itself, when data is communicated between the card and the associated device. Instead, the cardholder must typically rely on an indication that 'is provided by the reader or other external source in order to determine whether such communication has occurred. If these external sources are unavailable or inaccurate, a cardholder may take the smartcard away from the reader without actually completing the desired communication, or inadvertently communicate the same data multiple times.
Because of their credit-card size, smartcards cannot typically be supplied with batteries or other power sources. Contactless smartcards are typically powered by radio frequency
(RF) transmissions from a smartcard reader instead. While the use of RF transmissions is an effective way to energize a contactless smartcard, the amount of processing power that can be transmitted to the card in this manner is very limited. Thus, while it is desired to provide a contactless smartcard that is capable of informing the cardholder that communication to or from the smartcard has occurred, the limitations on the amount of power that can be transmitted to the smartcard make it impractical to perform this function using available technology. Brief Description of the Drawings
FIGs. 1, 2, 3, 9, 10 illustrate schematically, in cross section, device structures that can be used in accordance with various embodiments of the invention.
FIG. 4 illustrates graphically the relationship between maximum attainable film thickness and lattice mismatch between a host crystal and a grown crystalline overlayer. FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of illustrative semiconductor material manufactured in accordance with what is shown herein.
FIG. 6 is an x-ray diffraction taken on an illustrative semiconductor structure manufactured in accordance with what is shown herein.
FIG. 7 illustrates a high resolution Transmission Electron Micrograph of a structure including an amorphous oxide layer.
FIG. 8 illustrates an x-ray diffraction spectrum of a structure including an amorphous oxide layer. FIGs. 11-15 include illustrations of cross-sectional views of a portion of an integrated circuit that includes a compound semiconductor portion, a bipolar portion, and an MOS portion in accordance with what is shown herein.
FIGs. 16-22 include illustrations of cross-sectional views of a portion of another integrated circuit that includes a semiconductor laser and a MOS transistor in accordance with what is shown herein.
FIG. 23 illustrates one way that a device structure 50 can be incorporated in a smartcard according to an aspect of the present invention.
FIG. 24 shows an electronic chip reader that may be used to communicate with a smartcard according to an aspect of the invention. FIG. 25 depicts a smartcard of the present invention with a display on which text, graphics and or pictorial data may be provided.
FIG. 26 shows a smartcard that includes a light emitting diode according to an aspect of the invention.
FIG. 27 illustrates a smartcard that is capable of generating audible output, according to an aspect of the invention.
FIG. 28 depicts a smartcard that is capable of generating vibration output, according to an aspect of the invention.
FIG. 29 shows a smartcard that is capable of communication with a portable device, such as another smartcard, according to an aspect of the invention.
FIG. 30 illustrates a smartcard that includes data communication activators and associated light emitting diodes.
Skilled artisans will appreciate that in many cases elements in certain FIGs . are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in certain FIGs. may be exaggerated relative to other elements to help to improve understanding of what is being shown.
Detailed Description of the Drawings
The present invention involves semiconductor structures of particular types. For convenience herein, these semiconductor structures are sometimes referred to as "composite semiconductor structures" or "composite integrated circuits" because they include two (or more) significantly different types of semiconductor devices in one integrated structure or circuit. For example, one of these two types of devices may be silicon-based devices such as CMOS devices, and the other of these two types of devices may be compound semiconductor devices such GaAs devices. Illustrative composite semiconductor structures and methods for making such structures are disclosed in Ramdani et al. U.S. patent application No. 09/502,023, filed February 10, 2000, which is hereby incorporated by reference herein in its entirety. Certain material from that reference is substantially repeated below to ensure that there is support herein for references to composite semiconductor structures and composite integrated circuits. FIG. 1 illustrates schematically, in cross section, a portion of a semiconductor structure 20 which may be relevant to or useful in connection with certain embodiments of the present invention. Semiconductor structure 20 includes a monocrystalline substrate 22, accommodating buffer layer 24 comprising a monocrystalline material, and a layer 26 of a monocrystalline compound semiconductor material. In this context, the term "monocrystalline" shall have the meaning commonly used within the semiconductor industry. The term shall refer to materials that are a single crystal or that are substantially a single crystal and shall include those materials having a relatively small number of defects such as dislocations and the like as are commonly found in substrates of silicon or germanium or mixtures of silicon and germanium and epitaxial layers of such materials commonly found in the semiconductor industry. In accordance with one embodiment, structure 20 also includes an amorphous intermediate layer 28 positioned between substrate 22 and accommodating buffer layer 24. Structure 20 may also include a template layer 30 between accommodating buffer layer 24 and compound semiconductor layer 26. As will be explained more fully below, template layer 30 helps to initiate the growth of compound semiconductor layer 26 on accommodating buffer layer 24. Amorphous intermediate layer 28 helps to relieve the strain in accommodating buffer layer 24 and by doing so, aids in the growth of a high crystalline quality accommodating buffer layer 24.
Substrate 22, in accordance with one embodiment, is a monocrystalline semiconductor wafer, preferably of large diameter. The wafer can be of a material from Group IV of the periodic table, and preferably a material from Group IVA. Examples of
Group IV semiconductor materials include silicon, germanium, mixed silicon and germanium, mixed silicon and carbon, mixed silicon, germanium and carbon, and the like. Preferably substrate 22 is a wafer containing silicon or germanium, and most preferably is a high quality monocrystalline silicon wafer as used in the semiconductor industry. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material epitaxially grown on the underlying substrate 22. In accordance with one embodiment, amorphous intermediate layer 28 is grown on substrate 22 at the interface between substrate 22 and the growing accommodating buffer layer 24 by the oxidation of substrate 22 during the growth of layer 24. Amorphous intermediate layer 28 serves to relieve strain that might otherwise occur in monocrystalline accommodating buffer layer 24 as a result of differences in the lattice constants of substrate 22 and buffer layer 24. As used herein, lattice constant refers to the distance between atoms of a cell measured in the plane of the surface. If such strain is not relieved by amorphous intermediate layer 28, the strain may cause defects in the crystalline structure of accommodating buffer layer 24. Defects in the crystalline structure of accommodating buffer layer 24, in turn, would make it difficult to achieve a high quality crystalline structure in monocrystalline compound semiconductor layer 26. Accommodating buffer layer 24 is preferably a monocrystalline oxide or nitride material selected for its crystalline compatibility with underlying substrate 22 and with overlying compound semiconductor material 26. For example, the material could be an oxide or nitride having a lattice structure matched to substrate 22 and to the subsequently applied semiconductor material 26. Materials that are suitable for accommodating buffer layer 24 include metal oxides such as the alkaline earth metal titanates, alkaline earth metal zirconates, alkaline earth metal hafnates, alkaline earth metal tantalates, alkaline earth metal ruthenates, alkaline earth metal niobates, alkaline earth metal vanadates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide. Additionally, various nitrides such as gallium nitride, aluminum nitride, and boron nitride may also be used for accommodating buffer layer 24. Most of these materials are insulators, although strontium ruthenate, for example, is a conductor. Generally, these materials are metal oxides or metal nitrides, and more particularly, these metal oxide or nitrides typically include at least two different metallic elements. In some specific applications, the metal oxides or nitride may include three or more different metallic elements.
Amorphous interface layer 28 is preferably an oxide formed by the oxidation of the surface of substrate 22, and more preferably is composed of a silicon oxide. The thickness of layer 28 is sufficient to relieve strain attributed to mismatches between the lattice constants of substrate 22 and accommodating buffer layer 2 . Typically, layer 28 has a thickness in the range of approximately 0.5-5 nm. The compound semiconductor material of layer 26 can be selected, as needed for a particular semiconductor structure, from any of the Group IIIA and VA elements (III-V semiconductor compounds), mixed III-V compounds, Group II (A or B) and VIA elements (II-VI semiconductor compounds), and mixed II-VI compounds. Examples include gallium arsenide (GaAs) , gallium indium arsenide (GalnAs), gallium aluminum arsenide (GaAlAs), indium phosphide (InP) , cadmium sulfide (CdS) , cadmium mercury telluride (CdHgTe) , zinc selenide (ZnSe) , zinc sulfur selenide (ZnSSe), and the like. Suitable template 30 materials chemically bond to the surface of the accommodating buffer layer 24 at selected sites and provide sites for the nucleation of the epitaxial growth of the subsequent compound semiconductor layer 26. Appropriate materials for template 30 are discussed below. FIG. 2 illustrates, in cross section, a portion of a semiconductor structure 40 in accordance with a further embodiment. Structure 40 is similar to the previously described semiconductor structure 20 except that an additional buffer layer 32 is positioned between accommodating buffer layer 24 and layer of monocrystalline compound semiconductor material 26.
Specifically, additional buffer layer 32 is positioned between the template layer 30 and the overlying layer 26 of compound semiconductor material. Additional buffer layer 32, formed of a semiconductor or compound semiconductor material, serves to provide a lattice compensation when the lattice constant of accommodating buffer layer 24 cannot be adequately matched to the overlying monocrystalline compound semiconductor material layer 26.
FIG. 3 schematically illustrates, in cross section, a portion of a semiconductor structure 34 in accordance with another exemplary embodiment of the invention. Structure 34 is similar to structure 20, except that structure 34 includes an amorphous layer 36, rather than accommodating buffer layer 24 and amorphous interface layer 28, and an additional semiconductor layer 38. As explained in greater detail below, amorphous layer 36 may be formed by first forming an accommodating buffer layer and an amorphous interface layer in a similar manner to that described above. Monocrystalline semiconductor layer 26 is then formed (by epitaxial growth) overlying the monocrystalline accommodating buffer layer. The accommodating buffer layer is then exposed to an anneal process to convert the monocrystalline accommodating buffer layer to an amorphous layer. Amorphous layer 36 formed in this manner comprises materials from both the accommodating buffer and interface layers, which amorphous layers may or may not amalgamate. Thus, layer 36 may comprise one or two amorphous layers. Formation of amorphous layer 36 between substrate 22 and semiconductor layer 38 (subsequent to layer 38 formation) relieves stresses between layers 22 and 38 and provides a true compliant substrate for subsequent processing—e.g., compound semiconductor layer 26 formation.
The processes previously described above in connection with FIGS. 1 and 2 are adequate for growing monocrystalline compound semiconductor layers over a monocrystalline substrate. However, the process described in connection with FIG. 3, which includes transforming a monocrystalline accommodating buffer layer to an amorphous oxide layer, may be better for growing monocrystalline compound semiconductor layers because it allows any strain in layer 26 to relax. Semiconductor layer 38 may include any of the materials described throughout this application in connection with either of compound semiconductor material layer 26 or additional buffer layer 32. For example, layer 38 may include monocrystalline Group IV or monocrystalline compound semiconductor materials. In accordance with one embodiment of the present invention, semiconductor layer 38 serves as an anneal cap during layer 36 formation and as a template for subsequent semiconductor layer 26 formation. Accordingly, layer 38 is preferably thick enough to provide a suitable template for layer 26 growth (at least one monolayer) and thin enough to allow layer 38 to form as a substantially defect free monocrystalline semiconductor compound.
In accordance with another embodiment of the invention, semiconductor layer 38 comprises compound semiconductor material (e.g., a material discussed above in connection with compound semiconductor layer 26) that is thick enough to form devices within layer 38. In this case, a semiconductor structure in accordance with the present invention does not include compound semiconductor layer 26. In other words, the semiconductor structure in accordance with this embodiment only includes one compound semiconductor layer disposed above amorphous oxide layer 36.
The layer formed on substrate 22, whether it includes only accommodating buffer layer 24, accommodating buffer layer 24 with amorphous intermediate or interface layer 28, or an amorphous layer such as layer 36 formed by annealing layers 24 and 28 as described above in connection with FIG. 3, may be referred to generically as an "accommodating layer."
The following non-limiting, illustrative examples illustrate various combinations of materials useful in structures 20, 40 and 34 in accordance with various alternative embodiments. These examples are merely illustrative, and it is not intended that the invention be limited to these illustrative examples.
Example 1
In accordance with one embodiment, monocrystalline substrate 22 is a silicon substrate oriented in the (100) direction.
Silicon substrate 22 can be, for example, a silicon substrate as is commonly used in making complementary metal oxide semiconductor (CMOS) integrated circuits having a diameter of about 200-300 mm. In accordance with this embodiment, accommodating buffer layer 24 is a monocrystalline layer of SrzBaι-zTi03 where z ranges from 0 to 1 and amorphous intermediate layer 28 is a layer of silicon oxide (SiOx) formed at the interface between silicon substrate 22 and accommodating buffer layer 24. The value of z is selected to obtain one or more lattice constants closely matched to corresponding lattice constants of the subsequently formed layer
26. Accommodating buffer layer 24 can have a thickness of about 2 to about 100 nanometers (nm) and preferably has a thickness of about 10 nm. In general, it is desired to have an accommodating buffer layer 24 thick enough to isolate compound semiconductor layer 26 from substrate 22 to obtain the desired electrical and optical properties. Layers thicker than 100 nm usually provide little additional benefit while increasing cost unnecessarily; however, thicker layers may be fabricated if needed. The amorphous intermediate layer 28 of silicon oxide can have a thickness of about 0.5-5 nm, and preferably a thickness of about 1.5-2.5 nm.
In accordance with this embodiment, compound semiconductor material layer 26 is a layer of gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs) haying a thickness of about 1 nm to about 100 micrometers (μm) and preferably a thickness of about 0.5 μm to 10 μm. The thickness generally depends on the application for which the layer is being prepared. To facilitate the epitaxial growth of the gallium arsenide or aluminum gallium arsenide on the monocrystalline oxide, a template layer 30 is formed by capping the oxide layer. Template layer 30 is preferably 1-10 monolayers of Ti-As, Sr-O-As, Sr-Ga-O, or Sr-Al-O. By way of a preferred example, 1-2 monolayers 30 of Ti-As or Sr- Ga-0 have been shown to successfully grow GaAs layers 26.
Example 2
In accordance with a further embodiment, monocrystalline substrate 22 is a silicon substrate as described above. Accommodating buffer layer 24 is a monocrystalline oxide of strontium or barium zirconate or hafnate in a cubic or orthorhombic phase with an amorphous intermediate layer 28 of silicon oxide formed at the interface between silicon substrate 22 and accommodating buffer layer 24. Accommodating buffer layer 24 can have a thickness of about 2-100 nm and preferably has a thickness of at least 5 nm to ensure adequate crystalline and surface quality and is formed of a monocrystalline SrZr03, BaZr03, SrHf03, BaSn03 or BaHf03. For example, a monocrystalline oxide layer of BaZr0 can grow at a temperature of about 700 degrees C. The lattice structure of the resulting crystalline oxide exhibits a 45 degree rotation with respect to the substrate 22 silicon lattice structure.
An accommodating buffer layer 24 formed of these zirconate or hafnate materials is suitable for the growth of compound semiconductor materials 26 in the indium phosphide (InP) system.
The compound semiconductor material 26 can be, for example, indium phosphide (InP), indium gallium arsenide (InGaAs), aluminum indium arsenide, (AlInAs) , or aluminum gallium indium arsenic phosphide (AlGalnAsP) , having a thickness of about 1.0 nm to 10 μm. A suitable template 30 for this structure is 1-10 monolayers of zirconium-arsenic (Zr-As) , zirconium-phosphorus (Zr-P), hafnium- arsenic (Hf-As), hafnium-phosphorus (Hf-P) , strontium-oxygen- arsenic (Sr-O-As) , strontium-oxygen-phosphorus (Sr-O-P) , barium- oxygen-arsenic (Ba-O-As) , indium-strontium-oxygen (In-Sr-O) , or barium-oxygen-phosphorus (Ba-O-P) , and preferably 1-2 monolayers of one of these materials. By way of an example, for a barium zirconate accommodating buffer layer 24, the surface is terminated with 1-2 monolayers of zirconium followed by deposition of 1-2 monolayers of arsenic to form a Zr-As template 30. A monocrystalline layer 26 of the compound semiconductor material from the indium phosphide system is then grown on template layer 30. The resulting lattice structure of the compound semiconductor material 26 exhibits a 45 degree rotation with respect to the accommodating buffer layer 24 lattice structure and a lattice mismatch to (100) InP of less than 2.5%, and preferably less than about 1.0%.
Example 3
In accordance with a further embodiment, a structure is provided that is suitable for the growth of an epitaxial film of a II-VI material overlying a silicon substrate 22. The substrate 22 is preferably a silicon wafer as described above. A suitable accommodating buffer layer 24 material is SrxBa! _xTi03, where x ranges from 0 to 1, having a thickness of about 2-100 nm and preferably a thickness of about 5-15 nm. The II-VI compound semiconductor material 26 can be, for example, zinc selenide (ZnSe) or zinc sulfur selenide (ZnSSe) . A suitable template 30 for this material system includes 1-10 monolayers of zinc-oxygen
(Zn-O) followed by 1-2 monolayers of an excess of zinc followed by the selenidation of zinc on the surface. Alternatively, a template 30 can be, for example, 1-10 monolayers of strontium- sulfur (Sr-S) followed by the ZnSeS.
Example 4 This embodiment of the invention is an example of structure 40 illustrated in FIG. 2. Substrate 22, monocrystalline oxide layer 24, and monocrystalline compound semiconductor material layer 26 can be similar to those described in example 1. In addition, an additional buffer layer 32 serves to alleviate any strains that might result from a mismatch of the crystal lattice of the accommodating buffer layer and the lattice of the monocrystalline semiconductor material. Buffer layer 32 can be a layer of germanium or a GaAs, an aluminum gallium arsenide (AlGaAs) , an indium gallium phosphide (InGaP) , an aluminum gallium phosphide (AlGaP) , an indium gallium arsenide (InGaAs) , an aluminum indium phosphide (AllnP) , a gallium arsenide phosphide (GaAsP) , or an indium gallium phosphide (InGaP) strain compensated superlattice. In accordance with one aspect of this embodiment, buffer layer 32 includes a GaAsxP! -x superlattice, wherein the value of x ranges from 0 to 1. In accordance with another aspect, buffer layer 32 includes an InyGa! -yP superlattice, wherein the value of y ranges from 0 to 1. By varying the value of x or y, as the case may be, the lattice constant is varied from bottom to top across the superlattice to create a match between lattice constants of the underlying oxide and the overlying compound semiconductor material. The compositions of other materials, such as those listed above, may also be similarly varied to manipulate the lattice constant of layer 32 in a like manner. The superlattice can have a thickness of about 50-500 nm and preferably has a thickness of about 100-200 nm. The template for this structure can be the same of that described in example 1. Alternatively, buffer layer 32 can be a layer of monocrystalline germanium having a thickness of 1-50 nm and preferably having a thickness of about 2-20 nm. In using a germanium buffer layer, a template layer of either germanium-strontium (Ge-Sr) or germanium- titanium (Ge-Ti) having a thickness of about one monolayer can be used as a nucleating site for the subsequent growth of the monocrystalline compound semiconductor material layer. The formation of the oxide layer is capped with either a monolayer of strontium or a monolayer of titanium to act as a nucleating site for the subsequent deposition of the monocrystalline germanium. The monolayer of strontium or titanium provides a nucleating site to which the first monolayer of germanium can bond.
Example 5
This example also illustrates materials useful in a structure 40 as illustrated in FIG. 2. Substrate material 22, accommodating buffer layer 24, monocrystalline compound semiconductor material layer 26 and template layer 30 can be the same as those described above in example 2. In addition, a buffer layer 32 is inserted between accommodating buffer layer 24 and overlying monocrystalline compound semiconductor material layer 26. Buffer layer 32, a further monocrystalline semiconductor material, can be, for example, a graded layer of indium gallium arsenide (InGaAs) or indium aluminum arsenide (InAlAs) . In accordance with one aspect of this embodiment, buffer layer 32 includes InGaAs, in which the indium composition varies from 0 to about 47%. Buffer layer 32 preferably has a thickness of about 10-30 nm. Varying the composition of buffer layer 32 from GaAs to InGaAs serves to provide a lattice match between the underlying monocrystalline oxide material 24 and the overlying layer 26 of monocrystalline compound semiconductor material. Such a buffer layer 32 is especially advantageous if there is a lattice mismatch between accommodating buffer layer 24 and monocrystalline compound semiconductor material layer 26.
Example 6
This example provides exemplary materials useful in structure 34, as illustrated in FIG. 3. Substrate material 22, template layer 30, and monocrystalling compound semiconductor material layer 26 may be the same as those described above in connection with example 1.
Amorphous layer 36 is an amorphous oxide layer which is suitably formed of a combination of amorphous intermediate layer materials (e.g., layer 28 materials as described above) and accommodating buffer layer materials (e.g., layer 24 materials as described above) . For example, amorphous layer 36 may include a combination of SiOx and SrzBal-z Ti03 (where z ranges from 0 to 1) ,which combine or mix, at least partially, during an anneal process to form amorphous oxide layer 36.
The thickness of amorphous layer 36 may vary from application to application and may depend on such factors as desired insulating properties of layer 36, type of semiconductor material comprising layer 26, and the like. In accordance with one exemplary aspect of the present embodiment, layer 36 thickness is about 2 nm to about 100 nm, preferably about 2-10 nm, and more preferably about 5-6 nm.
Layer 38 comprises a monocrystalline compound semiconductor material that can be grown epitaxially over a monocrystalline oxide material such as material used to form accommodating buffer layer 24. In accordance with one embodiment of the invention, layer 38 includes the same materials as those comprising layer 26. For example, if layer 26 includes GaAs, layer 38 also includes GaAs. However, in accordance with other embodiments of the present invention, layer 38 may include materials different from those used to form layer 26. In accordance with one exemplary embodiment of the invention, layer 38 is about 1 monolayer to about 100 nm thick.
Referring again to FIGS. 1-3, substrate 22 is a monocrystalline substrate such as a monocrystalline silicon substrate. The crystalline structure of the monocrystalline substrate is characterized by a lattice constant and by a lattice orientation. In similar manner, accommodating buffer layer 24 is also a monocrystalline material and the lattice of that monocrystalline material is characterized by a lattice constant and a crystal orientation. The lattice constants of accommodating buffer layer 24 and monocrystalline substrate 22 must be closely matched or, alternatively, must be such that upon rotation of one crystal orientation with respect to the other crystal orientation, a substantial match in lattice constants is achieved. In this context the terms "substantially equal" and "substantially matched" mean that there is sufficient similarity between the lattice constants to permit the growth of a high quality crystalline layer on the underlying layer.
FIG. 4 illustrates graphically the relationship of the achievable thickness of a grown crystal layer of high crystalline quality as a function of the mismatch between the lattice constants of the host crystal and the grown crystal . Curve 42 illustrates the boundary of high crystalline quality material.
The area to the right of curve 42 represents layers that tend to be polycrystalline. With no lattice mismatch, it is theoretically possible to grow an infinitely thick, high quality epitaxial layer on the host crystal. As the mismatch in lattice constants increases, the thickness of achievable, high quality crystalline layer decreases rapidly. As a reference point, for example, if the lattice constants between the host crystal and the grown layer are mismatched by more than about 2%, monocrystalline epitaxial layers in excess of about 20 nm cannot be achieved. In accordance with one embodiment, substrate 22 is a (100) or (111) oriented monocrystalline silicon wafer and accommodating buffer layer 24 is a layer of strontium barium titanate. Substantial matching of lattice constants between these two materials is achieved by rotating the crystal orientation of the titanate material 24 by 45° with respect to the crystal orientation of the silicon substrate wafer 22. The inclusion in the structure of amorphous interface layer 28, a silicon oxide layer in this example, if it is of sufficient thickness, serves to reduce strain in the titanate monocrystalline layer 24 that might result from any mismatch in the lattice constants of the host silicon wafer 22 and the grown titanate layer 24. As a result, a high quality, thick, monocrystalline titanate layer 24 is achievable. Still referring to FIGS. 1-3, layer 26 is a layer of epitaxially grown monocrystalline material and that crystalline material is also characterized by a crystal lattice constant and a crystal orientation. In accordance with one embodiment of the invention, the lattice constant of layer 26 differs from the lattice constant of substrate 22. To achieve high crystalline quality in this epitaxially grown monocrystalline layer, accommodating buffer layer 24 must be of high crystalline quality. In addition, in order to achieve high crystalline quality in layer 26, substantial matching between the crystal lattice constant of the host crystal, in this case, monocrystalline accommodating buffer layer 24, and grown crystal 26 is desired. With properly selected materials this substantial matching of lattice constants is achieved as a result of rotation of the crystal orientation of grown crystal 26 with respect to the orientation of host crystal 24. If grown crystal 26 is gallium arsenide, aluminum gallium arsenide, zinc selenide, or zinc sulfur selenide and accommodating buffer layer 24 is monocrystalline SrxBaι. -xTi03, substantial matching of crystal lattice constants of the two materials is achieved, wherein the crystal orientation of grown layer 26 is rotated by 45° with respect to the orientation of the host monocrystalline oxide 24. Similarly, if host material 24 is a strontium or barium zirconate or a strontium or barium hafnate or barium tin oxide and compound semiconductor layer 26 is indium phosphide or gallium indium arsenide or aluminum indium arsenide, substantial matching of crystal lattice constants can be achieved by rotating the orientation of grown crystal layer 26 by 45° with respect to host oxide crystal 24. In some instances, a crystalline semiconductor buffer layer 32 between host oxide 24 and grown compound semiconductor layer 26 can be used to reduce strain in grown monocrystalline compound semiconductor layer 26 that might result from small differences in lattice constants. Better crystalline quality in grown monocrystalline compound semiconductor layer 26 can thereby be achieved. The following example illustrates a process, in accordance with one embodiment, for fabricating a semiconductor structure such as the structures depicted in FIGS. 1-3. The process starts by providing a monocrystalline semiconductor substrate 22 comprising silicon or germanium. In accordance with a preferred embodiment, semiconductor substrate 22 is a silicon wafer having a (100) orientation. Substrate 22 is preferably oriented on axis or, at most, about 0.5° off' axis. At least a portion of semiconductor substrate 22 has a bare surface, although other portions of the substrate, as described below, may encompass other structures. The term "bare" in this context means that the surface in the portion of substrate 22 has been cleaned to remove any oxides, contaminants, or other foreign material. As is well known, bare silicon is highly reactive and readily forms a native oxide. The term "bare" is intended to encompass such a native oxide. A thin silicon oxide may also be intentionally grown on the semiconductor substrate, although such a grown oxide is not essential to the process. In order to epitaxially grow a monocrystalline oxide layer 24 overlying monocrystalline substrate 22, the native oxide layer must first be removed to expose the crystalline structure of underlying substrate 22. The following process is preferably carried out by molecular beam epitaxy (MBE) , although other epitaxial processes may also be used in accordance with the present invention. The native oxide can be removed by first thermally depositing a thin layer of strontium, barium, a combination of strontium and barium, or other alkali earth metals or combinations of alkali earth metals in an MBE apparatus. In the case where strontium is used, the substrate 22 is then heated to a temperature of about 750°C to cause the strontium to react with the native silicon oxide layer. The strontium serves to reduce the silicon oxide to leave a silicon oxide-free surface. The resultant surface, which exhibits an ordered 2x1 structure, includes strontium, oxygen, and silicon. The ordered 2x1 structure forms a template for the ordered growth of an overlying layer 24 of a monocrystalline oxide. The template provides the necessary chemical and physical properties to nucleate the crystalline growth of an overlying layer 24.
In accordance with an alternate embodiment, the native silicon oxide can be converted and the surface of substrate 22 can be prepared for the growth of a monocrystalline oxide layer 24 by depositing an alkali earth metal oxide, such as strontium oxide or barium oxide, onto the substrate surface by MBE at a low temperature and by subsequently heating the structure to a temperature of about 750°C. At this temperature a solid state reaction takes place between the strontium oxide and the native silicon oxide causing the reduction of the native silicon oxide and leaving an ordered 2x1 structure with strontium, oxygen, and silicon remaining on the substrate 22 surface. Again, this forms a template for the subsequent growth of an ordered monocrystalline oxide layer 24.
Following the removal of the silicon oxide from the surface of substrate 22, the substrate is cooled to a temperature in the range of about 200-800°C and a layer 24 of strontium titanate is grown on the template layer by molecular beam epitaxy. The MBE process is initiated by opening shutters in the MBE apparatus to expose strontium, titanium and oxygen sources. The ratio of strontium and titanium is approximately 1:1. The partial pressure of oxygen is initially set at a minimum value to grow stochiometric strontium titanate at a growth rate of about 0.3-0.5 nm per minute. After initiating growth of the strontium titanate, the partial pressure of oxygen is increased above the initial minimum value. The overpressure of oxygen causes the growth of an amorphous silicon oxide layer 28 at the interface between underlying substrate 22 and the growing strontium titanate layer 24. The growth of silicon oxide layer 28 results from the diffusion of oxygen through the growing strontium titanate layer 24 to the interface where the oxygen reacts with silicon at the surface of underlying substrate 22. The strontium titanate grows as an ordered monocrystal 24 with the crystalline orientation rotated by 45° with respect to the ordered 2x1 crystalline structure of underlying substrate 22. Strain that otherwise might exist in strontium titanate layer 24 because of the small mismatch in lattice constant between silicon substrate 22 and the growing crystal 24 is relieved in amorphous silicon oxide intermediate layer 28.
After strontium titanate layer 24 has been grown to the desired thickness, the monocrystalline strontium titanate is capped by a template layer 30 that is conducive to the subsequent growth of an epitaxial layer of a desired compound semiconductor material 26. For the subsequent growth of a layer 26 of gallium arsenide, the MBE growth of strontium titanate monocrystalline layer 24 can be capped by terminating the growth with 1-2 monolayers of titanium, 1-2 monolayers of titanium-oxygen or with 1-2 monolayers of strontium-oxygen. Following the formation of this capping layer, arsenic is deposited to form a Ti-As bond, a Ti-O-As bond or a Sr-O-As. Any of these form an appropriate template 30 for deposition and formation of a gallium arsenide monocrystalline layer 26. Following the formation of template 30, gallium is subsequently introduced to the reaction with the arsenic and gallium arsenide 26 forms. Alternatively, gallium can be deposited on the capping layer to form a Sr-O-Ga bond, and arsenic is subsequently introduced with the gallium to form the GaAs. FIG. 5 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the present invention. Single crystal SrTi03 accommodating buffer layer 24 was grown epitaxially on silicon substrate 22. During this growth process, amorphous interfacial layer 28 is formed which relieves strain due to lattice mismatch. GaAs compound semiconductor layer 26 was then grown epitaxially using template layer 30.
FIG. 6 illustrates an x-ray diffraction spectrum taken on structure including GaAs compound semiconductor layer 26 grown on silicon substrate 22 using accommodating buffer layer 24. The peaks in the spectrum indicate that both the accommodating buffer layer 24 and GaAs compound semiconductor layer 26 are single crystal and (100) orientated. The structure illustrated in FIG. 2 can be formed by the process discussed above with the addition of an additional buffer layer 32 deposition step. Buffer layer 32 is formed overlying template layer 30 before the deposition of monocrystalline compound semiconductor layer 26. If buffer layer 32 is a compound semiconductor superlattice, such a superlattice can be deposited, by MBE for example, on the template 30 described above. If instead buffer layer 32 is a layer of germanium, the process above is modified to cap strontium titanate monocrystalline layer 24 with a final layer of either strontium or titanium and then by depositing germanium to react with the strontium or titanium. The germanium buffer layer 32 can then be deposited directly on this template 30.
Structure 34, illustrated in FIG. 3, may be formed by growing an accommodating buffer layer, forming an amorphous oxide layer over substrate 22, and growing semiconductor layer 38 over the accommodating buffer layer, as described above. The accommodating buffer layer and the amorphous oxide layer are then exposed to an anneal process sufficient to change the crystalline structure of the accommodating buffer layer from monocrystalline to amorphous, thereby forming an amorphous layer such that the combination of the amorphous oxide layer and the now amorphous accommodating buffer layer form a single amorphous oxide layer 36. Layer 26 is then subsequently grown over layer 38. Alternatively, the anneal process may be carried out subsequent to growth of layer 26.
In accordance with one aspect of this embodiment, layer 36 is formed by exposing substrate 22, the accommodating buffer layer, the amorphous oxide layer, and semiconductor layer 38 to a rapid thermal anneal process with a peak temperature of about 700°C to about 1000°C and a process time of about 1 to about 10 minutes. However, other suitable anneal processes may be employed to convert the accommodating buffer layer to an amorphous layer in accordance with the present invention. For example, laser annealing or "conventional" thermal annealing processes (in the proper environment) may be used to form layer 36. When conventional thermal annealing is employed to form layer 36, an overpressure of one or more constituents of layer 30 may be required to prevent degradation of layer 38 during the anneal process. For example, when layer 38 includes GaAs, the anneal environment preferably includes an overpressure of arsenic to mitigate degradation of layer 38.
As noted above, layer 38 of structure 34 may include any materials suitable for either of layers 32 or 26. Accordingly, any deposition or growth methods described in connection with either layer 32 or 26, may be employed to deposit layer 38.
FIG. 7 is a high resolution Transmission Electron Micrograph (TEM) of semiconductor material manufactured in accordance with the embodiment of the invention illustrated in FIG. 3. In Accordance with this embodiment, a single crystal SrTi03 accommodating buffer layer was grown epitaxially on silicon substrate 22. During this growth process, an amorphous interfacial layer forms as described above. Next, GaAs layer 38 is formed above the accommodating buffer layer and the accommodating buffer layer is exposed to an anneal process to form amorphous oxide layer 36.
FIG. 8 illustrates an x-ray diffraction spectrum taken on a structure including GaAs compound semiconductor layer 38 and amorphous oxide layer 36 formed on silicon substrate 22. The peaks in the spectrum indicate that GaAs compound semiconductor layer 38 is single crystal and (100) orientated and the lack of peaks around 40 to 50 degrees indicates that layer 36 is amorphous .
The process described above illustrates a process for forming a semiconductor structure including a silicon substrate 22, an overlying oxide layer, and a monocrystalline gallium arsenide compound semiconductor layer 26 by the process of molecular beam epitaxy. The process can also be carried out by the process of chemical vapor deposition (CVD) , metal organic chemical vapor deposition (MOCVD) , migration enhanced epitaxy (MEE) , atomic layer epitaxy (ALE) , physical vapor deposition (PVD) , chemical solution deposition (CSD) , pulsed laser deposition (PLD) , or the like. Further, by a similar process, other monocrystalline accommodating buffer layers 24 such as alkaline earth metal titanates, zirconates, hafnates, tantalates, vanadates, ruthenates, and niobates, perovskite oxides such as alkaline earth metal tin-based perovskites, lanthanum aluminate, lanthanum scandium oxide, and gadolinium oxide can also be grown. Further, by a similar process such as MBE, other III-V and II-VI monocrystalline compound semiconductor layers 26 can be deposited overlying monocrystalline oxide accommodating buffer layer 24. Each of the variations of compound semiconductor materials 26 and monocrystalline oxide accommodating buffer layer 24 uses an appropriate template 30 for initiating the growth of the compound semiconductor layer. For example, if accommodating buffer layer 24 is an alkaline earth metal zirconate, the oxide can be capped by a thin layer of zirconium. The deposition of zirconium can be followed by the deposition of arsenic or phosphorus to react with the zirconium as a precursor to depositing indium gallium arsenide, indium aluminum arsenide, or indium phosphide respectively. Similarly, if monocrystalline oxide accommodating buffer layer 24 is an alkaline earth metal hafnate, the oxide layer can be capped by a thin layer of hafnium. The deposition of hafnium is followed by the deposition of arsenic or phosphorous to react with the hafnium as a precursor to the growth of an indium gallium arsenide, indium aluminum arsenide, or indium phosphide layer 26, respectively. In a similar manner, strontium titanate 24 can be capped with a layer of strontium or strontium and oxygen, and barium titanate 24 can be capped with a layer of barium or barium and oxygen. Each of these depositions can be followed by the deposition of arsenic or phosphorus to react with the capping material to form a template 30 for the deposition of a compound semiconductor material layer 26 comprising indium gallium arsenide, indium aluminum arsenide, or indium phosphide.
FIG. 9 illustrates schematically, in cross section, a device structure 50 in accordance with a further embodiment. Device structure 50 includes a monocrystalline semiconductor substrate 52, preferably a monocrystalline silicon wafer. Monocrystalline semiconductor substrate 52 includes two regions, 53 and 54. An electrical semiconductor component generally indicated by the dashed line 56 is formed, at least partially, in region 53.
Electrical component 56 can be a resistor, a capacitor, an active semiconductor component such as a diode or a transistor or an integrated circuit such as a CMOS integrated circuit . For example, electrical semiconductor component 56 can be a CMOS integrated circuit configured to perform digital signal processing or another function for which silicon integrated circuits are well suited. The electrical semiconductor component in region 53 can be formed by conventional semiconductor processing as well known and widely practiced in the semiconductor industry. A layer of insulating material 58 such as a layer of silicon dioxide or the like may overlie electrical semiconductor component 56.
Insulating material 58 and any other layers that may have been formed or deposited during the processing of semiconductor component 56 in region 53 are removed from the surface of region 54 to provide a bare silicon surface in that region. As is well known, bare silicon surfaces are highly reactive and a native silicon oxide layer can quickly form on the bare surface. A layer of barium or barium and oxygen is deposited onto the native oxide layer on the surface of region 54 and is reacted with the oxidized surface to form a first template layer (not shown) . In accordance with one embodiment, a monocrystalline oxide layer is formed overlying the template layer by a process of molecular beam epitaxy. Reactants including barium, titanium and oxygen are deposited onto the template layer to form the monocrystalline oxide layer. Initially during the deposition the partial pressure of oxygen is kept near the minimum necessary to fully react with the barium and titanium to form monocrystalline barium titanate layer. The partial pressure of oxygen is then increased to provide an overpressure of oxygen and to allow oxygen to diffuse through the growing monocrystalline oxide layer. The oxygen diffusing through the barium titanate reacts with silicon at the surface of region 54 to form an amorphous layer of silicon oxide on second region 54 and at the interface between silicon substrate 52 and the monocrystalline oxide. Layers 60 and 62 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
In accordance with an embodiment, the step of depositing the monocrystalline oxide layer is terminated by depositing a second template layer 60, which can be 1-10 monolayers of titanium, barium, barium and oxygen, or titanium and oxygen. A layer 66 of a monocrystalline compound semiconductor material is then deposited overlying second template layer 64 by a process of molecular beam epitaxy. The deposition of layer 66 is initiated by depositing a layer of arsenic onto template 64. This initial step is followed by depositing gallium and arsenic to form monocrystalline gallium arsenide 66. Alternatively, strontium can be substituted for barium in the above example. In accordance with a further embodiment, a semiconductor component, generally indicated by a dashed line 68 is formed in compound semiconductor layer 66. Semiconductor component 68 can be formed by processing steps conventionally used in the fabrication of gallium arsenide or other III-V compound semiconductor material devices . Semiconductor component 68 can be any active or passive component, and preferably is a semiconductor laser, light emitting diode, photodetector, heterojunction bipolar transistor (HBT) , high frequency MESFET, or other component that utilizes and takes advantage of the physical properties of compound semiconductor materials. A metallic conductor schematically indicated by the line 70 can be formed to electrically couple device 68 and device 56, thus implementing an integrated device that includes at least one component formed in silicon substrate 52 and one device formed in monocrystalline compound semiconductor material layer 66. Although illustrative structure 50 has been described as a structure formed on a silicon substrate 52 and having a barium (or strontium) titanate layer 60 and a gallium arsenide layer 66 , similar devices can be fabricated using other substrates, monocrystalline oxide layers and other compound semiconductor layers as described elsewhere in this disclosure.
FIG. 10 illustrates a semiconductor structure 72 in accordance with a further embodiment. Structure 72 includes a monocrystalline semiconductor substrate 74 such as a monocrystalline silicon wafer that includes a region 75 and a region 76. An electrical component schematically illustrated by the dashed line 78 is formed in region 75 using conventional silicon device processing techniques commonly used in the semiconductor industry. Using process steps similar to those described above, a monocrystalline oxide layer 80 and an intermediate amorphous silicon oxide layer 82 are formed overlying region 76 of substrate 74. A template layer 84 and subsequently a monocrystalline semiconductor layer 86 are formed overlying monocrystalline oxide layer 80. In accordance with a further embodiment, an additional monocrystalline oxide layer 88 is formed overlying layer 86 by process steps similar to those used to form layer 80, and an additional monocrystalline semiconductor layer 90 is formed overlying monocrystalline oxide layer 88 by process steps similar to those used to form layer 86. In accordance with one embodiment, at least one of layers 86 and 90 are formed from a compound semiconductor material. Layers 80 and 82 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
A semiconductor component generally indicated by a dashed line 92 is formed at least partially in monocrystalline semiconductor layer 86. In accordance with one embodiment, semiconductor component 92 may include a field effect transistor having a gate dielectric formed, in part, by monocrystalline oxide layer 88. In addition, monocrystalline semiconductor layer 90 can be used to implement the gate electrode of that field effect transistor. In accordance with one embodiment, monocrystalline semiconductor layer 86 is formed from a group III-V compound and semiconductor component 92 is a radio frequency amplifier that takes advantage of the high mobility characteristic of group III-V component materials. In accordance with yet a further embodiment, an electrical interconnection schematically illustrated by the line 94 electrically interconnects component 78 and component 92. Structure 72 thus integrates components that take advantage of the unique properties of the two monocrystalline semiconductor materials .
Attention is now directed to a method for forming exemplary portions of illustrative composite semiconductor structures or composite integrated circuits like 50 or 72. In particular, the illustrative composite semiconductor structure or integrated circuit 102 shown in FIGs. 6-10 includes a compound semiconductor portion 1022, a bipolar portion 1024, and a MOS portion 1026. In FIG. 11, a p-type doped, monocrystalline silicon' substrate 110 is provided having a compound semiconductor portion 1022, a bipolar portion 1024, and an MOS portion 1026. Within bipolar portion 1024, the monocrystalline silicon substrate 110 is doped to form an N+ buried region 1102. A lightly p-type doped epitaxial monocrystalline silicon layer 1104 is then formed over the buried region 1102 and the substrate 110. A doping step is then performed to create a lightly n-type doped drift region 1117 above the N+ buried region 1102. The doping step converts the dopant type of the lightly p-type epitaxial layer within a section of the bipolar region 1024 to a lightly n-type monocrystalline silicon region. A field isolation region 1106 is then formed between the bipolar portion 1024 and the MOS portion 1026. A gate dielectric layer 1110 is formed over a portion of the epitaxial layer 1104 within MOS portion 1026, and the gate electrode 1112 is then formed over the gate dielectric layer 1110. Sidewall spacers 1115 are formed along vertical sides of the gate electrode 1112 and gate dielectric layer 1110.
A p-type dopant is introduced into the drift region 1117 to form an active or intrinsic base region 1114. An n-type, deep collector region 1108 is then formed within the bipolar portion 1024 to allow electrical connection to the buried region 1102. Selective n-type doping is performed to form N+ doped region s 1116 and the emitter region 1120. N+ doped r egions 1116 are formed within layer 1104 along adjacent sides of the gate electrode 1112 and are source, drain, or source/drain regions for the MOS transistor. The N+ doped regions 1116 and emitter region 1120 have a doping concentration of at least 1E19 atoms per cubic centimeter to allow ohmic contacts to be formed. A p-type doped region is formed to create the inactive or extrinsic base region 1118 which is a P+ doped region (doping concentration of at least 1E19 atoms per cubic centimeter) .
In the embodiment described, several processing steps have been performed but are not illustrated or further described, such as the formation of well regions, threshold adjusting implants, channel punchthrough prevention implants, field punchthrough prevention implants, as well as a variety of masking layers. The formation of the device up to this point in the process is performed using conventional steps. As illustrated, a standard N- channel MOS transistor has been formed within the MOS region 1026, and a vertical NPN bipolar transistor has been formed within the bipolar portion 1024. As of this point, no circuitry has been formed within the compound semiconductor portion 1022.
All of the layers that have been formed during the processing of the bipolar and MOS portions of the integrated circuit are now removed from the surface of compound semiconductor portion 1022. A bare silicon surface is thus provided for the subsequent processing of this portion, for example in the manner set forth above. An accommodating buffer layer 124 is then formed over the substrate 110 as illustrated in FIG. 12. The accommodating' buffer layer will form as a monocrystalline layer over the properly prepared (i.e., having the appropriate template layer) bare silicon surface in portion 1022. The portion of layer 124 that forms over portions 1024 and 1026, however, may be polycrystalline or amorphous because it is formed over a material that is not monocrystalline, and therefore, does not nucleate monocrystalline growth. The accommodating buffer layer 124 typically is a monocrystalline metal oxide or nitride layer and typically has a thickness in a range of approximately 2-100 nanometers. In one particular embodiment, the accommodating buffer layer is approximately 5-15 nm thick. During the formation of the accommodating buffer layer, an amorphous intermediate layer 122 is formed along the uppermost silicon surfaces of the integrated circuit 102. This amorphous intermediate layer 122 typically includes an oxide of silicon and has a thickness and range of approximately 1-5 nm. In one particular embodiment, the thickness is approximately 2 nm. Following the formation of the accommodating buffer layer 124 and the amorphous intermediate layer 122, a template layer 126 is then formed and has a thickness in a range of approximately one to ten monolayers of a material . In one particular embodiment, the material includes titanium- arsenic, strontium-oxygen-arsenic, or other similar materials as previously described with respect to FIGS. 1-5. Layers 122 and 124 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer.
A monocrystalline compound semiconductor layer 132 is then epitaxially grown overlying the monocrystalline portion of accommodating buffer layer 124 (or over the amorphous accommodating layer if the annealing process described above has been carried out) as shown in FIG. 13. The portion of layer 132 that is grown over portions of layer 124 that are not monocrystalline may be polycrystalline or amorphous. The monocrystalline compound semiconductor layer can be formed by a number of methods and typically includes a material such as gallium arsenide, aluminum gallium arsenide, indium phosphide, or other compound semiconductor materials as previously mentioned. The thickness of the layer is in a range of approximately 1-5,000 nm, and more preferably 100-500 nm. In this particular embodiment, each of the elements within the template layer are also present in the accommodating buffer layer 124, the monocrystalline compound semiconductor material 132, or both. Therefore, the delineation between the template layer 126 and its two immediately adjacent layers disappears during processing. Therefore, when a transmission electron microscopy (TEM) photograph is taken, an interface between the accommodating buffer layer 124 and the monocrystalline compound semiconductor layer 132 is seen.
At this point in time, sections of the compound semiconductor layer 132 and the accommodating buffer layer 124 (or of the amorphous accommodating layer if the annealing process described above has been carried out) are removed from portions overlying the bipolar portion 1024 and the MOS portion 1026 as shown in FIG. 14. After the section is removed, an insulating layer 142 is then formed over the substrate 110. The insulating layer 142 can include a number of materials such as oxides, nitrides, oxynitrides, low-k dielectrics, or the like. As used herein, low-k is a material having a dielectric constant no higher than approximately 3.5. After the insulating layer 142 has been deposited, it is then polished, removing portions of the insulating layer 142 that overlie monocrystalline compound semiconductor layer 132.
A transistor 144 is then formed within the monocrystalline compound semiconductor portion 1022. A gate electrode 148 is then formed on the monocrystalline compound semiconductor layer 132. Doped regions 146 are then formed within the monocrystalline compound semiconductor layer 132. In this embodiment, the transistor 144 is a metal-semiconductor field-effect transistor -(MESFET) . If the MESFET is an n-type MESFET, the doped regions 146 and monocrystalline compound semiconductor layer 132 are also n-type doped. If a p-type MESFET were to be formed, then the doped regions 146 and monocrystalline compound semiconductor layer 132 would have just the opposite doping type. The heavier doped (N+) regions 146 all ow ohmic contacts to be made to the monocrystalline compound semiconductor layer 132. At this point in time, the active devices within the integrated circuit have been formed. This particular embodiment includes an n-type
MESFET, a vertical NPN bipolar transistor, and a planar n-channel MOS transistor. Many other types of transistors, including P- channel MOS transistors, p-type vertical bipolar transistors, p- type MESFETs, and combinations of vertical and planar transistors, can be used. Also, other electrical components, such as resistors, capacitors, diodes, and the like, may be formed in one or more of the portions 1022, 1024, and 1026.
Processing continues to form a substantially completed integrated circuit 102 as illustrated in FIG. 15. An insulating layer 152 is formed over the substrate 110. The insulating layer 152 may include an etch-stop or polish-stop region that is not illustrated in FIG. 15. A second insulating layer 154 is then formed over the first insulating layer 152. Portions of layers 154, 152, 142, 124, and 122 are removed to define contact openings where the devices are to be interconnected. Interconnect trenches are formed within insulating layer 154 to provide the lateral connections between the contacts. As illustrated in FIG. 15, interconnect 1562 connects a source or drain region of the n-type MESFET within portion 1022 to the deep collector region 1108 of the NPN transistor within the bipolar portion 1024. The emitter region 1120 of the NPN transistor is connected to one of the doped regions 1116 of the n-channel MOS transistor within the MOS portion 1026. The other doped region 1116 is electrically connected to other portions of the integrated circuit that are not shown.
A passivation layer 156 is formed over the interconnects 1562, 1564, and 1566 and insulating layer 154. Other electrical connections are made to the transistors as illustrated as well as to other electrical or electronic components within the integrated circuit 102 but. are not illustrated in the FIGs. Further, additional insulating layers and interconnects may be formed as necessary to form the proper interconnections .between the various components within the integrated circuit 102. As can be seen from the previous embodiment, active devices for both compound semiconductor and Group IV semiconductor materials can be integrated into a single integrated circuit. Because there is some difficulty in incorporating both bipolar transistors and MOS transistors within a same integrated circuit, it may be possible to move some of the components within bipolar portion into the compound semiconductor portion 1022 or the MOS portion 1024. Therefore, the requirement of special fabricating steps solely used for making a bipolar transistor can be eliminated. Therefore, there would only be a compound semiconductor portion and a MOS portion to the integrated circuit .
In still another embodiment, an integrated circuit can be formed such that it includes an optical laser in a compound semiconductor portion and an optical interconnect (waveguide) to a MOS transistor within a Group IV semiconductor region of the same integrated circuit. FIGs. 16-22 include illustrations of one embodiment .
FIG. 16 includes an illustration of a cross-section view of a portion of an integrated circuit 160 that includes a monocrystalline silicon wafer 161. An amorphous intermediate layer 162 and an accommodating buffer layer 164, similar to those previously described, have been formed over wafer 161. Layers 162 and 164 may be subject to an annealing process as described above in connection with FIG. 3 to form a single amorphous accommodating layer. In this specific embodiment, the layers needed to form the optical laser will be formed first, followed by the layers needed for the MOS transistor. In FIG. 16, the lower mirror layer 166 includes alternating layers of compound semiconductor materials. For example, the first, third, and fifth films within the optical laser may include a material such as gallium arsenide, and the second, fourth, and sixth films within the lower mirror layer 166 may include aluminum gallium arsenide or vice versa. Layer 168 includes the active region that will be used for photon generation. Upper mirror layer 170 is formed in a similar manner to the lower mirror layer 166 and includes alternating films of compound semiconductor materials. In one particular embodiment, the upper mirror layer 170 may be p-type doped compound semiconductor materials, and the lower mirror layer 166 may be n- type doped compound semiconductor materials.
Another accommodating buffer layer 172, similar to the accommodating buffer layer 164, is formed over the upper mirror layer 170. In an alternative embodiment, the accommodating buffer layers 164 and 172 may include different materials. However, their function is essentially the same in that each is used for making a transition between a compound semiconductor layer and a monocrystalline Group IV semiconductor layer. Layer 172 may be subject to an annealing process as described above in connection with FIG. 3 to form an amorphous accommodating layer. A monocrystalline Group IV semiconductor layer 174 is formed over the accommodating buffer layer 172. In one particular embodiment, the monocrystalline Group IV semiconductor layer 174 includes germanium, silicon germanium, silicon germanium carbide, or the like.
In FIG. 17, the MOS portion is processed to form electrical components within this upper monocrystalline Group IV semiconductor layer 174. As illustrated in FIG. 17, a field isolation region 171 is formed from a portion of layer 174. A gate dielectric layer 173 is formed over the layer 174, and a gate electrode 175 is formed over the gate dielectric layer 173. Doped regions 177 are source, drain, or source/drain regions for the transistor 181, as shown. Sidewall spacers 179 are formed adjacent to the vertical sides of the gate electrode 175. Other components can be made within at least a part of layer 174. These other components include other transistors (n-channel or p- channel) , capacitors, transistors, diodes, and the like. A monocrystalline Group IV semiconductor layer is epitaxially grown over one of the doped regions 177. An upper portion 184 is P+ doped, and a lower portion 182 remains substantially intrinsic (undoped) as illustrated in FIG. 17. The layer can be formed using a selective epitaxial process . In one embodiment, an insulating layer (not shown) is formed over the transistor 181 and- the field isolation region 171. The insulating layer is patterned to define an opening that exposes one of the doped regions 177. At least initially, the selective epitaxial layer is formed without dopants. The entire selective epitaxial layer may be intrinsic, or a p-type dopant can be added near the end of the formation of the selective epitaxial layer. If the selective epitaxial layer is intrinsic, as formed, a doping step may be formed by implantation or by furnace doping. Regardless how the P+ upper portion 184 is formed, the insulating layer is then removed to form the resulting structure shown in FIG. 17. The next set of steps is performed to define the optical laser 180 as illustrated in FIG. 18. The field isolation region 171 and the accommodating buffer layer 172 are removed over the compound semiconductor portion of the integrated circuit. Additional steps are performed to define the upper mirror layer 170 and active layer 168 of the optical laser 180. The sides of the upper mirror layer 170 and active layer 168 are substantially coterminous .
Contacts 186 and 188 are formed for making electrical contact to the upper mirror layer 170 and the lower mirror layer 166, respectively, as shown in FIG. 18. Contact 186 has an annular shape to allow light (photons) to pass out of the upper mirror layer 170 into a subsequently formed optical waveguide. An insulating layer 190 is then formed and patterned to define optical openings extending to the contact layer 186 and one of the doped regions 177 as shown in FIG. 19. The insulating material can be any number of different materials, including an oxide, nitride, oxynitride, low-k dielectric, or any combination thereof. After defining the openings 192, a higher refractive index material 202 is then formed within the openings to fill them and to deposit the layer over the insulating layer 190 as illustrated in FIG. 20. With respect to the higher refractive index material 202, "higher" is in relation to the material of the insulating layer 190 (i.e., material 202 has a higher refractive index compared to the insulating layer 190) . Optionally, a relatively thin lower refractive index film (not shown) could be formed before forming the higher refractive index material 202. A hard mask layer 204 is then formed over the high refractive index layer 202. Portions of the hard mask layer 204, and high refractive index layer 202 are removed from portions overlying the opening and to areas closer to the sides of FIG. 15.
The balance of the formation of the optical waveguide, which is an optical interconnect, is completed as illustrated in FIG. 21. A deposition procedure (possibly a dep-etch process) is performed to effectively create sidewalls sections 212. In this embodiment, the sidewall sections 212 are made of the same material as material 202. The hard mask layer 204 is then removed, and a low refractive index layer 214 (low relative to material 202 and layer 212) is formed over the higher refractive index material 212 and 202 and exposed portions of the insulating layer 190. The dash lines in FIG. 21 illustrate the border between the high refractive index materials 202 and 212. This designation is used to identify that both are made of the same material but are formed at different times .
Processing is continued to form a substantially completed integrated circuit as illustrated in FIG. 22. A passivation layer 220 is then formed over the optical laser 180 and MOSFET transistor 181. Although not shown, other electrical or optical connections are made to the components within the integrated circuit but are not illustrated in FIG. 22. These interconnects can include other optical waveguides or may include metallic interconnects .
In other embodiments, other types of lasers can be formed. For example, another type of laser can emit light (photons) horizontally instead of vertically. If light is emitted horizontally, the MOSFET transistor could be formed within the substrate 161, and the optical waveguide would be reconfigured, so that the laser is properly coupled (optically connected) to the transistor. In one specific embodiment, the optical waveguide can include at least a portion of the accommodating buffer layer. Other configurations are possible.
Clearly, these embodiments of integrated circuits having compound semiconductor portions and Group IV semiconductor portions, are meant to illustrate what can be done and are not intended to be exhaustive of all possibilities or to limit what can be done. There is a multiplicity of other possible combinations and embodiments. For example, the compound semiconductor portion may include light emitting diodes, photodetectors, diodes, or the like, and the Group IV semiconductor can include digital logic, memory arrays, and most structures that can be formed in conventional MOS integrated circuits. By using what is shown and described herein, it is now simpler to integrate devices that work better in compound semiconductor materials with other components that work better in Group IV semiconductor materials. This allows a device to be shrunk, the manufacturing costs to decrease, and yield and reliability to increase. Although not illustrated, a monocrystalline Group IV wafer can be used in forming only compound semiconductor electrical components over the wafer. In this manner, the wafer is essentially a "handle" wafer used during the fabrication of the compound semiconductor electrical components within a monocrystalline compound semiconductor layer overlying the wafer. Therefore, electrical components can be formed within III-V or II- VI semiconductor materials over a wafer of at least approximately 200 millimeters in diameter and possibly at least approximately 300 millimeters. By the use of this type of substrate, a relatively inexpensive "handle" wafer overcomes the fragile nature of the compound semiconductor wafers by placing them over a relatively more durable and easy to fabricate base material. Therefore, an integrated circuit can be formed such that all electrical components, and particularly all active electronic devices, can be formed within the compound semiconductor material even though the substrate itself may include a Group IV semiconductor material. Fabrication costs for compound semiconductor devices should decrease because larger substrates can be processed more economically and more readily, compared to the relatively smaller and more fragile, conventional compound semiconductor wafers.
The present invention includes a contactless smartcard 250 that is capable of generating output, in a format that can be comprehended by a user, in response to manipulation of the data that is stored on an embedded microchip.
The integrated circuits (ICs) that are provided in currently available smartcards are typically formed from silicon wafers. While ICs that are formed from silicon and other such monocrystalline semiconductors readily generate thermal energy, a significant amount of externally supplied power would have to be supplied to allow such devices to generate optical output. In fact, the amount of power that would have to be supplied to enable an IC formed from a monocrystalline substrate to generate optical output exceeds that which can be efficiently supplied through RF transmission to a smartcard. Thus, a battery, or other power source that would significantly increase the size of the smartcard, would have to be supplied in order to enable the card to generate optical output . While monocrystalline semiconductors readily generate thermal energy, ICs that are formed from compound semiconductors, notably Group III-V compound semiconductors, can generate optical output without supplying external power. However, compound semiconductors are not used in smartcards because it is very expensive to form ICs from compound semiconductor wafers.
According to the present invention, a device structure 50, such as that described above with reference to FIG. 9, can be used to combine monocrystalline semiconductors and compound semiconductors in a single IC, and thereby provide inexpensive electrical components that generate optical output.
Turning now to FIG. 23, smartcard 250 incorporates the device structure 50 previously illustrated in FIG. 9. As shown, smartcard 250 includes an electronic chip 240 with electronic circuitry 256, which is embedded in region 253 of monocrystalline substrate 252. Electronic chip 240 includes an accommodating layer 260 and a compound semi-conductor layer 266. Accommodating layer 260 is positioned between substrate 252 and compound semiconductor layer 266. As described earlier, accommodating layer 260 may include a monocrystalline accommodating buffer layer, a monocrystalline accommodating buffer layer with an amorphous intermediate or interface layer, or an amorphous layer formed by annealing layers.
In accordance with the invention, chip 240 also includes an indicator 268, which is configured to generate output in response to receipt, transmission, storage, processing or other manipulation of the electronic data that is stored on and/or processed by circuitry 256 on electronic chip 240. As shown, indicator 268 is formed in compound semi-conductor layer 266 and is electrically coupled to circuitry 256 via conductor 270. Electronic chip 240 may be configured to manipulate electronic data in response to communication between smartcard 250 and an externally located reader 200, such as that illustrated in FIG. 24. Reader 200 will often include a kiosk, terminal or other publicly accessible device. It may include a display screen 210 and/or an identifiable communications region 212, next to which smartcard 250 should be placed in order to communicate with chip reader 200.
In one embodiment of the invention, chip reader 200 is a smartcard reader, readily available in the art. In such an embodiment, smartcard 250 communicates with the smartcard reader while it is within a predetermined distance from communications region 212. Circuitry 256 manipulates stored electronic data in response to this communication, and indicator 268 generates output in response to the manipulation of this electronic data. In one such embodiment of the invention, indicator 268 generates visually readable output. This visually readable output is preferably optical output and it may be modulated optical output. Referring now to FIG. 25, indicator 268 may include an associated display device for displaying text, graphical, and/or pictorial data. Indicator 268 may, for example, include a display device such as a light emitting diode (LED) . Smartcards are currently being used to pay fares in public transportation systems. In such a case, a cardholder may pass a smartcard 250 near a reader 200 to have the appropriate fare deducted as he boards a bus or train. As the fare is deducted, indicator 268 may display a phrase on the face of the card that indicates that a fare has been received, or it may display a numerical value such as a dollar amount that has been paid and/or a dollar amount that remains on the user's card.
Smartcards 250 are also being used to access bank accounts and other financial information. In this case, stock symbols or other personalized data that pertains to the cardholder's financial holdings may be stored on circuitry 256. The cardholder may pass a smartcard 250 near a reader 200 to obtain, for example, a graph that displays the performance of one or more of her stock holdings over the course of a given period of time. Smartcards 250 may also be used to conduct banking transactions. Thus, a menu screen could be displayed on smartcard 250 when it is near reader 200 to present the cardholder with a list of transactions that could be conducted. In such an embodiment, the display could include a touch screen that allows the cardholder to customize interactions with a reader 200 that is located, for example, in an automated teller machine that is connected to the bank's computer network. Thus, the cardholder could touch one portion of the screen to transfer funds between, for example, a checking account and a savings account, touch another portion of the screen to pay a credit card balance, and touch still another portion of the screen to purchase stocks or mutual funds. In each case, indicator 268 will preferably display text, graphics or pictorial data that will inform the cardholder that the appropriate transaction has taken place. As illustrated in FIG. 26, indicator 268 may include a light emitting diode (LED) , which may be located on the surface, edge, or other location on smartcard 250. Smartcard readers can usually only communicate with smartcards when they are inside a predetermined read field. If the card is inadvertently removed from this field, no data will be transferred. The embodiment of the invention shown in FIG. 26 may be most useful when the cardholder needs only to know that data is being communicated. Thus, a smartcard with an LED may be used to inform the cardholder that the card has been placed close enough to the reader to carry out the desired transaction.
In another embodiment of the invention, a smartcard 250 that includes LEDs may communicate with a reader 200 that has a very extensive range, to prevent the cardholder from venturing beyond a certain distance from the reader. While under such circumstances, it may not be necessary to pinpoint the cardholder's exact location, illumination (or termination of illumination) of the LED could warn the cardholder when he has wandered outside of the designated region. In still another embodiment of the invention, visually readable data may be generated by a printer, plotter or other device that is capable of visual communication without the use of optics. In such embodiments, a hard copy of the data may be provided on paper, plastic, cardstock or similar media. Turning now to FIG. 27, indicator 268 may also produce non- visual forms of output. In one embodiment of the invention, indicator 268 may generate an audible output in response to the manipulation of electronic data. Examples of such audible outputs include voice data as well as beeps, rings and other audible sounds. In one such embodiment, smartcard 250 may have a speaker that includes a transducer formed in compound semiconductor layer 266. In another embodiment, a circuit that generates such an audible output may be linked to electronic chip 240 via a photodiode, photodetector or other photoconductive device. In another embodiment of the invention, an example of which is illustrated in FIG. 28, an indicator 268 that causes at least a portion of the smartcard 250 to vibrate in response to the manipulation of electronic data on component 256 may be provided. These embodiments may include a piezoelectric device linked to an accommodating layer made, for example, from barium titanate or strontium barium titanate. These embodiments of the invention preferably also include an amplifier, which may enhance the ability to detect such vibration. It should be noted that indicator 268 may be capable of generating multiple types of data, and that a single smartcard 250 may generate visual as well as audible and/or vibration output.
Referring now to FIG. 29, in one embodiment of the invention a reader 200 is embedded in a portable device, such as another smartcard, and two or more smartcards 250 can communicate with each other. This other smartcard may be another smartcard 250 that incorporates the hybrid, monocrystalline semiconductor- compound semiconductor technology of device structure 50, or it may be a currently available smartcard with an electronic chip that is formed from a monocrystalline substrate, as illustrated in FIG. 23. According to these embodiments, smartcard 250 may engage in either bidirectional or unidirectional communication.
For example, a unidirectional communication embodiment of the invention may include a smartcard 250 that contains medical records. The data stored on such a smartcard 250 could be viewed, updated or otherwise manipulated by authorized medical personnel during visits to a doctor's office using the associated LED or other display such as those described above, or via a connected computer monitor or other large display. These records could then be transmitted to another smartcard to enable a cardholder to carry such information with him. Such a scheme would allow persons that are acutely ill or that otherwise need to provide fast and full access to their medical records to supply them to medical emergency personnel or to other persons that require such information. The emergency personnel could simply pass the cardholder's smartcard next to a reader in order to access, update or otherwise manipulate the information.
It should be noted here that in one embodiment of the invention, the smartcard that is transported by the cardholder in the above example could be a presently available smartcard that does not provide user comprehendible output . In such an embodiment, the authorized medical personnel that prepares the card may, for example, use smartcard 250 on which the medical records are stored to ensure that the appropriate data transfer has taken place. Similarly, the emergency or other personnel may confirm that a valid data transfer has taken place using reader 200 provided with smartcard 250 that is located in a first aid kit, ambulance, hospital emergency room or doctor's office. In another embodiment of the invention, the smartcard that is carried by the cardholder may also incorporate the technology of the present invention. Thus, it could provide some indication that data is communicated from one smartcard to another.
In one embodiment of the invention, communication from one smartcard 250 to another smartcard (either another smartcard 250 or a currently available smartcard) is accomplished via a laser output 274 from indicator 268, and in the preferred embodiment, the laser output is modulated.
Referring now to FIG. 30, in one embodiment of the invention, at least one activator 272 (e.g., a switch) is located on a surface of smartcard 250,' and is used to initiate communication between circuitry 256 and reader 200. Activators 272 will preferably be pressure sensitive contact points, but they may be any device that can trigger the communication of electronic data on demand by a cardholder. Thus, when activators 272 are provided, it may not be necessary to bring smartcard 250 next to electronic reader 200 to initiate data communication.
In one such embodiment of the invention, one or more LEDs 276, each of which is associated with an activator 272, may also be located on the surface of smartcard 250. In this embodiment, each activator 272 may initiate the communication of a different type of data. For example, when smartcard 250 is used to conduct banking activities, one activator 272 may cause a checking account balance to be displayed, while a second activator 272 is used to initiate the transfer of funds from a checking account to a savings account. Under such circumstances, the LED 276 that is adjacent to the respective activator 272 will preferably illuminate when the transaction takes place or as soon as it has been completed.
In another embodiment of the invention, a portable wallet in which smartcard 250 may be stored when the smartcard is not communicating with card reader 200 is provided. Such a wallet may be charged via a connection to a power supply. Thus, in addition to preventing circuitry 256 and indicator 268 from becoming damaged, the wallet can transmit additional energy to smartcard 250 while the card is not being used. This additional energy can then be stored in the smartcard for later use.
While the present invention has been described in conjunction with contactless smartcards 250, those skilled in the art will recognize that it could be adapted for use in a smartcard that requires physical contact between the card and reader 200 in order to communicate. Those skilled in the art will also appreciate that the present invention could be used in devices other than smartcards, in which it is desired to cause circuitry 256 to communicate with an electronic chip reader.
Further, while device structure 50 of FIG. 9 has been used to describe these embodiments of the invention, it will be appreciated that other embodiments may include additional semiconductor and oxide layers as illustrated in FIG. 10. It is intended to embrace all such alternative embodiments, and not to limit the invention to those embodiments of the invention that have been described here. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

Claims

What Is Claimed Is:
1. A smartcard capable of generating user comprehendible output, comprising: electronic circuitry embedded in a monocrystalline substrate and configured to manipulate electronic data in response to communication with an electronic chip reader; an accommodating layer positioned between said monocrystalline substrate and a compound semi-conductor layer; and an indicator embedded in said compound semi-conductor layer and electrically coupled to said electronic circuitry, wherein said indicator is configured to generate output in response to manipulation of said electronic data.
2. A smartcard as claimed in claim 1 wherein said indicator is configured to generate audible output in response to said electronic data manipulation.
3. A smartcard as claimed in claim 1 wherein said indicator is configured to cause vibration of at least a portion of the smartcard in response to said electronic data manipulation.
4. A smartcard as claimed in claim 1 wherein said indicator is configured to generate visually readable output in response to said electronic data manipulation.
5. A smartcard as claimed in claim 1 wherein the indicator includes an optical data generator embedded in said compound semi-conductor layer and electrically coupled to said electronic circuitry, wherein said optical data generator produces optical output in response to communication with the electronic chip reader.
6. A smartcard as claimed in claim 5 wherein said optical data generator includes a display and said optical output is produced on said display.
7. A smartcard as claimed in claim 5 wherein said optical output includes a laser output .
8. A smartcard as claimed in claim 5 wherein said optical output includes illumination of a light emitting diode on a surface of the smartcard.
9. A smartcard as claimed in claim 5 wherein said optical data generator produces modulated optical output in response to manipulation of said electronic data.
10. A smartcard as claimed in claim 1 or 5 wherein the monocrystalline substrate includes silicon.
11. A smartcard as claimed in claim 1 or 10 wherein the compound semiconductor layer includes gallium and arsenide.
PCT/US2001/017043 2000-06-30 2001-05-24 Electronically manipulated smartcard generating user comprehendible output WO2002003320A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667088A (en) * 1981-11-02 1987-05-19 Kramer Kane N Portable data processing and storage system
US4868376A (en) * 1987-05-15 1989-09-19 Smartcard International Inc. Intelligent portable interactive personal data system
US5442561A (en) * 1992-05-12 1995-08-15 Nippon Telegraph And Telephone Corporation Production management system and its application method
US5880452A (en) * 1990-11-15 1999-03-09 Geo Labs, Inc. Laser based PCMCIA data collection system with automatic triggering for portable applications and method of use

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667088A (en) * 1981-11-02 1987-05-19 Kramer Kane N Portable data processing and storage system
US4868376A (en) * 1987-05-15 1989-09-19 Smartcard International Inc. Intelligent portable interactive personal data system
US5880452A (en) * 1990-11-15 1999-03-09 Geo Labs, Inc. Laser based PCMCIA data collection system with automatic triggering for portable applications and method of use
US5442561A (en) * 1992-05-12 1995-08-15 Nippon Telegraph And Telephone Corporation Production management system and its application method

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