WO2002017586A1

WO2002017586A1 - Multicarrier transmitter circuit arrangement with predistortion linearisation method

Info

Publication number: WO2002017586A1
Application number: PCT/EP2000/008096
Authority: WO
Inventors: Samu Saarinen; Olli Tapio; Teemu Tolonen
Original assignee: Nokia Corporation
Priority date: 2000-08-18
Filing date: 2000-08-18
Publication date: 2002-02-28
Also published as: AU2000274105A1

Abstract

The present invention relates to a multicarrier circuit arrangement and a method for linearising a multicarrier circuit arrangement in which frequency channels are combined by using a complex mixing operation to generate a single composite complex signal, so as to achieve a complex channel separation. A predistorted complex signal is then generated by applying a complex predistortion to said complex signal. Thereby, an efficient linearisation of wideband multicarrier circuit arrangements can be achieved, since the bandwidth requirements of digital predistortion are relaxed by enabling a baseband predistortion of multicarrier signals. Furthermore, combining different frequency chan-nels at digital baseband domain makes it possible to use only one transmit chain, which means considerable reduction in the needed amount of digital/analogue components. Fore-mentioned can also be applied to feedback chain, i.e. all the frequency channels can be down-converted to predis-torter for calculation of new predistortion coefficients with only one down-conversion chain. Only one baseband pre-distorter is needed to linearise all the transmitted infor-mation because of complex channel separation. All of the intelligence and adaptivity in the proposed system is lo-cated in the digital domain, thereby enabling stable and accurate control of the transmitted signal in every operat-ing conditions.

Description

Multicarrier transmitter circuit arrangement with predistortion linearisation method

FIELD OF THE INVENTION

The present invention relates to a multicarrier circuit arrangement, such as a multicarrier or dual-carrier transmit- ter, and a method for linearizing such a multicarrier circuit arrangement in which a complex multicarrier signal is processed.

BACKGROUND OF THE INVENTION

Multicarrier or dual-carrier transmitter circuit arrangements have been proposed for base station or equivalent applications of mobile communication systems, such as WCDMA (Wideband Code Division Multiple Access) or GSM EDGE

(Global System for Mobile communications - Enhanced Data rates for GSM Evolution) systems. There is a trade-off between carrier spacing and adjacent channel interference requirements. Adjacent frequency bands interfere with each other due to the imperfection of power amplifiers and receiver filters. Imperfect transceivers induce out-off-band power in adjacent bands. The ACLR (Adjacent Carrier Leakage Ratio) quantifies the transceiver out-off-band transmitted power. The selectivity of the receiver filter is not infi- nite in the adjacent band. Thus, the power of adjacent bands that cannot be suppressed becomes interference. The ACS (Adjacent Carrier Selectivity) represents the capability to separate adjacent channels. Tight spectrum mask requirements for a transmitter and high selectivity require- ments for a receiver would guarantee low adjacent channel interference. However, these unrealistic requirements would have a detrimental impact on multicarrier circuit arrangements such as base stations or mobile stations of a cellular network. The source of imperfections in ACLR is mainly the non-linear properties of the power amplifier, as can be gathered from S-W. Chen, "Nonlinear Distortion in Digital Wireless Communications", Wireless Communication Conference, pp 20-26, August 1996. Strict linearity (ACLR, EVM, Peak Code domain error etc.) requirements have direct i - pact on the efficiency of the power amplifier and, therefore, on the cost of the multicarrier circuit arrangement.

A power amplifier with high power efficiency and low nonlinear distortion is a key requirement for linear odula- tion to be feasible in mobile radio communications. Many efforts on non-linearity compensation methods had been devoted to power-efficient amplifiers. Non-linearity compensated amplifiers can be classified into feedback, predistortion, and feed-forward amplifiers.

The feedback technique is well-known for non-linear compensation in power amplifiers, especially for audio amplifiers. However, feedback control at RF-frequencies becomes difficult because of the feedback circuit implementation. A linearized multicarrier power amplifier has been proposed which utilizes Cartesian feedback. Nevertheless, this technique is not applicable to transmitters of third generation mobile communication systems due to its rather narrow band nature.

Regarding the linearization of very wide-band applications, such as WCDMA (Wideband Code Division Multiple Access) , feed-forward is most commonly used at the moment. In a feed-forward amplifier, the distortion or error signal pro- duced in the amplifier is detected by comparing the input and output signals. The detected error signals are fed into a linear sub-amplifier to amplify them to the same level as that of the power amplifier. The amplified error signal is then subtracted from the output of the power amplifier. The adjustment of the delay time and gain in the second path is important for the success of the feed-forward amplifier. The linearity of the sub-amplifier must be high. However, this can decrease the overall power efficiency.

In a predistorter amplifier, the predistorter adds a pre- distorting signal to the input signal in advance to cancel the distortion generated in the amplifiers. The advantage of the predistorted amplifier is that, in principle, it is free from the instability problem, since it belongs to an open-loop control. However, the compensating performance degrades if the amplifier parameters deviate from the preset values. In order to resolve this disadvantage, an adaptive control method has been proposed by Yoshinori Nagata in "Linear Amplification Technique for Digital Mobile Com- munications", Proc. IEEE Vehicular Technology Conference, pp 159-164, 1989. A feedback path is introduced to detect the error and to automatically correct the predistorter. The predistorter is composed of iterative adaptation algorithm functionalities, memories which store predistortion coefficients and circuitry which inserts predistortion information to original signal at baseband frequency. The output of the power amplifier is demodulated and compared with the input signal to produce an error signal. The error signal is fed to the adaptation algorithm, which uses this error signal and old predistortion coefficient to determine updated predistortion coefficient. Thus, the predistorter is adaptive to the change in the characteristics of the power amplifier. The correction algorithm is based on an iterative method, for example as proposed in J. K. Cavers, "A Linearising Predistorter with Fast Adaptation", Proc. IEEE Vehicular Technology Conference, pp 41-47, May 1990.

However, in the case of wide-band multicarrier applica- tions, a large bandwidth is required for the predistortion processing, which leads to complex circuit arrangements. This might mean, for example, increased complexity or rep- lication in the up-conversion and down-conversion chains because several carriers has to be processed. Furthermore, several predistortion functionalities might be needed if each individual carrier is processed separately.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a multicarrier circuit arrangement with predistortion linearisation, by means of which the adjacent channel leakage power can be suppressed to an acceptable level, while keeping the circuitry simple.

This object is achieved by a method for linearizing a multicarrier circuit arrangement in which different frequency channel signals are processed, said method comprising the steps of: combining said frequency channel signals by using a complex mixing operation to generate a composite complex signal, so as to achieve a complex channel separation; and generating a predistorted complex signal by applying predistortion to said composite complex signal.

Additionally, the above object is achieved by a multicarrier circuit arrangement for processing different frequency channel signals, said multicarrier circuit arrangement cόm- prising: complex channel separating means for combining said frequency channel signals by using a complex mixing operation to generate a composite complex signal, so as to achieve a complex channel separation; and predistorting means for applying predistortion to said composite complex signal so as to generate a predistorted composite complex signal.

Accordingly, the usage of the complex channel separation provides the advantage that the predistortion can be performed for a single composite complex signal, such that a subsequent up-conversion can be made with only one up- conversion chain. Furthermore, the linearization can be achieved by simply combining the complex signal with com- plex predistortion coefficients. Thus, no channelizers are required in the feedback path to separate the carriers in order to perform predistortion individually for each of the carriers. Furthermore, the bandwidths requirements of the predistortion are relaxed, since a baseband predistortion of the multicarrier signals can be performed. In particular, if a multicarrier signal can be provided in an IQ- form, the predistortion bandwidth is halved, compared to the case of predistorting a real bandpass multicarrier signal in the intermediate frequency range.

The predistortion values may be calculated adaptively by comparing said complex signal with a feedback complex signal coupled from the output of said multicarrier circuit arrangement.

Preferably, the multicarrier circuit arrangement may be a dual-carrier transmitter, wherein the predistorted complex signal is converted to a real bandpass signal by a quadrature modulator. In this case, the conversion can be per- formed by using a single analogue or digital quadrature modulator. Thus, a direct-conversion architecture can be provided where the baseband signal is directly modulated to radio frequency with a single analog or digital quadrature modulator. The digital conversion could be performed by us- ing a DDS carrier generation scheme. This means that the modulation and up-conversion procedures are embedded together, contrary to a superheterodyne architecture. Due to the simplicity and low costs of such an architecture, it is an attractive choice for enabling the integration of many transmitter functions.

Alternatively, the complex signal could be first up-converted with an IQ- odulator to an intermediate frequency, and then with a mixer to a final radio frequency. With such a scheme, no tight bandpass filter is needed like in superheterodyne transmitter.

The predistortion may be a two-dimensional digital predistortion operation, wherein a complex predistortion coeffi- cient is added to the complex signal. Preferably, the two- dimensional digital predistortion may be performed by using the complex signal so as to address a memory storing said complex predistortion coefficient. The predistortion may be a two-dimensional mapping operation using a two-dimensional interpolation. With such a predistortion, non-idealities of the analog quadrature modulator are also compensated, such that the usage of a direct conversion scheme becomes even more interesting. By using the two-dimensional interpolation (cf. I. Wolff & Q. Ren: improvement of Digital Map- ping Predistorters for Linearising Transmitters, IEEE,

1997) inside a memory table, the table size can be reduced. The two-dimensional mapping operation may employ Cartesian components of the complex signal by which two-dimensional predistortion tables are addressed. A first component of the complex signal may be an in-phase signal and a second component may be a quadrature-phase signal.

The predistortion may be a three-dimensional mapping predistortion, wherein the components of the complex signal and an instantaneous frequency value of the input signal are all used to address a memory. By using the instantaneous frequency as an extra parameter, frequency dependent distortions may also be compensated.

The composite complex signal may be generated in dual- carrier case according to the following equation:

s_BB(t) = sι(t) • e ^ωlt + s₂(t) • e-Jωit,

wherein s]_(t) denotes a first complex modulated baseband carrier signal, S2(t) denotes a second complex modulated baseband signal, G>I denotes an intermediate frequency, and Sβ (t) denotes the composite complex signal.

Furthermore, the predistortion may be an adaptive predistortion adapted to time/frequency-, amplitude- and/or phase-properties of the multicarrier circuit arrangement by using a feedback loop. In this case, a complex sampling may be performed at an intermediate frequency in the feedback path to generate complex feedback signal. Furthermore, a feedback signal may be generated by performing a down-conversion of an output signal of the multicarrier circuit arrangement. Preferably, the adaptation of the predistortion operation may be based on a calculated error between a desired signal and a feedback signal obtained from the feedback loop. A new estimate for the complex predistortion coefficient may then be obtained on the basis of the calculated error. Thus, the predistortion can be made adaptive to the time/frequency, amplitude and/or phase variance properties of the multicarrier circuit arrangement with a discontinuous feedback loop, such that stability constraints can be relaxed.

Additionally, a phase adjustment between the forward branch and the feedback branch may be performed by feeding a portion of an I-channel of the feedback signal into a Q- channel thereof, and/or vice versa. The phase adjustment may be based on an estimation of the phase difference be- tween the complex signal and the feedback signal. Thereby, the phase estimation and adjustment can be made in the baseband digital domain with main-path and feedback chain signals in Cartesian form.

Furthermore, combining different frequency channels at digital baseband domain makes it possible to use only one transmit chain, which means considerable reduction in the needed amount of digital/analogue components. Forementioned can also be applied to feedback chain, i.e. all the fre- quency channels can be down-converted to predistorter for calculation of new predistortion coefficients with only one down-conversion chain.

Moreover, only one baseband predistorter is needed to line- arise all the transmitted information because of complex channel separation. Without complex channel separation, some kind of channelizer in the feedback chain would be needed to separate carriers before IQ -splitting of individual frequency channels. All of the intelligence and adaptivity in the proposed system is preferably located in the digital domain, thereby enabling stable and accurate control of the transmitted signal in every operating conditions. BRIEF DESCRIPTION OF THE DRAWINGS

In the following, the present invention will be described in greater detail with reference to the accompanying draw- ings, in which:

Fig. 1 shows a basic block diagram of a linearized multi- carrier circuit arrangement according to the present invention,

Fig. 2 shows a linearized dual-carrier direct up-conversion transmitter according to a preferred embodiment of the present invention,

Fig. 3 shows an implementation example of the complex channel separation unit of the preferred embodiment,

Fig. 4 shows a diagram indicating an output signal of the preferred embodiment after a modulation to RF,

Fig. 5 shows an implementation example of the adaptive pre- ,-, distortion unit of the preferred embodiment, and

Fig. 6 shows an implementation example of the phase rota- tion unit of the preferred embodiment.

DESCRIPTION OF A PREFERRED EMBODIMENT

The present invention will now be described on the basis of a preferred embodiment.

Fig. 1 shows a basic block diagram depicting the principle underlying the present invention. According to Fig. 1, different frequency channel signals from Chi to ChN, which may be baseband carriers in the form of complex signals having a bandwidth equal to the modulation bandwidth (3.84 MHz in WCDMA) and being centered at DC, are supplied from respective baseband hardware circuits 3-1 to 3-N, where they are generated and/or processed, to a complex channel separation unit 1 which generates a single complex signal comprising complex components, such as an I- component and a Q-component . The idea of complex channel separation is to combine the signals of the different channels or carriers so as to provide a single multicarrier signal in a complex form, such as a Cartesian or IQ-form comprising two components. The components of the initial separate signals are combined to the complex components I, Q of the- single complex signal in such a manner that they can be easily recovered at the receiving end. This may be achieved by suitable arithmetic processings which may be implemented by a digital or analog signal processing network.

In particular, the complex channel separation may be achieved by a complex mixing operation achieved e.g. by utilization of full-complex mixers, as described later.

The complex I- and Q-components are supplied to a predistortion unit 2 in which complex predistortion is achieved by combining the complex signal with a complex predistortion coefficient stored in a memory or look-up table (LUT) 6. The predistortion operation may be a complex mapping op- eration based on a summing of the complex predistortion coefficient and the complex signal, or a complex gain predistortion based on a multiplication of the complex signal with a complex gain coefficient stored in the LUT 6. After the predistortion operation, the components of the predistorted complex signal are supplied to a digital-to- analog converter (DAC) 3 which generates an analog complex signal and supplies the predistorted analog complex signal to an IQ-modulator 4 which converts the I- and Q-components to the RF-frequency range by mixing them with corresponding RF-signals and adding the converted components so as to obtain a final RF-output signal which is supplied to a nonlinear circuit 5, e.g. a power amplifier or mixer circuit or the like, which is to be linearized by the predistortion operation. The linearized output signal of the non-linear circuit 5 may be fed back to the predistortion unit 2 in order to achieve an adaptation of the predistortion unit 2 to the time/frequency-, amplitude- and/or phase-variance properties of the non-linear circuit 5.

In particular, the linearized RF-output signal is supplied to an IQ-demodulator 9 which performs a down-conversion to obtain demodulated I- and Q-components which are supplied to an analog-to-digital converter (ADC) 8 so as to be sampled and converted into a digital signal. The complex digital feedback signal is supplied to an update circuit 7 in which the complex digital feedback signal is compared to the complex input signal of the predistortion unit 2. The difference between the complex feedback signal and the complex input signal is supplied as a complex error signal to the LUT 6. Based on this complex error signal, the complex predistortion coefficients are updated in the LUT 6, such that new estimates for the predistortion complex coeffi- cients are iteratively obtained. The supply of the predistortion coefficient from the LUT 6 to the predistortion unit 2 is based on a complex addressing operation using the I- and Q-components of the complex input signal. The above-described circuit arrangement and operation enables a digital baseband predistortion for wideband dual- carrier signals. The above basic principle may as well be used for more than two carriers. An increase in the amount of carriers leads to increased processing requirements for the DAC 3 and the ADC 8, since a larger bandwidth is required in the predistortion procedure. In case of more than two input carriers or channels, a complex channel separation could be performed for every two input channels or carriers, while the complex channel-separated output signals may be predistorted in a successive or parallel manner. Alternatively, a suitable complex mixing operation could be performed for more than two channels, as long as a subsequent recovery of the original channel components can be assured.

Fig. 2 shows an implementation of the above basic principle in a dual-carrier direct up-conversion transmitter according to a preferred embodiment of the present invention, which may be used in a base transceiver station (BTS) of a mobile communication system.

According to Fig. 2, a first carrier comprising Cartesian components I_chl a d Q_c l is supplied via respective pulse shaping filters (PSF) 10, 11 and interpolation circuits 20, 21 to a complex channel separating unit 100. The same applies to Cartesian components I_c 2 ^anc* Qchl °f ^a second carrier, which are supplied to the complex channel separating unit 100 via respective pulse shaping filters 12, 13 and interpolation circuits 22, 23. The Cartesian components may comprise in-phase signals I_chl ^anc Ich2 ^anc quadrature- phase signals Q_chl ^anc Qch2 which are generated in digital baseband parts of the transmitter. The pulse shaping filters 10 to 13 are provided to optimize the bandwidth re- quirements, and the interpolation circuits 20 to 23 are provided to interpolate the digital signals by a factor N, using filters to filter out the images produced by the interpolation procedure. Interpolation can be performed by using e.g. interpolation filters such as halfband filters. If the interpolation ratio is 8, for example, then three halfband filters are needed.

The pulse-shaped and interpolated channel components are combined in the complex channel separating unit 100 by a complex mixing operation to generate a single complex signal which comprises an in-phase component I and a quadrature-phase component Q for both carriers. The complex mixing operation may be achieved by full complex mixer circuits as shown in Fig. 3. By using the complex channel separation, it is possible to reduce needed bandwidths and thus relax the sampling speed requirements in digital parts and essentially in the DA- and AD-converters.

Fig. 3 shows an architecture for generating two carriers in complex baseband. According to Fig. 3, the two digital complex baseband carriers or signals are denoted sj_. (n) and

S2 (n) and can be written as follows:

s_x ⁽n⁾ = I_chl⁽ⁿ⁾ + ^Qchl⁽ⁿ) (1)

s₂ ⁽n⁾ = I_c 2^{(n) +} J^Qch2⁽ⁿ⁾ (2)

These complex baseband signals sχ(n) and s₂ (n) are converted to a (complex) intermediate frequency of e.g. 2.5 MHz by corresponding mixing or multiplication operations with digital IF-frequency signals, wherein ωη_ denotes the angular velocity corresponding to the above intermediate frequency. The parameter n indicates the processing in the digital domain. The converted signal components of the re- spective baseband signals are added so as to generate com- plex mixing components s_BB^(n) and s_BB (n) which are added to the final complex channel separated signal s_BB(t) .

The up-conversion operation can be described by the follow- ing equations:

s_BB1(n) = S!(n)eJωin

= (I_chlcos(ωιn) - Q_chisin(ω!n) ) + j (Q_chlcos(ωιn) + I_chιsin (α>ιn) ) (3)

s_BB2(n) = s₂ (n)e^{~ ω}lⁿ

= (I_ch2^cos(^ωlⁿ) + Q_ch2^sin(^ωlⁿ) ) + (Q_ch2^C0S(ωιn) - I_c 2sin (ωin) ) (4)

Thus, the vectors of the two complex components s_BB^ (n) and ^SBB2 (ⁿ) rotate at the same angular velocity but in different directions.

In the analog domain, the components of the multicarrier (here dual-carrier) complex channel separated signal are given as follows:

I(t)=cos(a>it) [I_chl(t)+l_ch2(t)]+sin(a>ιt) [Q_ch2 (t) -Q_chl (t) ] (5)

Q (t) =sin (ω_xt) [I_chl (t) -l_ch2 (t) ] +cos (ω_xt) [Q_ch2 (t) +Q_chl (t) ] (6)

As can be gathered from the above equations (5) and (6), the individual Cartesian components of the original complex baseband signals can be recovered at a receiver by suitable signal combinations.

In the complex presentation, the complex channel separation signal s_BB(t) is given in the analog domain as follows: s_BB(t) = s₁(t)e ^ωl^t + s₂(t)e^{~ ω}l^t

Thus, according to the above architecture, two carriers are combined in the digital domain in complex baseband using complex channel separation. By this procedure, all DC- centered modulated carriers are shifted to different intermediate frequencies around DC. Thereby, the usage of lossy RF power combiners and separate transmit chains can be avoided. Secondly, when carriers are combined in complex baseband, requirements regarding needed bandwidth and sampling rate in the digital parts are relaxed. The complex channel separation can be implemented with two digital IQ- modulators having quadrature outputs, i.e. full-complex mixers. Four real multiplications and two summing operations are required. With this arrangement, single sideband frequency translation is performed and only one desired sideband is generated within an interval ranging from -fs 2 to fs/ , where f§ denotes the sampling frequency used in the digital circuitry. The IQ-modulator architecture with quadrature outputs can be implemented with a digital synthesis method, e.g. a DDS (Direct Digital Synthesis) or CORDIC algorithm. The CORDIC algorithm is described in „Methods of Mapping from Phase to Sine Amplitude in Direct Digital Synthesis" by J. Vankka, IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Vol. 44, No. 2, March 1997 and is effective in solutions where both in-phase and quadrature-phase components are needed simultaneously, since the CORDIC algorithm calculates both com- ponents simultaneously. Also, the implementation of a CORDIC block requires only basic arithmetic operations such as shifters, adders/subtractors, pipeline registers and the like, which are easy to implement in hardware. However, the circuit shown in Fig. 3 may as well be implemented by a signal processor based on a corresponding signal processing routine.

Fig. 4 shows the output signal of the dual-carrier direct up-conversion transmitter after the subsequent predistortion and up-conversion operation. In the present case, the two initial signals or carriers are directly up-converted to a 2.1 GHz carrier by means of an IQ-modulator 400. Thus, the centers of the two peaks shown in Fig. 4 are located at frequency values corresponding to the sum and difference between the RF-value (2.1 GHz) and the IF-value (2.5 MHz).

The direct conversion scheme provides the advantage of size reduction, simplicity and low power consumption, since the baseband signals are directly modulated to radio frequency with the single analog IQ-modulator 400. Thus the modulation and up-conversion procedures are embedded together, such that the transmitter functions can be integrated to a high degree, e.g. baseband parts can be implemented on an ASIC (Application-Specific Integrated Circuit) controlled with an appropriate controller or processor and the analog parts can be integrated to one or two RF ICs depending on the final architecture solution.

As shown in Fig. 2, the complex channel-separated signal components are supplied to a predistortion unit 200 to which complex predistortion coefficients are supplied from an adaptive memory 600 in which the complex predistortion parameters are stored and updated on the basis of a feed- back from the output of the dual-carrier transmitter. The adaptive memory 600 is addressed by the complex signal components supplied from the complex channel separation unit 100. Furthermore, the adaptation or updating of the complex predistortion coefficients is performed on the basis of a comparison between a complex feedback signal and a complex output signal of a delay circuit 701 in which the delay caused by the forward and feedback paths of the feedback loop is compensated. The delay provided by the delay circuit 701 is controlled by a control signal supplied from a delay estimation circuit 704 which is arranged to estimate the delay between the complex feedback signal and the complex output signal of the delay circuit 701 and to generate a control signal so as to control the delay circuit 701 to remove the delay. There are several ways to perform delay estimation by the delay estimation circuit 704. The delay circuit 701 provides an accurate adjustment of integer and fractional delay in order to ensure the adaptation to be correct, and may be implemented by any controllable digital delay circuitry such as a fractional delay filter means.

Fig. 5 shows an implementation example of the predistortion unit 200 and the adaptive memory 600. As shown in Fig. 5, the predistortion operation is a two-dimensional mapping predistortion operation wherein the linearization is achieved by adding a predistortion coefficient to the complex channel separated signal to thereby cancel or at least suppress the distortions at the output of a power amplifier 500 to which the RF-output signal is supplied. In other words, the predistortion unit 200 predistorts the incoming signal's complex envelope to the inverse of the non- linearity of the power amplifier 500. Due to the time/frequency-, amplitude- and/or phase-variance properties of the power amplifier 500, caused by load variations, aging, and temperature changes, the predistortion is made adaptive with a discontinuous feedback loop, which on the other hand relaxes the stability constraints experienced by other linearization schemes.

In particular, two two-dimensional LUTs 601 and 602 in which the quadrature component and the in-phase component, respectively, of the complex predistortion coefficients are stored are addressed by the complex input signal from the complex channel separation unit 100. The LUTs 601 and 602 contain complex predistortion coefficients, because the non-linearity of the power amplifier 500 has both amplitude and phase characteristics. The complex input signal S_BB(n) may be directly used as an address, since for every complex input signal combination (s_BB j, s_BB Q) there are corresponding complex predistortion coefficient values SR^M J and SR/^M Q- When memory compression techniques are used, a two-dimensional interpolation may be employed to determine the complex predistortion coefficent based on the current input complex signal value. The complex baseband signal S_BB(n) is predistorted simply by summing it with the re- spective complex predistortion value SR&M consisting of the Cartesian components SR^M Q and SRZAM I- Thus, the predistorted output signal at a time instant n is given as follows :

S_PD(n)= S_BB(n)+S_RAM(n) = [s_{BB f} ι+s_RAM/r J) +j (SBB,Q+SRAM,Q) (8)

The update procedure is performed by calculating the error between the desired signal, i.e. the complex input signal supplied from the complex channel separation unit 100, and the erroneous signal obtained as the down-converted complex feedback signal from the feedback loop. An adaptation means 610 is provided for the adaptation. There are various ways to perform the calculation of new predistortion coefficients, for example by using iterative adaptation algo- rithm.

As an example, the complex error signal is given as follows:

ε(n) = S_BB(n)-S_FB(n) = (s_BB, χ-s_{FB r τ} ) +j (s_BB/Q-s_FB/Q) (9) By using this error signal, a new estimate for the complex predistortion coefficient can be iteratively obtained based on the following equation:

S AM(n) ^{= s}RAM<ⁿ) + μ ^• ε(n) (10)

wherein the parameter μ indicates weighting of variable gain stages which may be arranged for amplifying the complex components εj(n) and SQ(Π) of the error signal ε(n) so as to achieve a desired signal level. The new estimate

S _RAj [ ( ) is obtained by adding the weighted error signal components μ • ε_j(n) and μ • εg{n) to old complex predistortion coefficient values

j and SR&M Q, respectively.

Thus, the complex predistortion coefficient stored in the two-dimensional LUTs 601 and 602 are successively updated and adapted to the time/frequency-, amplitude- and/or phase-variance characteristics of the power amplifier 500. The table size of the LUTs 601 and 602 can be reduced by using a two-dimensional interpolation inside the RAM- tables, as described e.g. in I. Wolff et al, "Improvement of Digital Mapping Predistorters for Linearizing Transmitters", IEEE, 1997.

Furthermore, the adaptation of the mapping predistortion can be enhanced by performing a three-dimensional mapping. This can be achieved by using the I- and Q-components of the complex input signal and an additional instantaneous frequency value for addressing the three-dimensional LUTs. By using this instantaneous frequency value as an extra parameter, frequency dependent distortions may be compensated as well. However, it is to be noted that any other additional parameter can be used as a third address dimension to thereby compensate a corresponding distortion dependency of the power amplifier 500 or the whole circuit arrangement .

Referring back to Fig. 2, the predistorted complex signal components I and Q are supplied via respective inverse sine circuits 251 and 252 and DACs 301 and 302 to respective reconstruction filters 351 and 352, such that predistorted analog signals I(t) and Q(t) which are supplied to the IQ- modulator 400 are generated. The inverse sine-circuits 251 and 252 are used to compensate distortions caused by the digital-to-analog operation of the DACs 301 and 302, and the reconstruction filters 351 and 352 are provided to remove any high frequency components generated in the digital-to-analog conversion operation.

A portion of the linearized RF-output signal of the power amplifier 500 is coupled to an IQ-demodulator 900 which demodulates the RF-quadrature signal so as to generate respective I- and Q-components which are supplied via respec- tive low-pass filters (LPFs) 851 and 852 to respective analog-to-digital converters (ADCs) 801 and 802.

In the mapping predistortion operation, the provision of same phases in the forward and feedback branches of the feedback loop is an important requirement. Therefore, a phase rotation unit 702 which is controlled by a phase estimation unit 703 are provided. According to the preferred embodiment, the phase adjustment is done in baseband by feeding a portion of the I-channel of the feedback signal into the Q-channel and/or vice versa.

Fig. 6 shows a principle diagram of an implementation of the phase rotation unit 702. In mapping predistortion, the same phase is required in forward and feedback branches. If the complex planes, in which the cartesian signal compo- nents used in the adaptation procedure are located, are phase-rotated, the linearisation procedure will be deteriorated. Therefore, the phase estimation unit 703 performs a phase estimation on the basis of a delayed complex channel separated signal obtained from the delay circuit 701, and the complex feedback signal. The phase estimation may be an angle estimation obtained from a CORDIC algorithm or with some trigonometric function provided in a digital signal processor's own function library. The CORDIC algorithm is an iterative algorithm for calculating many element functions, such as trigonometric functions. Since the algorithm is bit-recursive, more accuracy is obtained by each iteration. Since the CORDIC algorithm thus effectively implements coordinate transformation from cartesian to polar, the angle of the input complex vector sample can be easily calculated. In this vectoring mode, the algorithm forces the Q component of the complex vector to zero and accumulates the phase shifting during each iteration in an accumulator. After the iteration procedure, the phase of the complex vector can be read from the accumulator. The estimated angle ΦA,EST can thereby be calculated by taking the mean value from a large number of calculated phases in both forward and feedback paths. These two mean values are then subtracted from each other and the result is used as an in- p_Ut value for the phase rotation unit 702. The calculation of a new phase estimate can be performed as desired. The CORDIC algorithm can be implemented in a DSP (Digital Signal Processor) or by a hardware circuit.

The estimated angle ΦA,EST' ^as indicated in the upper complex diagram in Fig. 6, is supplied to the phase rotation unit 702. As the complex feedback signal is in the cartesian form and comprises the complex digital baseband feedback components I' (n) and Q' (n) , the phase rotation can be achieved by adding a predetermined portion of the in-phase component I' (n) to a predetermined portion of the quadrature-phase component Q' (n) , so as to obtain a corrected quadrature-phase component QcOR(ⁿ)- Furthermore, a predetermined portion of the quadrature-phase component Q¹ (n) is added to a predetermined portion of the in-phase component

I'(n), so as to obtain a corrected in-phase component ICOR(Π). The predetermined portions are obtained in a corresponding sine and cosine multiplier network, comprising multiplier circuits 712, 722, 732 and 742, where the prede- termined portions are obtained e.g. by multiplying the respective feedback component by a corresponding angle function of the estimated angle φ^ EST' ^{as can} ^^e gathered from the lower portion of Fig. 6. The processing performed in the phase rotation unit 702 leads to a rotation of the com- plex vectors I' and Q¹ so as to be matched with the phase angle of the delayed complex signal obtained from the delay circuit 701 in Fig. 2. The processing performed in the phase rotation units 702 may by achieved by corresponding digital signal processing circuits or by a single signal processor device.

Thus, the phases of the corrected complex feedback signal and the delayed complex input signal are adjusted to achieve a proper phase convergence required for the ap- ping-based linearization.

Accordingly, the linearization according to the preferred embodiment is performed by simply summing complex predistortion coefficients to complex baseband signals. Thus, no channelizers are required in the feedback path, only a direct down-conversion by the IQ-demodulator 900. Therefore, a high degree of integration of the preferred embodiment is possible, since the baseband parts can be implemented on an ASIC, while the analog parts can be integrated on one or two RF ICs. Generally, the present invention may be applied in multicarrier applications or in multimode transceivers of WCDMA-based transceiver stations or GSM EDGE systems. Furthermore, an implementation of the proposed linearized multicarrier direct conversion transmitter with a complex gain predistortion method is possible, wherein the mapping predistortion shown in Fig. 2 is replaced by a gain-predis- tortion. In this case, suitable complex gain coefficients are stored in the adaptive memory 600 so as to be multiplied with the channel separated complex input signal. How- ever, when such a complex gain predistortion, is used, a compensation of errors due to gain or phase imbalances of the analog IQ-modulator 400 and IQ-demodulator 900 might be necessary.

Furthermore, the forward- or transmit-path in Fig. 2 could be modified in such a manner that the up-conversion by the analog IQ-modulator 400 is only performed to an intermediate frequency, wherein an additional mixer circuit is provided to perform a subsequent up-conversion to the final frequency. Thereby, the requirements for the local oscillator provided in the IQ-modulator 400 could be reduced, if the final RF-frequency is to vary within a range of 900 MHz to 2.2 GHz, as required by the co-existence of current 2^nc generation mobile communication systems (e.g. GSM and GSM- 1800) and forthcoming 3^rci generation mobile communication systems (e.g. WCDMA).

Alternatively, the up-conversion could be directly performed by a DDS system with a sampling speed of around 4 GHz. Moreover, such a DDS-system could be used in the complex channel separation unit 100 to generate an IF signal which corresponds to the angle velocity <x>i required for the complex mixing operation. In the feedback path, it is possible to use one mixer to convert the signal to a lower intermediate frequency, to sample and to use a digital quadrature modulator to separate the in-phase and quadrature-phase signals needed in the adaptation. In this way, an introduction of any inaccuracies to the adaptation procedure due to linear impairments present in analogue quadrature modulators can be suppressed.

As regards a DC-offset problem of the IQ-modulator 400, which results in a discrete peak at the center of the output spectrum of Fig. 4 due to local oscillator leakage via the feedback loop, it is noted that the mapping predistortion method compensates this DC-offset problem at least to some extend. If there still exists a peak at the center frequency (i.e. 2100 MHz) or if there is an additional DC- offset problem in the IQ-demodulator 900, for example AC- coupling could be introduced into the feedback baseband parts to thereby remove the DC-offset. Due to the complex mixing operation in the complex channel separation unit

100, the signal band is shifted above DC by the amount of the intermediate frequency of e.g. 2.5 MHz.

In summary, the present invention relates to a multicarrier circuit arrangement and a method for linearising a multi- carrier circuit arrangement in which frequency channels are combined by using a complex mixing operation to generate a complex signal, so as to achieve a complex channel separation. A predistorted complex signal is then generated by applying a complex predistortion to said complex signal. Thereby, an efficient linearisation of wideband multicarrier circuit arrangements can be achieved, since the bandwidth requirements of digital predistortion are relaxed by enabling a baseband predistortion of multicarrier signals. It is pointed out that the multicarrier circuit arrangement and linearization method described in the preferred embodiment can be applied in any multicarrier circuit arrangement where the effects of a non-linear circuit element are to be compensated. The above description of the preferred embodiment and the accompanying drawings are only intended to illustrate the present invention. The preferred embodiment of the invention may thus vary within the scope of the attached claims.

Claims

1. A method for linearising a multicarrier circuit ar- rangement in which different frequency channel signals are processed, said method comprising the steps of: a) combining said different frequency channel signals by using a complex mixing operation to generate a single composite complex signal, so as to achieve a complex chan- nel separation; and b) generating a predistorted complex signal by applying predistortion to said composite complex signal.

2. A method according to claim 1, further comprising the step of calculating predistortion values by comparing said complex signal generated in complex channel separation with a feedback signal coupled from the output of said multicarrier circuit arrangement.

3. A method according to claim 1 or 2, wherein said predistorted complex signal is converted to a real bandpass signal by a quadrature modulator.

4. A method according to claim 3, wherein said conversion is performed by using a single quadrature modulator (400) .

5. A method according to claim 3, wherein said conversion is performed by using a digital quadrature modulation with a DDS carrier generation scheme.

6. A method according to claim 3, wherein said complex signal is first up-converted with an IQ-modulator to an intermediate frequency, and then with a mixer to a final radio frequency.

7. A method according to one of the preceding claims, wherein said predistortion is a two-dimensional digital predistortion, in which a complex predistortion coefficient is added to said complex signal.

8. A method according to claim 7, wherein said two- dimensional digital predistortion is performed by using said complex signal as an address signal for addressing a memory location in which said complex predistortion coeffi- cient is stored.

9. A method according to claims 7 or 8, wherein said predistortion is a two-dimensional mapping operation using a two-dimensional interpolation.

10. A method according to claim 9, wherein said two- dimensional mapping operation employs Cartesian components of said complex signal by which two-dimensional predistortion tables (601, 602) are addressed.

11. A method according one of claims 1 to 6, wherein said predistortion is a three-dimensional mapping predistortion in which the components of said complex signal and an instantaneous frequency value are used to address a memory (600) .

12. A method according to one of the preceding claims, wherein said composite complex signal is generated in dual- carrier case according to the following equation:

wherein Sχ(t) denotes said first frequency channel signal, S (t) denotes said second frequency channel signal, 0_ de- notes an intermediate frequency, and S_BB(t) denotes said composite complex signal.

13. A method according to one of the preceding claims, wherein said predistortion is an adaptive predistortion adapted to amplitude-, phase- and/or frequency/time- variance properties of said multicarrier circuit arrangement by using a feedback loop.

14. A method according to claim 2, wherein a complex sampling is performed at an intermediate frequency in the feedback path to obtain complex feedback signal for error signal calculation.

15. A method according to claim 13 or 14, wherein a feedback signal is generated by performing a down-conversion of an output signal of said multicarrier circuit arrangement.

16. A method according to one of claims 13 to 15, wherein the adaptation of said predistortion operation is based on a calculated error between a desired signal and a feedback signal obtained from said feedback loop.

17. A method according to claim 16, wherein a new estima- tion for said complex predistortion coefficient is obtained on the basis of said calculated error.

18. A method according to one of claims 13 to 17, wherein a phase adjustment between the forward branch and the feed- back branch of said feedback loop is performed by feeding a portion of an I-channel of said feedback signal into a Q- channel thereof, and/or vice versa.

19. A method according to claim 18, wherein said phase adjustment is based on an estimation of the phase difference between said complex signal and said feedback signal.

20. A method according to any one of the preceding claims, wherein a delay estimation of the delay between the forward branch and the feedback branch signals is performed and the delay is adjusted depending on the result of the delay estimation.

21. A multicarrier circuit arrangement for processing different frequency channel signals, said multicarrier circuit arrangement comprising: a) complex channel separating means (1; 100) for com- bining said frequency channel signals by using a complex mixing operation to generate a single composite complex signal so as to achieve a complex channel separation; and b) predistorting means (2; 200) for applying a complex predistortion to said complex signal so as to generate a predistorted complex signal.

22. A circuit arrangement according to claim 21, wherein said multicarrier circuit arrangement is a dual-carrier transmitter comprising a single quadrature modulator (4; 400) for directly converting said predistorted complex signal to a radio frequency range.

23. A circuit arrangement according to claim 21 or 22, wherein said predistorting means (2; 200) comprises a mem- ory (600; 601, 602) for storing complex predistortion coefficients .

24. A circuit arrangement according to claim 22, wherein said predistorting means (2; 200) is arranged to address two-dimensional predistortion tables stored in said memory (600; 601, 602) by using Cartesian components of said composite complex signal.

25. A circuit arrangement according to one of claims 21 to 24, wherein said predistorting means (2; 200) is arranged to perform a two-dimensional mapping operation using a two- dimensional interpolation of values stored in a/said memory (600; 601, 602) .

26. A circuit arrangement according to one of claims 21 to 24, wherein said predistorting means (2; 200) is arranged to address a three-dimensional predistortion table stored in a/said memory (6; 600) , by using Cartesian components of said complex signal and an instantaneous frequency value.

27. A circuit arrangement according to one of claims 21 to

26, further comprising adaptation means (7; 600; 610) for adapting said predistorting means (2; 200) to frequency/time-, amplitude- and phase-variance properties of said multicarrier circuit arrangement.

28. A circuit arrangement according to claim 27, wherein said adaptation means (600; 610) comprises error calculation means for calculating an error between a desired sig- nal and a feedback signal obtained from a feedback loop.

29. A circuit arrangement according to claim 28, further comprising phase adjusting means (702, 703) for adjusting a phase difference between the forward branch and the feed- back branch of said feedback loop by feeding a portion of an I-channel of said feedback signal into a Q-channel thereof, and/or vice versa.

30. A circuit arrangement according to claim 29, wherein said phase adjusting means (702, 703) comprises phase estimating means (703) for estimating the phase difference.

31. A circuit arrangement according to one of claims 21 to

30, comprising a delay estimation means (704) for estimating the delay between the forward branch and the feedback branch signals, and a delay adjustment means (701) for adjusting the delay depending on the result of the delay estimation.

32. A circuit arrangement according to one of claims 21 to

31, wherein said complex channel separating means (100) comprises a full-complex mixer or a quadrature modulator having quadrature outputs.