WO2002044836A2

WO2002044836A2 - Microprocessor-network communicaiton method and apparatus

Info

Publication number: WO2002044836A2
Application number: PCT/US2001/043621
Authority: WO
Inventors: Yijun Zhao
Original assignee: P & S Datacom Corporation
Priority date: 2000-11-28
Filing date: 2001-11-16
Publication date: 2002-06-06
Also published as: WO2002044836A3; AU2002241498A1

Abstract

A singal adapter (20) function as an intermediary between a microprossor software and hardware strucutres and transmits the reformated signal to the microporcessor (25). The signal adapter (20) also trnasforms a signal received from the microprocessor (25) into a signal compatible with the network protocol and transmites the transformed signal to the network gateway (12). The signal adapter (20) is capable of establishing a network communciaiton for various kinds of microprocessors without significantly modifying or reprogramming the microprocessors.

Description

MICROPROCESSOR-NETWORK COMMUNICATION METHOD AND APPARATUS

This application is a continuation-in-part application of U.S. Patent Application Serial Number 09/477,995, filed on January 5, 2000.

Field of the Invention

The present invention relates, in general, to network communication and, more particularly, to establishing communication between a microprocessor and a network.

Background of the _t Invention

Electronic devices are widely used in various aspects of daily life. Many electronic devices, such as those found in mobile telephones, automobiles, vending machines, utility meters, security systems, medical monitoring systems, etc., include microprocessors such as, for example, embedded microcontroller units (MCUs) for performing different functions and processes. It is often desirable to connect the MCU in an electronic device to a network such as Internet,, so that the operation of the electronic device can be remotely monitored and/or controlled. One approach for connecting a microprocessor such as an MCU to a network is to program a network protocol, e.g., Transmission Control Protocol/Internet Protocol (TCP/IP) , into the MCU. An MCU with TCP/IP programmed therein can access Internet through a modulation and demodulation device (MODEM) . This approach normally needs an MCU of at least 16 bits. It also needs a large memory, e.g., at least 32 kilo-bytes, and a high operating speed in order to achieve a satisfactory performance. Furthermore, the engineers who program the MCU chip must be familiar not only with the applications of the MCU but also with the TCP/IP protocol and related interfaces. Therefore, this approach usually requires a long development period, a high performance chip, and is cost inefficient. Another approach for connecting a microprocessor such as an MCU to a network is to establish an off chip network interface, e.g., an interface developed by emWare, Inc. under the trademark "emGateway", and program a network interface compatible protocol, e.g., a protocol developed by emWare, Inc. under the trademark "emNet", into the MCU chip. An MCU with emNet programmed therein can access Internet via the network interface emGateway. Although emNet requires less memory than TCP/IP, this approach still requires the design engineers to be familiar not only with the application of the MCU but also with the emNet and related interfaces.

Furthermore, the existing MCU chips in a user's application systems may not satisfy the designer's expectation because of chip capability, memory, speed, etc. Therefore, this approach often also requires a long development period, a relatively high performance chip, and is cost inefficient.

Accordingly, it would be advantageous to have a cost efficient method for communicating between a microprocessor and a network. It is desirable for the method to be simple and reliable. It is also desirable for the method to be compatible with different types of microprocessors in terms of capabilities, performances, costs, etc. It is especially desirable for the method to be compatible with a user' s existing microprocessor chips. It would be of further advantage to have a simple, reliable, and cost efficient apparatus to implement the method.

Summary of the Invention

A prime advantage of the present invention is to provide a simple and cost efficient process for communicating between a microprocessor and a network. Another advantage of the present invention is to provide a simple, reliable, and cost efficient apparatus to implement the communication process. A further advantage of the present invention is to provide the communication process capable of establishing communications between the network and microprocessors with wide spectra of applications, capabilities, performances, bit numbers, memory sizes, etc. In addition, a particular advantage of the present invention is that the communication process can be readily implemented with an existing microprocessor chip.

In order to achieve these and other advantages of the present invention, a method for communicating between a microprocessor and a network is implemented by first coupling the microprocessor to a signal adapter. The signal adapter of the present invention establishes communications between a microprocessor having an internal bus and a network gateway having a network bus. By way of example, the signal adapter of the present invention is sometimes referred to as a WebChip. Thus, the architecture and structure of the microprocessor can be independent of the communication protocol adopted by the network gateway.

The signal adapter includes a signal processing unit and a memory unit coupled to the signal processing unit. A communication protocol is stored in the memory unit. The signal adapter also has an interpreter stored in the memory unit. The interpreter is compatible with the programming language, e.g., Java, C, C++, an assembly language, etc., of the microprocessor. The signal adapter functions as an intermediary between the network and the microprocessor. A signal in the network typically follows a network protocol. For example, a signal in the Internet typically follows Transmission Control ^Protocol/Internet Protocol (TCP/IP) . Preferably, a signal in the network is sent to the microprocessor through a network gateway and the signal adapter. The network gateway coverts the signal from TCP/IP to a protocol compatible with the communication protocol on the signal adapter. The signal adapter identifies, interprets, and reformats the signal received from the network gateway into a microprocessor acceptable signal, e.g., a signal in a protocol compatible with the internal bus of the microprocessor, e.g., SPI, I²C, MICORWARE, etc. Further, the signal is preferably in a format compatible with Java, C, C++, an assembly language, etc. Depending on the signal, the signal adapter can execute the reformatted signal and/or send the reformatted signal to the microprocessor.

The microprocessor executes the received signal and sends a return signal back to the network. The return signal is sent to the signal adapter according to a format acceptable to the signal adapter. The signal adapter identifies, interprets, and reformats the return signal in accordance with the communication protocol and sends it to the network

I gateway. The network gateway converts the signal into the network protocol and sends it to the network. The signal adapter of the present invention can establish communications between networks and microprocessors of various capabilities, performances, bit numbers, and memory sizes. It is compatible with microprocessors having as little as four bits. It occupies significantly less memory on the microprocessor than prior art communication systems. It does not require significant modifications of the software and the hardware structure of existing microprocessors in a user's application systems. The designers of the microprocessors are not required to be familiar with the network protocol. By communicating with a network, e.g., Internet, via a network gateway, the communication protocol on the signal adapter can be simple and memory space efficient. Therefore, the signal adapter of the present invention is simple, reliable, and cost efficient.

Brief Description of the Drawings

Fig. 1 is a block diagram of a microprocessor-network communication system in accordance with the present invention;

Fig. 2 is a block diagram illustrating the physical structure of a signal adapter in accordance with a preferred embodiment of the present invention;

Fig. 3 is a functional block diagram illustrating a signal adapter in accordance with another preferred embodiment of the present invention; and Fig. 4 is a block diagram schematically illustrating a signal adapter in accordance with yet another embodiment of the present invention.

Detailed Description of the Preferred Embodiments

Various embodiments of the present invention are described herein below with reference to the figures, in which elements having similar functions are labeled using the same or related reference numerals in the figures. It should be understood that the scope of the present invention is not limited to those embodiments shown in the figures and described herein below.

Figure 1 is a block diagram illustrating a microprocessor-network communication system 10 in accordance with the present invention. By way of example, Fig. 1 shows communication system 10 between a network 15 and a plurality of microprocessors 25A, 25B, ..., and 25N. In accordance with the present invention, communication system 10 is capable of establishing the communications between network 15 and any number of microprocessors, e.g., one, two, three, four, and so on. Microprocessors 25A-25N include any kinds of processing units such as, for example, digital signal processing units (DSPs) , £entral processing units (CPUs) , microcontroller units (MCUs) , etc. Microprocessors 25A-25N can be coupled to various kinds of electronic systems (not shown) such as, for example, smart devices, utility meters, refrigeration systems, home security systems, medical monitoring systems, vending machines, navigation systems, etc. for monitoring and/or controlling the operations of those electronic systems. Communication system 10 establishes communications between network 15 and microprocessors 25A-25TSI through a network interface 12 and a plurality of signal adapters 20A, 20B, ..., and 20N. Network interface 12 is also referred to as a network gateway or a gateway. By way of example, signal adapters 20A-20N are sometimes referred to as WebChips and can includes a microprocessor, communication peripheral, field programmable £ate array (FPGA) , programmable logic device (P D) , system on chip (SOC) , application specific standard product (ASSP) , application specific -ntegrated circuit

(ASIC), DSP, CPU, MCU, etc. Signal adapter 20A is coupled to microprocessor 25A via a signal transmission line 24A. Likewise, signal adapter 20B is coupled to microprocessor 25B via a signal transmission line 24B, and signal adapter 20N is coupled to microprocessor 25N via a signal transmission line

24N. Signal adapters 20A-20N establish communications between network gateway 12 and respective microprocessors 25A-25N. In a preferred embodiment, each of signal adapters 20A-20N and corresponding microprocessors 25A-25N are located adjacent to each other and close to respective^, electronic systems (not shown) coupled to corresponding microprocessors 25A-25N. Signal adapters 20A-20N establish communications respective microprocessors 25A-25N having internal buses and network gateway 12 having a network bus. -Thus, the architectures and structures of microprocessors 25A-25N can be independent of the communication protocol adopted by network gateway 12.

By way of example, Fig. 1 shows network gateway 12 being coupled to network 15 via a signal transmission line 14 and coupled to signal adapters 20A, 20B, ..., and 20N via corresponding signal transmission lines 16A, 16B, ..., and 16N. This is not intended as limitations of the present invention. In a preferred embodiment, network 15, e.g., an Internet browser with TCP/IP, a web page, a database, a graphic user interface (GUI), a custom application program interface, etc., and network gateway 12 are installed in a single system, e.g., an information server, a database server, a personal computer, a p_ersonal digital assistant (PDA) , a _set-t_op box (STB) , an Internet appliance (IA) , etc. Alternatively, the communications between network gateway 12 and network 15 can be either wired or wireless. Likewise, the communications between network gateway 12 and signal adapters 20A-20N can also be either wired or wireless. Examples of wireless communication include radio frequency (RF) communication and infrared communication following an Infrared Data Association (IrDA) protocol. Wired communication can be either serial or parallel signal transmissions. The serial signal transmissions, such as asynchronous data transmissions following the RS-232 or RS-485 serial communication standard published by the Electronic Industries Alliance (EIA) , are typically more cost efficient and more reliable than parallel signal transmissions. However, the parallel signal transmissions are usually faster than the serial signal transmissions .

Figure 2 is a block diagram of the structure of a signal adapter 20 coupled between a network gateway 12 and a microprocessor 25 in accordance with a preferred embodiment of the present invention. Signal adapter 20 can be any of signal adapters 20A-20N shown in Fig. 1. Microprocessor 25 can be any of microprocessors 25A-25N shown in Fig. 1. Signal adapter 20 is an apparatus for establishing a communication or providing an interface between microprocessor 25 and a network, such as network 15 shown in Fig. 1. Signal adapter 20 transforms a signal received from network gateway 12 and following a communication protocol to a signal in an internal protocol compatible with the programming language and the hardware structure of microprocessor 25. The internal protocol is sometimes also referred to as a microprocessor protocol. Signal adapter 20 also transforms a signal received from microprocessor 25 and following the microprocessor protocol compatible with the programming language the hardware structure of microprocessor 25 to a signal in the communication protocol compatible with network gateway 12. Therefore, signal adapter 20 can also be referred to as a network adapter, a network connector, an interface, a signal conversion device, a data conversion device, a network connecting device, a network connectivity device, a network interface, a communication controller, etc.

Signal adapter 20 includes a signal processing unit 42 and a memory unit 44 coupled to signal processing unit 42. Preferably, memory unit 44 is a nonvolatile memory unit, e.g., a read only memory (ROM) , an electrically erasable and programmable read only memory (EEPROM) , FLASH memory, and the likes. Signal processing unit 42 can be a microprocessor, an MCU, a CPU, or the likes. Typically, signal adapter 20 also includes a volatile memory unit (not shown), e.g., a static random access memory (SRAM) or a dynamic random access memory (DRAM) unit coupled to signal processing unit 42. A communication protocol 43 and an interpreter 45 are established in signal adapter 20. By way of example, communication protocol 43 and interpreter 45 are stored in memory unit 44. Communication protocol 43 is preferably compatible with a protocol of network gateway 12. By way of example, network gateway 12 may adopt emNet protocol. Interpreter 45 is preferably compatible with a programming, language, e.g., Java, C, C++, assembly language, etc., of microprocessor 25.

Signal adapter 20 has terminals 54 and 56 connected to signal processing unit 42. Terminal 54 is adapted for coupling to microprocessor 25 via a signal transmission line 24. Signal transmission line 24 can be a serial signal transmission line or a parallel signal transmission line. In , a preferred embodiment, signal transmission line 24 includes a three-wire serial synchronous communication protocol referred to as s_erial peripheral interface (SPI) and developed by Motorola, Inc. In another preferred embodiment, signal transmission line 24 includes a multi-master bus referred to as an Inter-Integrated Circuit (I²C) bus and developed by Philips Semiconductors, Inc. In yet another preferred embodiment, signal transmission line 24 includes a serial bus developed by National Semiconductor Corporation under the trademark MICROWARE.

Terminal 56 is adapted for transmitting signals between signal processing unit 42 and network gateway 12. The signal transmissions between signal processing unit 42 and network gateway 12 can be either wired or wireless and may follow any industry standards or protocols such as those described herein above with reference to Fig. 1. An interface circuit 46 in signal adapter 20 is connected to terminal 56 and functions to conform signal to predetermined standards and protocols. Signal adapter 20 further includes an oscillator and identifier circuit 48 coupled to signal processing unit 42. The oscillator provides a clock signal to signal processing unit 42. The identifier provides an electronic identification to signal adapter 20, thereby enabling network gateway 12 to selectively communicate with any of microprocessors 25A-25N via respective signal adapters 20A-20N as shown in Fig. 1.

In a preferred embodiment, signal processing unit 42 and memory unit 44 are fabricated on a single semiconductor chip. Interface circuit 46 and oscillator and identifier circuit 48 can be either fabricated on the same chip as signal processing unit 42 and memory unit 44 or fabricated on different chips. Preferable, signal processing unit 42, memory unit 44, interface circuit 46, and oscillator and identifier circuit 48 are packaged together as a single integrated c_ircuit (IC) device 20. However, this is not a limitation of the present invention. In accordance with the present invention, different components in signal adapter 20 can be fabricated on a single chip or on different chips and can be packaged into a signal device or packaged into several devices. Further, signal adapter 20 is not limited to being an IC device. It is also conceivable for signal adapter 20 to be comprised of discrete devices.

In operation, when signal adapter 20 is switched on, it is initially disconnected from network gateway 12. Signal adapter 20 sends a signal to microprocessor 25 requesting initialization. Microprocessor 25 responds by transmitting an initialization signal to signal adapter 20. Signal adapter 20 sets up the connection with network gateway 12 in accordance with the initialization signal. If signal adapter 20 does not receive the initialization signal from microprocessor 25 within a predetermined time interval, it will use a default initial state to establish the connection with network gateway 12. Signal adapter 20 will generate an error signal and transmit the error signal to network gateway 12, informing network 15 regarding the initialization failure.

The communications among microprocessor 25, signal adapter 20, and network gateway 12 follow a predetermined protocol. In a preferred embodiment, network gateway 12 and signal adapter 20 have a master-slave relationship with respect to each other, and signal adapter 20 and microprocessor 25 have a master-slave relationship with respect to each other. A master can initiate a process in a slave by sending a signal to the slave, and the slave sends signals back the master upon request. Network gateway 12 can send command signals, data signals, and request signals to signal adapter 20. Upon receiving a signal from network gateway 12, communication protocol 43 in signal adapter 20 unpacks the signal and verifies the validity of the signal. By way of example, signal adapter 20 can verify the validity of the signal by performing a cyclic redundancy check (CRC) . Signal adapter 20 informs network gateway 12 about any invalid signal. In accordance with communication protocol 43 and interpreter .45 stored in memory unit 44, signal processing unit 42 transforms or converts a valid signal following the communication protocol into a signal following the microprocessor protocol in accordance with a microprocessor programming language. In other words, signal adapter 20 generates a signal or a data package in the microprocessor protocol compatible with microprocessor 25 in response to the signal in the communication protocol and received from network gateway 12. More particularly, signal adapter 20 identifies, interprets, and reformats the signal from network gateway 12 into a signal acceptable to microprocessor 25. Depending the signal, signal adapter 20 executes the transformed signal and/or transmits the ^■ transformed signal to microprocessor 25 via signal transmission line 24.

Microprocessor 25 executes the incoming signal or data received from signal adapter 20. Depending on the signal, microprocessor 25 may return a signal or data package back to network gateway 12. In a preferred embodiment, microprocessor 25 can send data or return signals to adapter only after receiving permission from signal adapter 20. Upon receiving the permission, microprocessor 25 transmits the returned signal to signal adapter 20 via signal transmission line 24. Preferably, the return signal follows a predetermined format acceptable to signal adapter 20. In accordance with communication protocol 43 and interpreter 45 stored in memory unit 44, signal processing unit 42 transforms, converts, or reformats the return signal following the microprocessor programming language into a signal in the communication protocol. In other words, signal adapter 20 generates a signal or a data packet in a protocol compatible with the communication protocol in response to the signal in the • microprocessor protocol compatible with microprocessor 25 and received from microprocessor 25. Following permission from network gateway 12, signal adapter 20 transmits the transformed signal to network gateway 12 through interface circuit 46. Depending on its size, a signal or data transmitted between network gateway 12, signal adapter 20, and microprocessor 25 can be transmitted in a single data packet or in a plurality of data packets.

As mentioned herein above, signal adapter 20 sends a signal to microprocessor 25 requesting initialization when signal adapter 20 is switched on. After initialization, signal adapter 20 periodically sends event polling signals to microprocessor 25. If there is an event to be reported from microprocessor 25 to network gateway 12. Signal adapter 20 will establish a connection or a path of signal transmission to network gateway 12. In addition, signal adapter 20 may transmit signals to microprocessor 25 for sending data to microprocessor 25 and for granting permission to microprocessor 25 to send data to signal adapter 20.

In response to a command signal from signal adapter 20, microprocessor 25 can send a control command signal to signal adapter 20 to disrupt the path of signal transmission between signal adapter 20 and network gateway 12, or disconnect signal adapter 20 from network gateway 12. While being disconnected from network gateway 12, signal adapter 20 is preferably in a low power consumption sleep state. In accordance with a preferred embodiment of the present invention, signal adapter 20 in the sleep state periodically sends request signals to microprocessor 25. For example, signal adapter 20 can generate and transmit a request signal to microprocessor 25 once in a period ranging from approximately 50 milliseconds (ms) to approximately 800 ms. According to one preferred embodiment, signal adapter 20 transmits a request signal to microprocessor 25 every 200 ms . According to another preferred embodiment, signal adapter 20 transmits a request signal to microprocessor 25 every 500 ms . In accordance with the present invention, microprocessor 25 sends a response signal to signal adapter 20. The response signal may continue to place signal adapter 20 in the sleep mode. The response signal may also be a control command signal for reconnecting signal adapter 20 to 'network gateway 12, initializing or resetting signal adapter 20, etc.

In a preferred embodiment, information communicated between microprocessor 25 and network gateway 12 are preferably based on an object property table that describes object properties related to the operation of microprocessor

25 such as the number of objects in the object property table, the bytes occupied by the object property table, etc. The object property table can be stored in microprocessor 25, signal adapter 20, network gateway 12, or a server on network 15. If the object property table is stored in microprocessor 25, the object property table is preferably mapped from microprocessor 25 to signal adapter 20 and further to network gateway 12 upon initialization of signal adapter 20.

Figure 3 is a functional block diagram illustrating a signal adapter 20 couple between microprocessor 25 and network gateway 12 in accordance with another preferred embodiment of the present invention. Signal adapter 20 serves to establish communications between microprocessor 25 having an internal bus and network gateway 12 having a network bus. Thus, the architecture and structure of microprocessor 25 can be independent of the communication protocol adopted by network gateway 12. By way Of example, microprocessor 25 is an MCU.

Signal adapter 20 has an application layer 100 functionally coupled to MCU 25 via a data transmission layer 62, an MCU bus 64, and signal transmission line 24. Data transmission layer 62 controls the signal transmission between application layer 100 and MCU bus 64. Data transmission layer 62 also performs the trouble shooting function during the data transmission process. MCU bus 64 provides a physical port for signal transmission line 24 between signal adapter 20 and MCU 25. MCU bus 64 generates voltage levels at signal transmission line 24 when signal adapter 20 transmits signals to MCU 25, and sense the voltage levels at signal transmission line 24 when signal adapter 20 receives signals from MCU 25. Application layer 100 is further coupled to network gateway 12 via a communication interface protocol stack 82, a gateway bus 84, and signal transmission line 16. Communication interface protocol stack 82 preferably supports various types of communication processes. When signal adapter 20 transmits data to network gateway 12, communication interface protocol stack 82 encodes the data packets into electrical signals and sends the signals to network gateway 12 via gateway bus 84. When signal adapter 20 receives a data packet from network gateway 12, communication interface protocol stack 82 decodes the data packet from the electrical signals transmitted from network gateway 12 via gateway bus 84. Communication interface protocol stack 82 also verifies the validity of the signal. Communication interface protocol stack 82 includes a medium assess control unit (MAC) 83 for network address coding. MAC 83 serves to direct data packets to proper a destination node address on network 15 shown in Fig. 1. MAC 83 also serves to determine whether signal adapter 20 and MCU 25 coupled thereto are at the proper network node address for an incoming data packet. Gateway bus 84 transmits signal to network gateway 12 by generating voltage levels and signal transmission line 16. When receiving signals from network gateway 12, gateway bus 84 senses the voltage levels at signal transmission line 16. Gateway bus 84 can be any kinds of data transmission physical interfaces, e.g., RS-232, RS-485, universal _serial bus (USB), controller area network (CAN) , consumer electronics bus (CEBus) , Bluetooth, etc. Gateway bus 84 is sometimes also referred to as a network bus .

Application layer 100 includes a protocol conversion unit or converter 102 in application layer 100 for converting the data format between a protocol compatible with MCU 25, referred as an MCU protocol by way of example, and a protocol compatible with network gateway 12, referred to as a communication protocol by way of example. Protocol converter 102 is coupled to a memory 104 in application layer 100.

Memory 104 preferably includes a non-volatile memory such as, for example, FLASH, EEPROM, etc., and a volatile memory such as SRAM, DRAM, etc. In a preferred embodiment, signal adapter 20 has a digital identification (Digital ID) (not shown) stored in memory 104. The Digital ID of signal adapter 20 provides accessibility of signal adapter 20 from anywhere on network 15 shown in Fig. 1. Protocol converter 102 and memory 104 are also coupled to an MCU data processing unit 106 and a network data process unit 108 in application layer 100. MCU data processing unit 106 is coupled to data transmission layer 62. MCU data processing unit 106 packs the data to be sent to MCU 25 into data packets and transmits the data packets to data transmission layer 62. MCU data processing unit 106 also unpacks the data packets from MCU 25 via data transmission layer 62 and sends the unpacked data to protocol converter 102. Network data processing unit 108 is coupled to communication interface protocol stack 82. Network data processing unit 108 packs the data to be sent to network gateway 12 into data packets and transmits the data packets to communication interface protocol stack 82. Network data processing unit 108 also unpacks the data packets from network gateway 12 via communication interface protocol stack 82 and sends the unpacked data to protocol converter 102.

Application layer 100 also includes communication control unit or a controller 105 coupled to protocol converter 102, memory 104, MCU data processing unit 106, and network data processing unit 108 in application layer 100. Controller 105 is further coupled to data transmission layer 62, communication interface protocol stack 82, and gateway bus 84 in signal adapter 20. In a preferred embodiment, controller 105 can modify the communication codes stored in memory 104, thereby controlling the operation modes of signal adapter 20. Through controlling data transmission layer 62, controller 105 is capable of setting the signal transmission modes between MCU 25 and signal adapter 20. Likewise, through communication interface protocol stack 82, controller 105 is capable of setting the signal transmission modes between signal adapter 20 and network gateway 12 and setting the format of the data packets to be sent from signal adapter 20 to network gateway 12. Through gateway bus 84, controller 105 is capable of selecting the communication modes and signal transmission speeds between signal adapter 20 and network gateway 12.

Memory 104 stores the programming codes and relevant parameters for the operation of signal adapter 20. Memory 104 may also store the object property table. If the object property table is stored in MCU 25, it is preferably mapped into memory 104 when signal adapter 20 is initialized. Memory 104 also temporarily stores the information passing through signal adapter 20 during the communication between network gateway 12 and MCU 25. In a preferred embodiment, memory 104 includes two memory blocks so that the programming codes in memory 104 can be modified through an In-Application re- Programming (IAP) process initiated by user coupled to network gateway 12. In operation, when signal adapter 20 is switched on, it is initially disconnected from network gateway 12. Signal adapter 20 sends a signal to MCU 25 requesting initialization. MCU 25 responds by transmitting a control signal to signal adapter 20. Controller 105 in signal adapter 20 executes the control signal from MCU 25 and sets up the connection with network gateway 12 in accordance with the initialization signal. If signal adapter 20 does not receive the control signal from MCU 25 within a predetermined time interval, controller 105 will generate an error signal. Alternatively, controller 105 may use a default initial state to establish the connection between signal adapter 20 and network gateway 12. Controller 105 selects a communication interface protocol, e.g., USB, RS-232, R-485, etc., stored in communication interface protocol stack 82 to match that of gateway bus 84.

The communications between MCU 25, signal adapter 20, and network gateway 12 follow a predetermined model or structure. In a preferred embodiment, network gateway 12 and signal adapter 20 have a master-slave relationship with respect to each other, and signal adapter 20 and MCU 25 have a master- slave relationship with respect to each other. A master can initiate a process in a slave by sending a signal to the slave, and the slave sends signals back the master upon request. Network gateway 12 can send command signals, data signals, and request signals to signal adapter 20. Gateway bus 84 senses the voltage levels at signal transmission line 16, thereby receiving the signals form network gateway 12. MAC 83 in communication interface protocol stack 82 determines whether signal adapter 20 and MCU 25 coupled thereto are the proper network node address for receiving the signals from network gateway 12. Communication interface protocol stack 82 decodes the electrical signals from gateway bus 84 and preferably verifies the validity of the signals from network gateway 12. Preferably, signal adapter 20 informs network gateway 12 about any invalid signal. After the validity check, communication interface protocol stack 82 sends the decoded signals to network data process unit 108 in data packets . Network data processing unit 108 unpacks the data packets and sends the unpacked data to protocol converter 102. The signals from network gateway 12 follow a communication protocol, protocol converter 102 transforms or converts a valid signal following the communication protocol into a signal following an MCU protocol in accordance with a microprocessor programming language and the hardware structure of MCU 25. In other words, protocol converter 102 generates signals or data in an MCU protocol compatible with MCU 25 in response to the signals in the communication protocol and received from network gateway 12. More particularly, protocol converter 102 identifies, interprets, and reformats the signal from network gateway 12 into a signal acceptable to MCU 25.

Depending on the nature of the signal, controller 105 may instruct signal adapter 20 to ignore the transformed signal, or execute the signal and proceed to transmit the transformed signal to MCU 25. To transmit the signal to MCU 25, protocol converter 102 sends the transformed signal to MCU data processing unit 106, which packs the signal into data packets and transmits the data packets to MCU bus 64 via data transmission layer 62. Data transmission layer 62, which performs the functions of data transmission control and trouble shooting. MCU bus 64 generates voltage levels at signal transmission line 24 to transmit data to MCU 25.

As a slave with respect to signal adapter 20, MCU 25 preferably responds every signal from signal adapter 20. If MCU 25 fails to respond within a predetermined time interval, e.g., a time interval between approximately 50 ms and approximately 800 ms, controller 105 in signal adapter 20 will recognizes it as a timeout error. MCU 25 transmits the response signal in data packets to signal adapter 20 via signal transmission line 24. MCU bus 64 senses the voltage levels at signal transmission line 24 to detect the signals from MCU 25. Data transmission layer 62 relays the signal from MCU bus 64 to MCU data processing unit 106. MCU data processing unit 106 unpacks the data packets received from data transmission layer 62 and sends the unpacked data to protocol converter 102.

Protocol converter 102 transforms, converts, or reformats the data following the MCU protocol to into signals or data following the communication protocol of network gateway 12. In other words, protocol converter 102 generates the signals in the communication protocol accepted by network gateway 12 in response to signals or data in an MCU protocol compatible with MCU 25. More particularly, protocol converter 102 identifies, interprets, and reformats the signal from MCU 25 into a signal acceptable to network gateway 12. Signal adapter 20 can ignore the signal from MCU 25. Further, signal adapter 20 may transmit the signal received from MCU 25 to network gateway 12. To relay the signal from MCU 25 to network gateway 12, protocol converter 102 transmits the converted signal to network data processing unit 108, which packs the signal into data packets and sends the data packets to communication interface protocol stack 82. Communication interface protocol stack 82 encodes the data packets into electrical signals.

Gateway bus 84 generates voltage levels at signal transmission line 16 in accordance with the encoded electrical signals from communication interface protocol stack 82, thereby transmitting the response signal from MCU 25 to network gateway 12.

As a master with respect to MCU 25, signal adapter 20 can sends command signals to MCU 25. Signal adapter 20 may send commands to MCU 25 as requested by its own master network gateway 12 or as initiated by signal adapter 20 itself. For example, signal adapter may periodically sends event polling signals to MCU 25. A command signal from signal adapter 20 preferably requires a response from MCU 25. The response signal from MCU 25 may include information and data requested by signal adapter 20. MCU may also respond signal adapter 20 by transmitting a control command to signal adapter 20. Controller 105 in signal adapter 20 preferably executes the control command, thereby initializing, rebooting, or resetting signal adapter 20. Through controller 105, the control command from MCU 25 can specify the communication modes between signal adapter 20 and MCU 25 and between signal adapter 20 and network gateway 12. The control command can also disconnect signal adapter 20 from network gateway 12 and put signal adapter in a low power consumption sleep mode. In the sleep mode, signal adapter 20 periodically sends polling signals to MCU 25. MCU 25 can wake up signal adapter 20 by sending a command to signal adapter 20 in response to the polling signal.

A user on network 15 can send programming codes to signal adapter 20 via network gateway 12. Preferably, the programming codes transmitted to signal adapter 20 can be used for modifying the programming codes of signal adapter 20 in an IAP process. In addition, signal adapter 20 can reformats the programming codes and send the reformatted programming codes - to MCU 25 for modifying the programming codes in MCU 25 in an IAP process.

Figure 4 is a block diagram schematically illustrating a signal adapter chip 120 in accordance coupled between MCU 25 and network gateway 12 in with yet another preferred embodiment of the present invention. Signal adapter chip 120, which is sometimes also referred to as a WebChip, includes a signal adapter 20 and a peripheral circuit 90. By way of example, signal adapter chip 120 can replace any of signal adapters 20A-20N shown in Fig. 1. Signal adapter 20 in signal adapter chip 120 is functionally similar to signal adapter 20 shown in Figs. 2 and 3. Peripheral circuit 90 may include any circuit, e.g., real t_ime clock (RTC) , FPGA, power management circuitry, data converter, etc., that is suitable to serve as a periphery for MCU 25. MCU 25 can be replaced with a microprocessor, FPGA, PLD, ASSP, ASIC, DSP, CPU, etc. Signal adapter chip 120 also includes a switching unit 121 coupled to MCU 25 via signal transmission line 24. Switching unit 121 is also coupled to signal adapter 20 via an internal bus 124 and to peripheral circuit 90 via another internal bus 94. A switch logic circuit 123 on signal adapter chip 120 is coupled for controlling switching unit 121. MCU 25 has a chip selection (CS) or chip enabling (CE) signal line 125 coupled to switch logic circuit 123 in signal adapter chip 120.

A feature of signal adapter chip 120 is the inclusion of peripheral circuit on the same chip as signal adapter 20. Through CS signal line 125, MCU 25 transmits a chip selection signal to switch logic circuit 123. Switch logic circuit 123 controls switching unit 121 to determine whether signal transmission line 24 is coupled to signal adapter 20 via internal bus 124 or to peripheral circuit 90 via internal bus 94. When coupled to signal adapter 20 via signal transmission line 24, switching unit 121, and internal bus 124, MCU 25 can communicate with signal adapter 20 and network gateway 12 in a process similar to those described supra with reference to Figs. 1, 2, and 3. MCU 25 is a slave with respect to signal adapter 20. When coupled to peripheral circuit 90 via signal transmission line 24, switching circuit 121, and internal bus 94, MCU 25 is the master of peripheral circuit 94. The communication and operation of an MCU and its peripheral circuit are well known in the art. By now it should be appreciated that a process and a signal adapter for establishing microprocessor-network communications have been provided. The signal adapter of the present invention is capable of establishing communications between networks and microprocessors without modifying the software structure or the hardware structure of existing microprocessors. The microprocessor design processes do not depend on the network protocol. The designers of the microprocessors are not required to be familiar with the network protocol. The signal adapter is compatible with microprocessors, MCUs, CPUs, etc., of various capabilities, performances, bit numbers, and memory sizes. Thus, the development time and cost of a microprocessor-network system in accordance with the present invention are significantly reduced compared with prior art microprocessor-network communication systems. In a preferred embodiment, the signal adapter communicates with the network via a network gateway, thereby significantly simplifying the signal adapter compared with prior art devices. Therefore, the signal adapter of the present invention is simple, reliable, and cost efficient. In addition, the communication process of the present invention can be readily implemented with microprocessors in a user's existing application systems.

Claims

1. A method for establishing a communication between a microprocessor and a network, comprising the steps of: coupling a signal adapter to the microprocessor; transmitting a first signal in a first protocol from the signal adapter to the microprocessor; transmitting a second signal in the first protocol from the microprocessor to the signal adapter in response to the first signal; and generating a third signal in a second protocol from the signal adapter to the network in response to the second signal.

2. The method as claimed in claim 1, wherein the step of transmitting a second signal further includes transmitting the second signal to initialize the signal adapter and establish a path of signal transmission between the signal adapter and the network.

3. The method as claimed in claim 1, further comprising the step of transmitting the third signal from the signal adapter to the network.

4. The method as claimed in claim 3, wherein the step of transmitting the third signal from the signal adapter to the network includes transmitting the third signal to the network via a network gateway.

5. The method as claimed in claim 1, wherein the step of transmitting a first signal includes transmitting the first signal of a type selected from the group consisting of polling command signals, data signals, and request signals.

6. The method as claimed in claim 1, further comprising the steps of: establishing a first master-slave relationship between the network and the signal adapter with the network being a master with respect to the signal adapter and the signal adapter being a slave with respect ' to the network; and establishing a second master-slave relationship between the signal adapter and the microprocessor with the signal adapter being a master with respect to the microprocessor and the microprocessor being a slave with respect to the signal adapter.

7. The method as claimed in claim 1, further comprising the step of creating an object property table in the microprocessor.

8. The method as claimed in claim 7, further comprising the step of mapping the object property table to the signal adapter.

9. The method as claimed in claim 1, wherein the step of transmitting a first signal includes transmitting the first signal to perform an In-Application re-Programming process in the microprocessor.

10. i A method for establishing microprocessor-network communication, comprising the steps of: coupling a signal adapter to a microprocessor; transmitting a first signal in a first protocol from a network gateway to the signal adapter; transforming the first signal to a second signal in a second protocol; transmitting the second signal from the signal adapter to the microprocessor; transmitting a third signal in the second protocol from the microprocessor to the signal adapter in response to the second signal; transforming the third signal to a fourth signal in the first protocol; and transmitting the fourth signal from the signal adapter to the network gateway.

11. The method as claimed in claim 10, wherein the step transmitting the second signal includes the step of performing an In-Application re-Programming process in the microprocessor.

12. The method as claimed in claim 10, further comprising the steps of: coupling a second signal adapter to a second microprocessor; transmitting a fifth signal in a first protocol from the network gateway to the second signal adapter; and reformatting the fifth signal to a sixth signal acceptable to the second microprocessor.

13. The method as claimed in claim 10, wherein: the steps of transmitting a first signal in a first protocol and transforming the third signal to a fourth signal in the first protocol include adopting a network compatible protocol as the first protocol; and the steps of transforming the first signal to a second signal in a second protocol and transmitting a third signal in the second protocol include adopting a protocol compatible with a software and hardware structure of the microprocessor as the second protocol.

14. The method as claimed in claim 10, further comprising the steps of: creating an object property table in the microprocessor; and mapping the object property table to the signal adapter.

15. An apparatus for establishing a communication between a microprocessor and a network gateway, comprising: a protocol converter, said protocol converter being adapted for converting signals between a first protocol and a second protocol; a memory unit coupled to said protocol converter; a communication controller coupled to said memory and to said protocol converter; a communication interface protocol stack coupled to said protocol converter and to the network gateway; and a data transmission layer coupled to said protocol converter and to the microprocessor.

16. The apparatus of claim 15, further comprising: a first data transmission unit coupled between said communication interface protocol stack and said protocol converter; and a second data transmission unit coupled between said data transmission layer coupled to said protocol converter.

17. The apparatus of claim 15, further comprising a digital identification stored in said memory unit.

18. The apparatus of claim 15, said protocol converter being adapted for transforming a first signal following the first protocol and received from the network gateway to a second signal following the second protocol and transforming a third signal following the second protocol received from the microprocessor to a fourth signal following the first protocol.

19. The apparatus of claim 15, said communication controller periodically generating request signals and transmits the request signals to the microprocessor.

20. The apparatus of claim 19, said communication controller periodically generating event polling signals and transmits the event polling signals to the microprocessor.