WO2002101711A1 - Graphics system including a plurality of heads - Google Patents

Graphics system including a plurality of heads Download PDF

Info

Publication number
WO2002101711A1
WO2002101711A1 PCT/US2002/016929 US0216929W WO02101711A1 WO 2002101711 A1 WO2002101711 A1 WO 2002101711A1 US 0216929 W US0216929 W US 0216929W WO 02101711 A1 WO02101711 A1 WO 02101711A1
Authority
WO
WIPO (PCT)
Prior art keywords
heads
vga
display
display system
host
Prior art date
Application number
PCT/US2002/016929
Other languages
French (fr)
Inventor
Jonah Matthew Alben
Krishnaraj S. Roa
Original Assignee
Nvidia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corporation filed Critical Nvidia Corporation
Publication of WO2002101711A1 publication Critical patent/WO2002101711A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1438—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using more than one graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers

Definitions

  • the present invention relates generally to a graphics display system and more particularly to a graphics display system that includes a broadcast mode VGA feature.
  • a graphics display system it is desirable to be able to display the images to different types of displays.
  • Conventional graphic display systems do allow displaying to a different display, but only if the timing is exactly the same for the displays. For example, in a conventional graphics display system, if a flat panel provides a 1600x1200x60 Hz scale image, a cathode ray tube (CRT) will display the same scale image. Typically this is accomplished utilizing a single head design which works for one display pipeline. To describe this single head design in more detail, refer now to Figure 1.
  • FIG. 1 is a block diagram of a conventional graphics display system 10.
  • the conventional graphics display system 10 includes a memory 12 which is in communication with a frame buffer interface 14.
  • the system 10 includes a host 16 which receives programming signals from an AGP (or PCI) bus 18 which controls both a VGA controller 20 and a CRT controller 22.
  • the VGA controller 20 retrieves information from and provides information to the frame buffer interface and communicates with the CRT controller 22 via register signals.
  • the CRT controller 22 is coupled to pipeline 24.
  • the VGA controller 20, CRT controller 22 and pipeline 24 comprise a single display head 40.
  • the CRT controller 22 then provides data through a pipeline 24 to a plurality of displays, for example a CRT 26, fiat panel (FP) display 28 or a television 30.
  • FP fiat panel
  • a problem with the single head system is that, unless all of the displays are compatible, then there are timing issues associated therewith. Accordingly, the pipeline would require complex circuitry to ensure that these timing issues are addressed, which would significantly add to the cost of the graphics display system.
  • the conventional graphics display system 10 works well with traditional panels (800x600, 1024x768) which use standard VESA timings. However, the mobile industry is moving aggressively towards large flat panels (1600x1200, 2048x1536) with non-standard timings.
  • a graphics display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller. Each of the heads is adapted for a display.
  • the graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads are programmed by a single command by the host.
  • a system and method for providing a broadcast mode VGA feature is disclosed.
  • a method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA data read from the bus always comes from one of the heads.
  • the output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, the software sets up the timing in extended registers and enables the CRT. The VGA application can then provide mode settings via the appropriate write to VGA registers and the correct display will be on each
  • Figure 1 is a block diagram of a conventional graphics display system.
  • FIG. 2 is a block diagram of a graphics display system in accordance with the present invention.
  • Figure 3 is a diagram that illustrates areas for VGA register settings 202 and shadow state register settings 204 for the custom settings for the specific display.
  • Figure 4 is a flow chart illustrating a process for programming both VGA controllers simultaneously within the graphics display system in accordance with the present invention.
  • the present invention relates generally to a graphics display system and more particularly to a graphics display system that includes a plurality of heads.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
  • FIG. 2 is a block diagram of a graphics display system 100 in accordance with the present invention.
  • the graphics display system 100 includes first and second display heads 102a and 102b which can be individually programmed via the host 110. Each of the heads 102a and 102b are in-eommunication with a frame buffer interface 14'. Although two heads 102a and 102b are shown in accordance with the preferred embodiment, one of ordinary skill in the art readily recognizes that there can be any number of heads within the graphics system and that would be within the spirit and scope of the present invention.
  • Each head 102a and 102b is also in communication with the host 110 which receives programming signals from an AGP (or PCI) bus 18.
  • the host 110 communicates with both of the CRT controllers 122a and 122b.
  • the VGA controllers 120a and 120b retrieve information from and provide information to the frame buffer interface and communicate with its respective CRT controller, 122a orl22b, via register signals.
  • Each of the CRT controllers 122a and 122b then provides data through its respective pipeline 124a or 124b to a plurality of displays, for example, flat panel displays, TV and a CRT.
  • the host 110 in a custom mode, provides programming signals to the CRT controllers 122a and 122b to provide the custom settings for the particular display (i.e., flat panel, television and/or CRT).
  • the host 110 in a broadcast mode also provides a standard VGA programming signal 121, which sets the VGA register settings in both VGA controllers 122a and 122b. In so doing, the standard VGA programming signal 121 allows each of the heads 102a and 102b to be programmed simultaneously.
  • Figure 3 is a diagram that illustrates areas for VGA register settings 202 and shadow state register settings 204 for the custom settings for the specific display.
  • the custom timing information for the particular display i.e., a CRT, FP or TV
  • the host also provides the standard VGA settings for all of the active heads.
  • the VGA write transactions from the bus are broadcast, i.e., written to both heads, 102a and 102b, substantially simultaneously. Furthermore, in broadcast mode, the VGA data that are read from the bus always comes from head 102a (since both of the heads should have the same read data). Accordingly, the broadcast VGA mode allows a single screen surface to be displayed to two totally arbitrary displays with independent timing (CRT at 640x480x85Hz, FP at 1600x1200x60Hz scaled, etc.).
  • FIG. 4 is a flow chart illustrating a process for programming both VGA controllers simultaneously within the graphics display system in accordance with the present invention. Accordingly, in a system and method in accordance with the present invention, first the graphics application determines which heads within the display system are to be active, via step 302. Then, the custom timing for each head is provided, via step 304. In this mode, those settings which relate to the type of device (i.e., flat panel television, CRT, etc.) are set. Next, broadcast mode is entered and the VGA registers for all of the active heads are programmed through a single command, via step 306. Finally, control of the display system is returned to the graphics application for each of the particular heads, via step 308. Accordingly, a single command can be utilized for simultaneously programming or switching display modes on each of heads in a multiple head graphics display system.
  • the custom timing for each head is provided, via step 304. In this mode, those settings which relate to the type of device (i.e., flat panel television, CRT, etc.) are set.
  • a system and method for providing a broadcast mode VGA feature is disclosed.
  • a method and system in accordance with the present invention includes one VGA controller per head. In so doing, ina broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the CRT. The VGA application can then provide mode settings via the appropriate write VGA registers and the correct display will be on each head.

Abstract

A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller and each of the plurality of heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads could be programmed by a single command by the host. Each of the heads are adapted for a display. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the display devices. The VGA application can then provide mode settings via the appropriate write VGA registers and the correct display will be on each head.

Description

GRAPHICS SYSTEM INCLUDING A PLURALITY OF HEADS
FIELD OF THE INVENTION
The present invention relates generally to a graphics display system and more particularly to a graphics display system that includes a broadcast mode VGA feature.
BACKGROUND OF THE INVENTION
Typically in a graphics display system, it is desirable to be able to display the images to different types of displays. Conventional graphic display systems do allow displaying to a different display, but only if the timing is exactly the same for the displays. For example, in a conventional graphics display system, if a flat panel provides a 1600x1200x60 Hz scale image, a cathode ray tube (CRT) will display the same scale image. Typically this is accomplished utilizing a single head design which works for one display pipeline. To describe this single head design in more detail, refer now to Figure 1.
Figure 1 is a block diagram of a conventional graphics display system 10. The conventional graphics display system 10 includes a memory 12 which is in communication with a frame buffer interface 14. The system 10 includes a host 16 which receives programming signals from an AGP (or PCI) bus 18 which controls both a VGA controller 20 and a CRT controller 22. The VGA controller 20 retrieves information from and provides information to the frame buffer interface and communicates with the CRT controller 22 via register signals. The CRT controller 22 is coupled to pipeline 24. The VGA controller 20, CRT controller 22 and pipeline 24 comprise a single display head 40. In this single head system 10, the CRT controller 22 then provides data through a pipeline 24 to a plurality of displays, for example a CRT 26, fiat panel (FP) display 28 or a television 30. Each of the displays can be serially switched onto the single head graphics system 10 or all of the displays can simultaneously receive the signals from the graphics system 10.
A problem with the single head system is that, unless all of the displays are compatible, then there are timing issues associated therewith. Accordingly, the pipeline would require complex circuitry to ensure that these timing issues are addressed, which would significantly add to the cost of the graphics display system. The conventional graphics display system 10 works well with traditional panels (800x600, 1024x768) which use standard VESA timings. However, the mobile industry is moving aggressively towards large flat panels (1600x1200, 2048x1536) with non-standard timings.
In addition, the higher resolutions are not supported by most CRTs. If multiple displays are to be utilized simultaneously they must be coupled tightly together. This is oftentimes undesirable because the costs associated with circuitry to allow for compatibility is prohibitive.
Accordingly, what is needed is a system that overcomes the above-identified problems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A graphics display system is disclosed. The display system comprises a plurality of heads. Each of the plurality of heads includes a VGA controller. Each of the heads is adapted for a display. The graphics display system also includes a host coupled to the plurality of heads, wherein all the standard VGA settings for each of the plurality of the heads are programmed by a single command by the host. A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, in a broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA data read from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, the software sets up the timing in extended registers and enables the CRT. The VGA application can then provide mode settings via the appropriate write to VGA registers and the correct display will be on each head.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a conventional graphics display system.
Figure 2 is a block diagram of a graphics display system in accordance with the present invention.
Figure 3 is a diagram that illustrates areas for VGA register settings 202 and shadow state register settings 204 for the custom settings for the specific display.
Figure 4 is a flow chart illustrating a process for programming both VGA controllers simultaneously within the graphics display system in accordance with the present invention.
DETAILED DESCRIPTION
The present invention relates generally to a graphics display system and more particularly to a graphics display system that includes a plurality of heads. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
Figure 2 is a block diagram of a graphics display system 100 in accordance with the present invention. The graphics display system 100 includes first and second display heads 102a and 102b which can be individually programmed via the host 110. Each of the heads 102a and 102b are in-eommunication with a frame buffer interface 14'. Although two heads 102a and 102b are shown in accordance with the preferred embodiment, one of ordinary skill in the art readily recognizes that there can be any number of heads within the graphics system and that would be within the spirit and scope of the present invention.
Each head 102a and 102b is also in communication with the host 110 which receives programming signals from an AGP (or PCI) bus 18. The host 110 communicates with both of the CRT controllers 122a and 122b. The VGA controllers 120a and 120b retrieve information from and provide information to the frame buffer interface and communicate with its respective CRT controller, 122a orl22b, via register signals.
Each of the CRT controllers 122a and 122b then provides data through its respective pipeline 124a or 124b to a plurality of displays, for example, flat panel displays, TV and a CRT. The host 110, in a custom mode, provides programming signals to the CRT controllers 122a and 122b to provide the custom settings for the particular display (i.e., flat panel, television and/or CRT).
This allows each of those heads, 102a and 102b, to operate independently. The host 110 in a broadcast mode also provides a standard VGA programming signal 121, which sets the VGA register settings in both VGA controllers 122a and 122b. In so doing, the standard VGA programming signal 121 allows each of the heads 102a and 102b to be programmed simultaneously.
Figure 3 is a diagram that illustrates areas for VGA register settings 202 and shadow state register settings 204 for the custom settings for the specific display. In the shadow state register settings 204, which the VGA controller has no access to, the custom timing information for the particular display (i.e., a CRT, FP or TV) is stored. The host also provides the standard VGA settings for all of the active heads.
In a preferred embodiment, in broadcast VGA mode, the VGA write transactions from the bus are broadcast, i.e., written to both heads, 102a and 102b, substantially simultaneously. Furthermore, in broadcast mode, the VGA data that are read from the bus always comes from head 102a (since both of the heads should have the same read data). Accordingly, the broadcast VGA mode allows a single screen surface to be displayed to two totally arbitrary displays with independent timing (CRT at 640x480x85Hz, FP at 1600x1200x60Hz scaled, etc.).
To describe the present invention in more detail refer now to the following discussion in conjunction with the accompanying figures.
Figure 4 is a flow chart illustrating a process for programming both VGA controllers simultaneously within the graphics display system in accordance with the present invention. Accordingly, in a system and method in accordance with the present invention, first the graphics application determines which heads within the display system are to be active, via step 302. Then, the custom timing for each head is provided, via step 304. In this mode, those settings which relate to the type of device (i.e., flat panel television, CRT, etc.) are set. Next, broadcast mode is entered and the VGA registers for all of the active heads are programmed through a single command, via step 306. Finally, control of the display system is returned to the graphics application for each of the particular heads, via step 308. Accordingly, a single command can be utilized for simultaneously programming or switching display modes on each of heads in a multiple head graphics display system.
A system and method for providing a broadcast mode VGA feature is disclosed. A method and system in accordance with the present invention includes one VGA controller per head. In so doing, ina broadcast mode a write transaction from the bus is broadcast or written to both heads. Also, in a broadcast mode, the VGA read data from the bus always comes from one of the heads. The output timing registers specific to a non-CRT output are not broadcast. To provide broadcast VGA to a CRT and/or a flat panel, software sets up the timing in extended registers and enables the CRT. The VGA application can then provide mode settings via the appropriate write VGA registers and the correct display will be on each head.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. A graphics display system comprising: a plurality of heads, each of the plurality of heads including a VGA controller, each of the plurality of heads adapted for a display; and a host coupled to the plurality of heads, wherein the standard VGA settings for each of the plurality of heads are programmed by a single command by the host.
2. The graphics display system of claim 1 wherein each of the plurality of heads includes a CRT controller coupled to the VGA controller, a pipeline coupled to the CRT controller, and a display coupled to the pipeline.
3. The graphics display system of claim 1 wherein the host programs each of the VGA controllers in a broadcast mode.
4. The graphics display system of claim 2 wherein the host reads data from one of the VGA controllers when in a broadcast mode.
5. The graphics display system of claim 1 wherein the host provides custom timing signals for each of the plurality of heads dependent upon the display when in a custom mode.
6. The graphics display system of claim 1 wherein the display can be any of the following: a CRT display, a flat panel display and a television.
7. A graphics display system comprising: a plurality of heads, each of the plurality of heads including a VGA controller, a CRT controller coupled to the VGA controller and a pipeline coupled to the CRT controller and a display coupled to the pipeline; each of the plurality of heads adapted for a display; and a hostcoupled to the plurality of heads, wherein the standard VGA settings for each of the plurality of heads are programmed by a single command by the host, wherein the host programs each of the VGA controllers in a broadcast mode.
8. The graphics display system of claim 7 wherein the host reads data from one of the VGA controllers when in a broadcast mode.
9. The graphics display system of claim 8 wherein the host provides custom timing signals for each of the plurality of heads dependent upon the display when in a custom mode.
10. The graphics display system of claim 7 wherein the display can be any of the following: a CRT display, a flat panel display and a television.
11. A graphics display system comprising: a first head, the first head including a first VGA controller, a first CRT controller coupled to the first VGA controller and a first pipeline coupled to the first CRT controller, the first head adapted for a first display; a second head, the second head including a second VGA controller, a second CRT controller and a second pipeline coupled to the second CRT controller; the second head adapted for a second display; and a host for sending commands to the first and second heads, the host in a custom mode for sending commands individually to the first and second heads for the first and second displays; the host in a_broadcast mode for sending a command to first and second VGA controllers to simultaneously program the VGA settings for the first and second VGA controllers.
12. The graphics display system of claim 2 wherein the host reads data from one of the first and second VGA controllers when in a broadcast mode.
13. The graphics display system of claim 1 wherein the first and second displays can be any of the following: a CRT display, a flat panel display and a television.
14. A method for programming a plurality of heads within a graphics display system; the method comprising the steps of:
(a) providing custom timing in a first mode for each of the plurality of heads; and
(b) providing a single command in a second mode to all of the plurality of heads to program all of the standard VGA settings in all of the heads.
15. The method of claim 14 which includes the step of:
(c) returning control of the display system to a graphics application.
16. The method of claim 14 wherein in the second mode the plurality of heads are programmed substantially simultaneously.
17. The method of claim 15 wherein the first mode comprises a custom mode and the second mode comprises a broadcast mode.
PCT/US2002/016929 2001-06-07 2002-05-30 Graphics system including a plurality of heads WO2002101711A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/877,462 US7095386B2 (en) 2001-06-07 2001-06-07 Graphics system including a plurality of heads
US09/877,462 2001-06-07

Publications (1)

Publication Number Publication Date
WO2002101711A1 true WO2002101711A1 (en) 2002-12-19

Family

ID=25370012

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/016929 WO2002101711A1 (en) 2001-06-07 2002-05-30 Graphics system including a plurality of heads

Country Status (2)

Country Link
US (2) US7095386B2 (en)
WO (1) WO2002101711A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095386B2 (en) * 2001-06-07 2006-08-22 Nvidia Corporation Graphics system including a plurality of heads
US6832269B2 (en) * 2002-01-04 2004-12-14 Silicon Integrated Systems Corp. Apparatus and method for supporting multiple graphics adapters in a computer system
US20060036775A1 (en) * 2004-08-16 2006-02-16 Konstantin Levit-Gurevich Apparatus and methods for video graphics array (VGA) virtualization in system exploiting multiple operating systems
US8453148B1 (en) 2005-04-06 2013-05-28 Teradici Corporation Method and system for image sequence transfer scheduling and restricting the image sequence generation
US8766993B1 (en) * 2005-04-06 2014-07-01 Teradici Corporation Methods and apparatus for enabling multiple remote displays
SG137754A1 (en) 2006-05-12 2007-12-28 Nvidia Corp Antialiasing using multiple display heads of a graphics processor
US8073990B1 (en) 2008-09-23 2011-12-06 Teradici Corporation System and method for transferring updates from virtual frame buffers
US8224885B1 (en) 2009-01-26 2012-07-17 Teradici Corporation Method and system for remote computing session management
US8410994B1 (en) 2010-08-23 2013-04-02 Matrox Graphics Inc. System and method for remote graphics display
US9250683B2 (en) 2013-03-14 2016-02-02 Nvidia Corporation System, method, and computer program product for allowing a head to enter a reduced power mode

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204864B1 (en) * 1995-06-07 2001-03-20 Seiko Epson Corporation Apparatus and method having improved memory controller request handler
US6219040B1 (en) * 1997-08-11 2001-04-17 Cirrus Logic, Inc. CRT to FPD conversion/protection apparatus and method

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0271626B1 (en) * 1986-12-16 1992-03-04 International Business Machines Corporation Bypass mechanism for daisy chain connected units
JPH01248185A (en) * 1988-03-30 1989-10-03 Toshiba Corp Display controller
US6215459B1 (en) * 1993-10-01 2001-04-10 Cirrus Logic, Inc. Dual display video controller
US5500654A (en) * 1993-12-27 1996-03-19 Kabushiki Kaisha Toshiba VGA hardware window control system
US5414831A (en) * 1993-12-30 1995-05-09 Lsi Logic Corporation Apparatus and method for accessing a plurality of computer devices having a common address
US5488385A (en) * 1994-03-03 1996-01-30 Trident Microsystems, Inc. Multiple concurrent display system
US5841418A (en) * 1995-06-07 1998-11-24 Cirrus Logic, Inc. Dual displays having independent resolutions and refresh rates
US5694141A (en) * 1995-06-07 1997-12-02 Seiko Epson Corporation Computer system with double simultaneous displays showing differing display images
US5786825A (en) * 1995-12-13 1998-07-28 National Semiconductor Virtual display subsystem in a computer
US6333750B1 (en) * 1997-03-12 2001-12-25 Cybex Computer Products Corporation Multi-sourced video distribution hub
US6023281A (en) * 1998-03-02 2000-02-08 Ati Technologies, Inc. Method and apparatus for memory allocation
US20020003507A1 (en) * 1999-02-26 2002-01-10 Robert D. Dodge Dual mode digital video interface and remote lcd monitor
US6424320B1 (en) * 1999-06-15 2002-07-23 Ati International Srl Method and apparatus for rendering video
US6628243B1 (en) * 1999-12-09 2003-09-30 Seiko Epson Corporation Presenting independent images on multiple display devices from one set of control signals
US7095386B2 (en) * 2001-06-07 2006-08-22 Nvidia Corporation Graphics system including a plurality of heads

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204864B1 (en) * 1995-06-07 2001-03-20 Seiko Epson Corporation Apparatus and method having improved memory controller request handler
US6219040B1 (en) * 1997-08-11 2001-04-17 Cirrus Logic, Inc. CRT to FPD conversion/protection apparatus and method

Also Published As

Publication number Publication date
US7095386B2 (en) 2006-08-22
US20020186218A1 (en) 2002-12-12
US7633461B1 (en) 2009-12-15

Similar Documents

Publication Publication Date Title
US7633461B1 (en) Graphics system including a plurality of heads
US4642794A (en) Video update FIFO buffer
US6583771B1 (en) Display controller for controlling multi-display type display, method of displaying pictures on multi-display type display, and multi-display type information processing system
US7242370B2 (en) Display apparatus, method of controlling the same, and multidisplay system
US7667708B2 (en) Display controller, electronic instrument, and method of supplying image data
US8199136B2 (en) Image data transmission apparatus and method for image display system
US4642789A (en) Video memory controller
US20010006375A1 (en) Host device, image display device, image display system, image display method, panel attribute reading-out method and image display control method
EP1418495A2 (en) Display controller permitting connection of multiple displays with a single video cable
JPH06214550A (en) Equipment and method for provision of frame buffer memory for output display of computer
US5293474A (en) System for raster imaging with automatic centering and image compression
US6825845B2 (en) Virtual frame buffer control system
US20010022587A1 (en) Display device and image displaying method on display device
US20010043206A1 (en) Display control device
US20060055626A1 (en) Dual screen display using one digital data output
US6115032A (en) CRT to FPD conversion/protection apparatus and method
US6121949A (en) Method and apparatus for automatically maintaining a predetermined image quality in a display system
KR100472633B1 (en) Display device, video controller unit, and method for displaying images
JP2002032063A (en) Liquid crystal display device and method for controlling window display magnification
EP0422300B1 (en) Display system with graphics cursor
CN100397471C (en) Driver module and driving method of display with multi-path display output
US7006713B1 (en) Image-processing apparatus and image-displaying apparatus
CN103631548A (en) Image external-connection device and method for processing image external-connection device
US7432991B1 (en) Random access display monitor
JP2001516897A (en) Apparatus for controlling a plurality of display devices, a system having this device and an associated method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP