WO2002101919A1

WO2002101919A1 - Distortion compensating device

Info

Publication number: WO2002101919A1
Application number: PCT/JP2001/004931
Authority: WO
Inventors: Kazuo Nagatani; Tokuro Kubo; Hiroyoshi Ishikawa; Yasuyuki Oishi; Takayoshi Ode; Hajime Hamada; Nobukazu Fudaba
Original assignee: Fujitsu Limited
Priority date: 2001-06-12
Filing date: 2001-06-12
Publication date: 2002-12-19

Abstract

A distortion compensating device for compensating for the distortion of a transmission signal by means of a distortion compensation coefficient and inputting the signal into a distortion device comprises a distortion compensation coefficient storage section where a distortion compensation coefficient is stored in accordance with the transmission signal, an error signal storage section where an error signal which is the error between the transmission signal and a feedback signal and related to the transmission signal is stored, and a distortion compensation coefficient calculating section which adaptively calculates a new value of the distortion compensation coefficient in accordance with the transmission signal by using the distortion compensation coefficient and error signal stored in the distortion compensation coefficient storage section and distortion compensation coefficient storage section respectably and updates the value of the distortion compensation coefficient stored in the distortion compensation coefficient storage section.

Description

Specification

Distortion compensator

Technical field

The present invention relates to a distortion compensating device, and more particularly to a distortion compensating device capable of reducing the number of shift registers for timing adjustment and reducing the circuit scale.

Background art.

In recent years, frequency resources have become tight, and high-efficiency transmission by digitization has been widely used in wireless communication. When applying multi-level phase modulation to wireless communication, it is important to reduce the adjacent channel leakage power by reducing the nonlinear distortion by linearizing the amplification characteristics of the transmission side, especially the power amplifier, and it is inferior in linearity. When using an amplifier to improve power efficiency, it is essential to have a technology that compensates for the occurrence of distortion.

FIG. 15 is a block diagram showing an example of a transmission device in a conventional radio, in which a transmission signal generator 1 transmits a serial digital data string, and a serial-to-parallel converter (S / P converter). In step 2, the digital data stream is alternately distributed one bit at a time and converted into a two-system system (J) of an in-phase component signal (I signal: In-phase component) and a quadrature component signal (Q signal: Quadrature component). 3 converts the I signal and the Q signal into analog baseband signals and inputs the signals to the quadrature modulator 4. The quadrature modulator 4 receives the input I signal and Q signal (transmission baseband signal). The frequency converter 5 performs a quadrature transformation by multiplying the reference carrier by a signal obtained by shifting the phase by 90 ° and adding the multiplication results, and outputs the result.The frequency converter 5 mixes the quadrature modulation signal and the local oscillation signal. Frequency conversion Power amplifier 6 emits a carrier wave outputted from the frequency converter 5 into the air from the antenna (antenna) 7 amplifies the power.

In mobile communications such as W-CDMA and PDC (Personal Digital Cellular), the transmission power of the transmitting device is large, and the input / output characteristics (distortion function f (p)) of the transmission power amplifier 6 are indicated by the dotted line in (a) of FIG. Becomes non-linear as shown by. This nonlinear characteristic causes nonlinear distortion, and the transmission frequency f. As shown by the solid line in Fig. 16 (b), the peripheral frequency spectrum raises the side lobe, leaks to the adjacent channel, and causes adjacent interference. That is, as shown in (b), the power that the transmitted wave leaks to the adjacent frequency channel increases due to the nonlinear distortion. The leakage power becomes noise with respect to other channels, This degrades the communication quality of the channel. Therefore, it is strictly regulated. Here, the leakage power is small in the linear region of the power amplifier (see (a) in Figure 16) and large in the nonlinear region. For this reason, in order to obtain a high-output transmission power amplifier, it is necessary to widen the linear region, and it is necessary to prepare an amplifier having a capacity exceeding the actually required capacity, which is disadvantageous in cost and equipment size. There is a problem. Therefore, a radio device (linearizer) with a distortion compensation function that compensates for distortion in transmission power and realizes the use of an amplifier in a region where power load efficiency is high.

FIG. 17 is a block diagram of a transmission apparatus having a digital nonlinear distortion compensation function using a DSP (Digital Signal Processor). The digital data group (transmission signal) transmitted from the transmission signal generator 1 is converted into two series of I signal and Q signal in the S / P converter 2 and input to the distortion compensator 8 composed of DSP. Is done. The distortion compensator 8 stores the distortion compensation coefficient h (pi) (i = 0 to 1023) corresponding to the power level 0 to 1023 of the transmission signal X (t), as shown in FIG. 18. Distortion compensation coefficient storage unit 8a, predistortion unit 8b that performs distortion compensation processing (predistortion) on the transmission signal using distortion compensation coefficient h (pi) corresponding to the transmission signal level, transmission signal X ( t) is compared with the demodulated signal (feed pack signal) y (t) demodulated by the quadrature detector described later, and the distortion compensation coefficient h (pi) is calculated and updated so that the difference becomes zero. A compensation coefficient calculation unit 8c is provided. The distortion compensator 8 performs a pre-distortion process on the transmission signal using a distortion compensation coefficient h (pi) corresponding to the power level of the transmission signal X (t), and inputs the signal to the DA converter 3. The D A converter 3 converts the input I signal and Q signal to an analog baseband signal and inputs the signal to the quadrature modulator 4. The quadrature modulator 4 multiplies the input I signal and Q signal by a reference carrier and a signal obtained by shifting the phase by 90 °, and adds the multiplication results to perform quadrature modulation and output the result. The frequency converter 5 mixes the quadrature modulated signal and the local oscillation signal to convert the frequency, and the transmission power amplifier 6 amplifies the power of the carrier signal output from the frequency converter 5 and puts it into the air from the antenna 7. Radiate.

A part of the transmission signal is input to the frequency converter 10 via the directional coupler 9, where the frequency is converted and input to the quadrature detector 11. The quadrature detector 11 performs quadrature detection by multiplying the transmitted signal by the reference carrier and a signal obtained by shifting the phase by 90 °, and reproduces the I and Q signals of the baseband on the transmitting side to convert the A / D converter 1 2 To enter. The AD converter 12 converts the input I and Q signals into digital signals and inputs them to the distortion compensator 8. The distortion compensator 8 compares the transmission signal before distortion compensation with the feedpack signal demodulated by the quadrature detector 11 by adaptive signal processing using an LMS (Least Mean Square) algorithm, and the difference is zero. Calculate and update the distortion compensation coefficient h (pi) so that Next, pre-distortion processing is performed on the next transmission signal to be transmitted using the updated distortion compensation coefficient, and the signal is output. Thereafter, by repeating the above operation, the nonlinear distortion of the transmission power amplifier 6 is suppressed, and the adjacent channel leakage power is reduced.

FIG. 19 is an explanatory diagram of a distortion compensator (adaptive predistorter) using adaptive LMS. 1 5 a transmission signal X (t) to the distortion compensation coefficient h _n - a (p) a multiplier for multiplying the (corresponding to Puridisu Tosho emission portion 8 b of FIG. 18), 1 5 b is distortion function f (p) 15 c is a feedback system that feeds back the output signal y (t) from the transmission power amplifier, and 15 d calculates the power p (= X (t) ² ) of the transmission signal _X (t). The calculation unit (amplitude-to-power conversion unit), 15 e is a distortion compensation coefficient storage unit that stores a distortion compensation coefficient corresponding to each power of the transmission signal X (t) (the distortion compensation coefficient storage unit 8 a in FIG. 18). And outputs a distortion compensation coefficient h _n- "p" corresponding to the power p of the transmission signal x (t), and a distortion compensation coefficient h _n (p) determined by the LMS algorithm. h _n — ^ p) is updated.

15 f is a conjugate signal output unit, 15 g is a subtractor that outputs the difference e (t) between the transmission signal X (t) and the feedback demodulation signal y (15 h is e (t) and u * (t) Multiplier, 15 i is a multiplier that multiplies h _n — i ( _P ) and y * (t), 15 j is a multiplier that multiplies the step size parameter, 15 k Is an adder that adds h _n-丄 (p) and e (t) u * (t), 15 m, 15 n, 15 ρ is a delay unit (shift register), and the transmission signal x ( The delay time from the input of t) to the input of the feedback demodulated signal y (t) to the subtractor 15 g is added to the transmission signal. This constitutes 16. u (t) is a signal subjected to distortion, and the following operation is performed by the above configuration.

h _n (p) = h _n _! (p) + μ e (t) u * (t)

e (t) = x (t) -y (t)

y (t) = h _n _! (p) x (t) f (p)

u (t) = x (t) f (p) = h y (t)

P = I x (t) I ² Here, x, y, f, h, u, and e are complex numbers, and * is a complex conjugate number. By performing the above arithmetic processing, the distortion compensation coefficient h (p) is updated so that the difference e (t) between the transmission signal X (t) and the feedback demodulation signal y (t) is minimized, and Eventually, it converges to the optimal distortion compensation coefficient value, and the distortion of the transmission power amplifier is compensated. .

FIG. 20 is an overall configuration diagram of the transmitting apparatus expressed as X (t) = I (t) + jQ (t), and the same reference numerals are assigned to the same parts as in FIGS. 17 and 19. ing.

As described above, in the digital nonlinear distortion compensation method, the carrier obtained by orthogonally modulating the transmission signal is feedback-detected, and the amplitude of the transmission signal and the feedback signal are digitally converted and compared, and based on the comparison result, The principle is that the distortion compensation coefficient is updated in real time. According to this nonlinear distortion compensation method, distortion can be reduced, and as a result, it is possible to suppress the leakage power even when operating in a non-linear region with a high output, and to improve the power load efficiency.

In a distortion compensator such as an adaptive predistorter that performs distortion compensation using a feedback signal, a modulated signal output from a DA converter (including a quadrature modulator) is AD-converted and subtracted by a subtractor. It passes through an analog filter, up-convert mixer, transmission power amplifier, down-convert mixer, analog filter, etc. before being fed back to g. For this reason, the feedpack signal has a delay inherent in each analog element between the DA converter and the AD converter. Since the distortion compensator updates the distortion compensation coefficient using the error signal that is the result of the comparison operation between the feed pack signal and the reference signal, it is necessary to use a delay section (shift register) for timing adjustment at each location. There is. In particular, a shift register 15n (Fig. 19) used to feed back the distortion compensation coefficient, and a timing adjustment to generate an address when the updated distortion compensation coefficient is written to the distortion compensation coefficient storage unit 15e 15 m shift register for reference signal generation to be compared with the feedback signal.15 p is used when delay is added due to change of analog element or when digital signal processing speed is increased. And the circuit scale of the device increases. Of these, shift register 15η shifts 48-bit data in parallel, so the longer the delay time of the feedback signal becomes, the larger it becomes.

From the above, it is an object of the present invention to reduce the number of shift registers required for a distortion compensator. And reduce the circuit scale.

Another object of the present invention is to solve the problem caused by reducing the number of shift registers, stabilize the convergence of the distortion compensation coefficient, and generate the same effect of distortion compensation as before.

Disclosure of the invention

The present invention provides a distortion compensation process for a transmission signal using a distortion compensation coefficient, inputs the signal to a distortion device, and calculates a difference between the transmission signal before distortion compensation and a feedback pack signal fed back from an output side of the distortion device. Is a distortion compensation device that adaptively calculates a distortion compensation coefficient based on the error signal, and stores the calculated distortion compensation coefficient in association with the transmission signal power. (1) Distortion compensation according to the transmission signal power A distortion compensation coefficient storage unit that stores coefficients; (2) a distortion compensation unit that performs a distortion compensation process on a transmission signal by using a distortion compensation coefficient corresponding to the power of the transmission signal; A signal delay section for delaying the transmission signal until a signal to be fed-packed from the output side of the distortion device arrives; (4) a difference between the delayed transmission signal output from the signal delay section and the feedback signal; Calculate the error signal An operation unit; (5) an error signal storage unit that stores the error signal in accordance with the power of the transmission signal output from the signal delay unit; (6) the distortion compensation coefficient storage unit and the error signal storage unit according to the transmission signal power And a distortion compensation coefficient calculating unit that adaptively calculates the distortion compensation coefficient using the distortion compensation coefficient and the error signal stored in the memory and updates the old distortion compensation coefficient. As described above, in addition to the distortion compensation coefficient storage unit that stores the distortion compensation coefficient, the error signal storage unit that stores the error signal that is the difference between the reference signal (delayed transmission signal) and the feed pack signal is provided. The distortion compensation coefficient is adaptively calculated using the distortion compensation coefficient and the error signal corresponding to the transmission signal power stored in the distortion compensation coefficient storage section and the error signal storage section, respectively. Since the coefficients are updated, the number of shift registers required for the distortion compensator can be reduced, and the circuit scale can be reduced. That is, the shift register used for feedback of the distortion compensation coefficient lin conventionally required, and the address generation timing adjustment for writing the updated distortion compensation coefficient into the distortion compensation coefficient storage unit. The shift register becomes unnecessary.

The distortion compensation coefficient calculation unit of the distortion compensation apparatus of the present invention includes a distortion compensation coefficient convergence unit that can converge the distortion compensation coefficient even when transmission signals having the same power value continuously arrive. You. The distortion compensation coefficient convergence means stores, for example, the correspondence between the power value of the transmission signal and the step size parameter () used in the adaptive operation, and outputs a step size parameter corresponding to the transmission signal power value. Means for appropriately calculating a distortion compensation coefficient using the step size parameter and updating the old distortion compensation coefficient in the distortion compensation coefficient storage unit. In this way, even if the error signal is large, the step size parameter can be made small, so that even if transmission signals of the same power arrive continuously, the distortion compensation coefficient does not depart from the expected value. And converge to a constant value. That is, it is possible to solve the problem caused by reducing the number of shift registers, stably converge the distortion compensation coefficient, and achieve the same effect as the conventional one.

Also, the distortion compensating apparatus of the present invention includes a training signal generating section for generating a training signal, an initial training signal input to the distortion compensating section, and a transmission when the average value of the error signal becomes equal to or less than a set value. Signal switching means for inputting a signal to the distortion compensation unit. In this way, the convergence of the distortion compensation coefficient can be performed stably, and the power consumption of the device can be suppressed.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a configuration diagram of a distortion compensation device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a distortion compensation device according to a second embodiment of the present invention.

FIG. 3 is a diagram for explaining that the distortion compensation coefficient does not converge.

FIG. 4 is an explanatory view of the principle of the second embodiment.

FIG. 5 is an explanatory diagram of the probability of occurrence of transmission signal power.

FIG. 6 is a configuration diagram of a distortion compensation device according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a distortion compensation coefficient convergence unit using a force counter. FIG. 8 is a configuration diagram of a distortion compensating apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a configuration diagram of a distortion compensation device according to a fifth embodiment of the present invention.

FIG. 10 is a flowchart for explaining the processing timing of the fifth embodiment.

FIG. 11 is a configuration diagram of a distortion compensation apparatus according to a sixth embodiment of the present invention.

FIG. 12 is an explanatory diagram of the duty of the pulse signal.

FIG. 13 is a configuration diagram of a distortion compensation apparatus according to a seventh embodiment of the present invention.

FIG. 14 is a configuration diagram of a distortion compensating apparatus according to an eighth embodiment of the present invention. FIG. 15 is a configuration diagram of a conventional transmission device.

FIG. 16 is an explanatory diagram of a problem due to the nonlinearity of the transmission power amplifier.

FIG. 17 is a configuration diagram of a transmission device having a conventional digital nonlinear distortion compensation function. <FIG. 18 is a functional configuration diagram of a distortion compensation unit.

FIG. 19 is an explanatory diagram of distortion compensation processing by adaptive LMS.

FIG. 20 is an overall configuration diagram of a transmission device that expresses a transmission signal X (t) in a complex manner.

BEST MODE FOR CARRYING OUT THE INVENTION

(A) First embodiment

Figure 1 is a block diagram of a distortion compensating apparatus of the first embodiment of the present invention, 101 the distortion compensation coefficient storage unit that stores a distortion compensation coefficient h _n (p) in accordance with the power P of the transmission signal X (t) (Dual-port RAM: DRAM), 102 is a distortion compensation unit (multiplication unit) that multiplies the transmission signal x (t) by a distortion compensation _coefficient h _n (p) corresponding to the transmission signal power, and 103 Is the time from the arrival of the transmission signal X (t) to the arrival of the feedback signal y (t) from the output 'side of the distortion device, the signal delay part of the shift register configuration that delays the transmission signal, 104 is an error signal operation unit that calculates an error signal e (t) which is a difference between the transmission signal (reference signal) output from the signal delay unit 103 and the feed pack signal y (t), and 105 is an error signal e (t). ) And the quadrant signal of the feedback signal y (t) are stored in correspondence with the power of the transmission signal output from the signal delay unit. Report RAM: DPRAM), 106 is a distortion compensation coefficient operation unit, which performs distortion compensation according to the power P of the transmission signal X (t) stored in the distortion compensation coefficient storage unit 101 and the error signal storage unit 105, respectively. The distortion / compensation coefficient storage unit 101 computes the distortion compensation coefficient h _{n + 1} (p) adaptively using the coefficient h _n (p), the error signal e _n , the quadrant signal y _n , and the step size parameter. Update the old distortion compensation coefficient h _n (p) of.

108 is a DA converter having a DA converter, a quadrature modulator, a frequency upconverter, etc., 109 is a transmission power amplifier which is a distortion device, and 110 is a part for extracting and outputting a part of a transmission signal. A combiner, 111 is a feedback system that feeds back a transmission signal to a distortion compensator, 112 is an AD converter, which has a frequency downconverter, a quadrature demodulator, an AD converter, etc., 113 is a transmission signal An address generation unit that generates the power P as an address of the distortion compensation coefficient storage unit 101, and 114 sets the power of the delayed transmission signal output from the signal delay unit 103 as the address of the error signal storage unit 105. hand The generated address generator 115 is a flip-flop delay circuit that delays the address signal by the time required for the distortion compensation coefficient calculation of the distortion compensation coefficient calculator 106, for example, for one clock period.

In the distortion compensation coefficient calculation unit 106, 106 a rotation calculation unit for outputting the _{_e} η · u η *, 106b is a multiplier for multiplying the stearyl Step Size parameter μ to the rotation calculating unit output signal, 106c is h _n (p ) and an adder for adding the μ e _{_n} · u _n *.

When the transmission signal (t) is input, the address generation unit 113 calculates the power value P of the transmission signal, and inputs the power value P as an address to the distortion compensation coefficient storage unit 101 and the error signal storage unit 105. . The distortion compensation coefficient storage unit 101 inputs the distortion compensation coefficient h _n (p) from the address P designated by the address generation unit 113 to the distortion compensation unit 102. Distortion compensating unit 102 outputs the transmission signal x (t) is multiplied by a distortion compensation coefficient h _n (p). The DA converter 108 performs DA conversion, modulation, and frequency up-comparison processing on the distortion-compensated transmission signal, and inputs the signal to the transmission power amplifier 108. The transmission power amplifier 108 amplifies the transmission signal and radiates it from an antenna (not shown). The directional coupler 110 extracts a part of the transmission signal and inputs it to the A / D converter 112. The A / D converter performs frequency down-comparison, demodulation, and A / D conversion processing to provide a feedback signal y (t). Is input to the error signal calculation unit 104.

In parallel with the above, the error signal storage unit 105 outputs the error signal e „and the quadrant signal y from the address P specified by the address generation unit 113. The distortion compensation coefficient calculator 106 calculates the following equation h„ + (p) = h „(ρ) + μ e _n . u _n (1)

, The old distortion compensation coefficient h _n (p) stored in the address P of the distortion compensation storage unit 101 is updated with h _n (p).

Further, the signal delay unit 103 delays the transmission signal (t) by a set time and inputs the transmission signal (t) to the address generation unit 114 and the erroneous signal calculation unit 104. The error signal calculation unit 104 calculates an error signal e (t) which is a difference between the transmission signal delayed by the signal delay unit 103 and the feedback signal. The address generation unit 114 calculates the power value P of the transmission signal delayed by the signal delay unit 103, and inputs the power value P as an address to the error signal storage unit 105. The error signal storage unit 105 stores the quadrant signal of the error signal e (t) and the feedback signal y (t) input from the error signal calculation unit 104 at the address specified by the address generation unit 114. .

In summary, according to the first embodiment, the distortion compensation coefficient storage unit 101 stores the transmission signal x (t). The distortion compensation process is performed using the distortion compensation coefficient h _n (p) read from the error signal e _n , the error signal e _n already stored in the error signal storage unit 105, the quadrant signal y _n, and the distortion compensation coefficient h _n (p) is used to calculate a new distortion compensation coefficient h _n + i (p), and the old distortion compensation coefficient h _n (p) in the distortion compensation coefficient storage unit 101 is calculated using the distortion compensation coefficient hn + 1 (p). To update. If the delay time is Td, the error signal e (t) based on the distortion compensation result this time and the quadrant signal are stored in the error signal storage unit 105 after the delay time Td from the input of the transmission signal X (t). I do. As a result, the shift register (delay unit 15n in Fig. 19) used to feed back the distortion compensation coefficient h _n (p), which was conventionally required, to the distortion compensation coefficient operation unit 106, and the updated distortion When writing the compensation coefficient h _{n +}丄 (p) into the distortion compensation coefficient storage unit 101, the shift register (the delay unit 15m in Fig. 19) for adjusting the address generation timing can be deleted.

In the first embodiment, it is necessary to newly provide the error signal storage unit 105 as compared with the related art. However, removing the two shift registers increases the amount of hardware reduction and can reduce the circuit scale.

(B) Second embodiment

FIG. 2 is a configuration diagram of a distortion compensating apparatus according to a second embodiment of the present invention, and the same parts as those in the first embodiment in FIG. The difference from the first embodiment is that (1) the correspondence between the power value P of the transmission signal X) and the step size parameter ^ to data μ used in the adaptive operation is stored in the memory 106e of the step size parameter control unit 106d. (2) Step size The parameter control unit 106d obtains and outputs the step size parameter corresponding to the power value P of the transmission signal from the memory 106e, and the distortion compensation coefficient calculation unit 106 uses this step size parameter UL. adaptively Ibitsuto償係number h _n + t (p) the (1) is a point to update by Ri calculated by the formula.

In the distortion compensating apparatus of the first embodiment, the distortion compensation coefficient of the distortion compensation coefficient storage unit 101 is updated using the error signal stored in the error signal storage unit 105. However, there is a delay of Td from when the distortion compensation coefficient in the distortion compensation coefficient storage unit 101 is updated to when the old error signal is updated with a new error signal that is a distortion compensation result. Therefore, if a transmission signal having the same power is continuously input a plurality of times during this delay time Td, the distortion compensation coefficient is updated a plurality of times using the old error signal. At this time, if the error signal is large, the distortion compensation coefficient is far from the expected value and does not converge. FIG. 3 is a diagram illustrating that the distortion compensation coefficient does not converge. And time equal transmission signal power is continuously input to the distortion compensating apparatus during Td, using the same old error signal e _n to the distortion compensation coefficient hn (p) of the same § dress Remind as in FIG. 3 Will be updated continuously. As a result, if a large error signal e _n is written to the error signal storage unit 105, the value is updated using that value, so that the distortion compensation coefficient becomes h „(p) → hn + 1 () → ·· → h „+ 1 (Ρ) 'and does not converge. That is, if the error signal is large,

(1) the second term on the right side of the coefficient update base-vector μ e _{_n.} U _η * becomes large, updating a plurality of times the distortion compensation coefficients successively with this coefficient updating solid Torr distortion compensation coefficient h _{eta +} (Ρ) 'is far from the expected value h _{π +} i (ρ) shown by the dotted line. By the way, even when transmission signals having the same power value are continuously input to the distortion compensator during the time T d, if the step size parameter μ is small, as shown in FIG. 4, the distortion compensation coefficient h _n + 1 (ρ) 'can be converged without being far from the expected update value h _η + i (ρ).

Therefore, in the second embodiment, the occurrence probability of the transmission signal power is determined in advance (see Fig. 5), and as shown in Fig. 2, a small μ is assigned to the power value that has a high appearance frequency and is likely to be continuously input. it relies coefficient update base-vector e _n with. rather small values of u _n *, contrary to low frequency, the large μ is the power value is less likely to continuously input, i.e., the normal value Assign a close value. This makes it possible to stably converge the distortion compensation coefficient.

(C) Third Embodiment ′ FIG. 6 is a configuration diagram of a distortion compensating apparatus according to a third embodiment of the present invention, and the same parts as those in the first embodiment in FIG. The difference from the first embodiment is that a distortion compensation coefficient convergence section 120 having a counter configuration is provided. As described in the second embodiment, in the distortion compensating apparatus of the first embodiment, when a transmission signal having the same power is continuously input multiple times during the delay time Td, the distortion compensation is performed using the old error signal. Since the coefficient is updated a plurality of times, the distortion compensation coefficient does not converge if the error signal is large. That is, before the time T d required from the update of the distortion compensation coefficient to the storage of a new error signal in the error signal storage unit 105 elapses, the distortion compensation of the same address in the distortion compensation coefficient storage unit 101 is performed. If the coefficient update operation is performed multiple times, the distortion compensation coefficient will not converge well. Therefore, in the third embodiment, a distortion compensation coefficient convergence unit 120 having a counter configuration is provided, and the coefficient update timing is monitored for each address of the distortion compensation coefficient storage unit 101. FIG. 7 is a configuration diagram of the distortion compensation coefficient collecting unit 120, 121 is an address generating unit 113, an address decoder for decoding an output address, and 122a to 122ii are counters provided for each address. Is a counter overflow detection unit that detects overflow of each counter unit and outputs a write enable signal WE. Each of the counter units 122a to 122n has a counter start determination unit 131 and a counter 132.

The counter start determination unit 131 generates a count start signal Restart when the address generation unit 113 generates its own address (the address access signal is at a high level) in a state where an overflow has already occurred from its own counter. Then, the counter 132 starts counting clock pulses in response to the count start signal Restart. When a predetermined number of clock pulses are counted, an overflow occurs, an overflow pulse is generated, and the counting is stopped thereafter.

When an address is generated from the address generation section 113, the counter overflow detection section 123 checks whether the counter section corresponding to the address has overflown, and if an overflow has occurred, generates a write enable signal WE and generates a write enable signal WE. If not, the write enable signal WE is not generated. If write rice one enable signal WE is generated, the distortion compensation coefficient Symbol憶部101 distortion compensation coefficient input from the distortion compensation coefficient calculation unit 1 06 h _{n + 1} (p) in the old distortion compensation coefficient h _n a (p) Update. However, if the write Ineburu signal WE is generated, distortion compensation coefficient h _{n + 1} the distortion compensation coefficient storage unit 101 inputs the distortion compensation coefficient calculation unit 106 the old distortion compensation coefficient h _n in (p) (p) updating do not do.

As described above, after the distortion compensation coefficient is written at a predetermined address of the distortion compensation coefficient storage unit 101, if the set number of clock pulses are counted, in other words, the address can be written after the set time has elapsed, and thereafter, the address can be written. When the address is generated by the generation unit 113, a write enable signal WE is generated, and the distortion compensation coefficient can be written to the distortion compensation coefficient storage unit 110. However, after writing the distortion compensation coefficient to a predetermined address of the distortion compensation coefficient storage unit 101, if the set time has not yet elapsed, writing to the address becomes impossible, and the address is generated by the address generation unit 113. However, the write enable signal WE does not occur and the distortion compensation coefficient cannot be written to the distortion compensation coefficient storage unit 110.

As described above, according to the third embodiment, there are a plurality of transmission signals having the same power during the delay time Td. Even if the input is performed consecutively, the distortion compensation coefficient is updated only once, so that the distortion compensation coefficient can be kept far from the expected value and can be converged to a constant value.

(D) Fourth embodiment

FIG. 8 is a configuration diagram of a distortion compensating apparatus according to a fourth embodiment of the present invention, and the same parts as those in the first embodiment in FIG. The difference from the first embodiment is that a distortion compensation coefficient convergence section 150 having a memory configuration is provided. In the distortion compensating apparatus of the first embodiment, if a transmission signal having the same power is input multiple times continuously during the delay time Td, the distortion compensation coefficient is updated multiple times using the old error signal. Therefore, if the error signal is large, the distortion compensation coefficient does not converge. That is, before the time T d required from the update of the distortion compensation coefficient to the storage of a new error signal in the error signal storage unit 105 elapses, the same address in the distortion compensation coefficient storage unit 101 is stored. When the work of updating the distortion compensation coefficient is performed a plurality of times, the distortion compensation coefficient does not converge well.

Therefore, in the fourth embodiment, a distortion compensation coefficient convergence unit 150 having a memory configuration is provided, and a coefficient update time is recorded for each address of the distortion compensation coefficient storage unit 101 to monitor the coefficient update timing. That is, a reference timer is prepared, and when a distortion compensation coefficient at a predetermined address in the distortion compensation coefficient storage unit 101 is updated, an update time is stored in a memory in association with the address. Then, the latest update time stored in the memory is compared with the current time indicated by the reference timer, and only when the difference (elapsed time) exceeds a threshold value, for example, the delay time Td, the distortion compensation coefficient of the address is updated. Make it possible. The distortion compensation coefficient convergence unit 150 includes a timer 151 that indicates a reference time, an update time storage unit 152 that records the update time of the distortion compensation coefficient stored at each address of the distortion compensation coefficient storage unit 101, A time difference calculation unit 153 that calculates a time difference Δ の between the update time and the current time, compares the time difference Δ ΐ with the threshold Τ thr, and outputs a write enable signal WE when A t ^ Tt hr, and outputs a signal A t <T thr A comparison unit 154 which does not output the write enable signal WE and a delay circuit 155 which delays the address generated from the address generation unit 113 by one clock time are provided.

When an address is generated from the address generation unit 113, the distortion compensation coefficient h _n (p) is read from the address in the distortion compensation coefficient storage unit 101, and distortion compensation is performed as in the first embodiment. Also, the distortion compensation coefficient calculation unit 106 calculates the distortion compensation coefficient h _{n +1} (p) according to the equation (1) and inputs it to the distortion compensation coefficient storage unit 101.

When an address is generated from the address generation unit 113, the latest update time is read from the address in the update time storage unit 152, and the time difference calculation unit 153 calculates the time difference Δ between the update time and the current time. Computing t, the comparator 154 outputs the write enable signal WE when At≥Tthr, and does not output the write enable signal WE when At <Tthr. Thus the distortion compensation coefficient storage unit 101 updates the A t the distortion compensation coefficient input from the correction coefficient arithmetic operator 106 if Tthr h _{n + 1} (p) in the old strain complement償係number h _n (p). However, delta if ΐ rather Tthr, the distortion compensation coefficient storage unit 101 updates the old distortion compensation coefficient in distortion compensation coefficient h _{n + 1} input from the distortion compensation coefficient calculator _{1 0 6 (p) h n} (p) do not do.

As described above, after the distortion compensation coefficient is written at a predetermined address of the distortion compensation coefficient storage unit 101, the address can be written after a set time has elapsed, and thereafter, when the address is generated by the address generation unit 113, the write enable signal WE is output. Is generated, and the distortion compensation coefficient h _{n +} ^ p) can be written to the distortion compensation coefficient storage unit 110. However, after writing the distortion compensation coefficient at a predetermined address in the distortion compensation coefficient storage unit 101, writing to the address becomes impossible if the set time has not yet elapsed, and the address generation unit 113 generates the address. Also, the write enable signal WE is not generated, and the distortion compensation coefficient hn _{+ 1} (p) cannot be written to the distortion compensation coefficient storage unit 110.

As described above, according to the fourth embodiment, even if a transmission signal having the same power is input a plurality of times continuously during the delay time Td, the distortion compensation coefficient is updated only once, so that the distortion compensation coefficient is updated only once. Can be kept far from the expected value and can be converged to a constant value.

(E) Fifth embodiment

FIG. 9 is a configuration diagram of a distortion compensating apparatus according to a fifth embodiment of the present invention, and the same parts as those in the first embodiment of FIG. The difference from the first embodiment is that a distortion compensation coefficient convergence section 160 is provided. In the distortion compensating apparatus of the first embodiment, when a transmission signal having the same power is continuously input multiple times during the delay time Td, the distortion compensation coefficient is updated multiple times using the old error signal. Therefore, if the error signal is large, the distortion compensation coefficient does not converge. That is, before the time Td required from the time when the distortion compensation coefficient is updated to the time when a new error signal is stored in the error signal storage unit 105 elapses, the distortion of the same address in the distortion compensation coefficient storage unit 101 is obtained. If the update of the compensation coefficient is performed several times, the distortion compensation coefficient does not converge well.

Therefore, in the fifth embodiment, a compensation coefficient convergence unit 160 having a pulse generation unit 161 that generates a pulse signal PL having a duty of 50% and a predetermined period (for example, 2 × Td) is provided. However, duty = (ON period / pulse period) × 100 (%). As shown in the flowchart of FIG. 10, when the pulse signal PL is at the high level, the error signal is stored only in the error signal storage unit (error signal table) 105. When the pulse signal PL is at a low level, the distortion compensation coefficient is stored in a distortion compensation coefficient storage unit (distortion compensation coefficient table) 101, and the error signal is read from a predetermined address of the error signal storage unit 105. In such a case, 0 is written to the address.

When the pulse signal PL is at a high level and an address generator 113 generates an address, the distortion compensation coefficient h _n (p) is read from the address in the distortion compensation coefficient storage unit 101, and the same as in the first embodiment. Is subjected to distortion compensation. Also, the distortion compensation coefficient calculation unit 106 calculates the distortion erosion coefficient hn _{+ 1} (p) according to equation (1) and inputs the calculated value to the distortion compensation coefficient storage unit 101. Since the pull signal WE is not input, the distortion compensation coefficient hn _{+ 1} (p) is not stored in the distortion compensation coefficient storage unit 101.

A part of the output of the power amplifier 109 is fed back and converted into a digital signal by the AD converter 112, and the error signal calculator 104 calculates the error signal e (t). When the pulse signal PL is at the high level, the selectors 162 and 163 select the quadrant data of the error signal e (t) and the feed pack signal y (t) and input them to the error signal storage unit 105. Since the selector 164 selects the address output from the address generator 114 and inputs it to the error signal storage 105, the error signal e (t) and quadrant data are sequentially stored in the address of the error signal storage 105. Is done. On the other hand, when the address is generated from the address generation unit 113 when the pulse signal PL is at the low level, the distortion compensation coefficient h _n (p) is read from the address in the distortion compensation coefficient storage unit 101 and the distortion compensation is performed. It is. Further, the address generating unit 113 mosquitoes ^ address is generated, the error signal e _n from the Adore scan of the error signal storage unit 105, it is read out quadrant data y _n is input to the distortion compensation coefficient calculation unit 106. The distortion compensation coefficient calculator 106 calculates the distortion compensation coefficient hn _{+ 1} (p) according to the equation (1), and inputs the calculated value to the distortion compensation coefficient storage 101. When the pulse signal PL is at the low level, the write enable signal WE is input to the distortion compensation coefficient storage unit 101, so that the distortion compensation coefficient hn _{+ 1} (p) is written to the address, and the old distortion compensation The coefficient h _n (p) is updated. When the pulse signal PL is at a low level, the selectors 162 and 163 select zero and input them to the error signal storage unit 105, and the selector 164 receives the input from the address generation unit 113 via the delay circuit 165. The error signal e _n and the quadrant data y _n are once read out from the address of the error signal storage unit 105 since the address to be selected is input to the error signal storage unit 105. Is written to zero. This zero writing prevents the distortion compensation coefficient at the same address from being updated more than once when the pulse signal PL is at a single level. A flag is set for the accessed address, and the next access is It is also possible to configure so that the value of the address is not used when the lag is raised. As described above, when the pulse signal PL is in the low-level distortion compensation coefficient update state, the distortion compensation coefficient is updated only once, even if the transmission signal having the same power is continuously input multiple times. Coefficients can be prevented from deviating from expected values, and can be converged to a constant value.

(F) Sixth embodiment

FIG. 11 is a configuration diagram of a distortion compensating apparatus according to a sixth embodiment of the present invention, and the same parts as those in the fifth embodiment in FIG. The difference from the fifth embodiment is that (1) the pulse signal generator 161 can change the duty of the pulse signal PL, and (2) the error signal power decreases when the distortion compensation coefficient converges. The point is to increase the duty by increasing the ON period as the error signal power decreases by monitoring the average value of the power. The operation is performed at a duty of 50% in the process of pulling in the distortion compensation coefficient.

The power calculator 166 calculates the error signal power of the error signal e (t) output from the error calculator 104, the comparator 167 outputs the difference between the error power and the threshold power, and the averaging unit 168 calculates the average value of the difference power. The pulse signal generator 16 1 monitors the average power value and increases the on-period as shown in Figs. 12 (a), (b) and (c) as the error signal power decreases. To increase the duty. After the distortion compensation coefficient converges to a constant value and the error signal power decreases, the updating of the distortion compensation coefficient is stopped to maintain the distortion compensation coefficient at the constant value and compensate for the distortion. it can. When the error signal power increases, the updating of the distortion compensation coefficient is restarted.

(G) Seventh embodiment

FIG. 13 is a configuration diagram of a distortion compensating apparatus according to a seventh embodiment of the present invention. The same parts as those in the first embodiment of FIG. The differences from the first embodiment are as follows: (1) At the initial stage, the training signal sequence is input to the distortion compensator until the distortion compensation coefficient converges. (2) When the distortion compensation coefficient converges, the training signal The point is that the transmission signal is input to the distortion compensation device instead of the sequence.

201 is a training signal generator that generates a training signal sequence, 202 is the initial training signal sequence that is input to the distortion compensator 102, and when the average value of the error signal falls below the set value, the transmission signal x (t) is A switch input to the distortion compensator 102, a power calculator 203 for calculating the error signal power, and an average calculator 204 for calculating the average of the error signal power. In the training signal sequence, it is necessary to consider that signals of the same power do not occur continuously. training Since the error signal power of the comparison result becomes smaller when the distortion compensation coefficient converges due to the switching signal sequence, when the average value of the error signal power becomes smaller than the set value, the switch unit 202 trains the signal input to the distortion compensator. Switch from signal sequence to transmission signal x (t).

According to the seventh embodiment, the convergence of the distortion compensation coefficient can be performed stably, and the power consumption of the distortion compensation device can be reduced.

(G) Eighth embodiment

FIG. 14 is a configuration diagram of the distortion compensating apparatus according to the eighth embodiment of the present invention, and the same parts as those in the first embodiment in FIG. The following two points are different from the first embodiment. The first difference is that when a transmission signal X (t) is input and an address corresponding to the power of the transmission signal is generated from the address generation section 113, the distortion compensation coefficient section storage section 101 stores an error. The distortion compensation coefficient h _n (p), the error signal e _n , and the quadrant signal y _n are input to the distortion compensation coefficient storage unit 301 from the address of the signal storage unit 105, and the distortion compensation coefficient storage unit 301 The distortion compensation coefficient h _n + i (p) is calculated according to the equation (1) and input to the distortion compensation unit 102. The distortion compensation unit 102 calculates the distortion compensation _coefficient ¾ h _n +! The point is that distortion is compensated based on (p). The second difference is that calculates the difference between the previous error signal stored in the error signal present error signal calculated by the arithmetic unit 10 ⁴ and the error signal memory 105 in the comparison unit 302, the average value Is calculated by the average value calculation unit 303.If the average value of the difference is small, the distortion compensation coefficient and the error signal are regarded as converging, and the distortion compensation coefficient storage unit 101 and the error signal storage unit 105 are updated. First, when the average value of the differences becomes large, the storage contents of the storage units 101 and 105 are updated.

According to the eighth embodiment, the provision of the distortion compensation coefficient calculator 301 as compared with the first embodiment allows the error signal to be reflected on the distortion compensation coefficient earlier, and the distortion compensation coefficient is used as the distortion compensation coefficient. The distortion can be compensated by inputting to the unit 102. After the distortion compensation coefficient converges to a constant value and the error signal power decreases, the distortion compensation coefficient can be maintained at the constant value and the distortion can be compensated by stopping the updating of the distortion compensation coefficient. . When the error signal power increases, the updating of the distortion compensation coefficient is restarted.

As described above, according to the eighth embodiment, since the distortion compensation coefficient calculation unit 301 is provided, it is possible to input a distortion compensation coefficient reflecting an error signal to the distortion compensation unit earlier than in the first embodiment to perform distortion compensation. it can. Also, according to the eighth embodiment, after the distortion compensation coefficient converges to a constant value and the error signal power decreases, the updating of the distortion compensation coefficient is stopped by stopping the distortion compensation coefficient. Distortion can be compensated while maintaining a constant value. When the error signal power increases, the update of the distortion compensation coefficient is restarted.

As described above, according to the present invention, the number of shift registers required for the distortion compensator can be reduced, and the circuit scale can be reduced. In particular, the effect of reduction when the delay of the analog element is large is great.

Also, according to the present invention, even when transmission signals having the same power value are input continuously, the distortion compensation coefficient can be made to converge, and the disadvantage caused by reducing the number of shift registers can be eliminated to eliminate the distortion compensation coefficient. Can be stably converged, and the same effect of distortion compensation as in the past can be obtained.

Claims

The scope of the claims

1. The difference between the transmitted signal before distortion compensation and the feedback signal fed-packed from the output side of the distortion device after distortion compensation processing is applied to the transmission signal using the distortion compensation coefficient and input to the distortion device. A distortion compensation device that adaptively computes a distortion compensation coefficient based on an error signal and stores the computed distortion compensation coefficient in association with a transmission signal.

A distortion compensation coefficient storage unit that stores a distortion compensation coefficient according to a transmission signal,

A distortion compensation unit that performs a distortion compensation process on a transmission signal using a distortion compensation coefficient corresponding to the transmission signal;

An error signal storage unit for storing an error signal, which is a difference between a transmission signal before distortion compensation and a feed pack signal fed from an output side of the distortion device, in association with the transmission signal;

The distortion compensation coefficient is adaptively calculated using the distortion compensation coefficient corresponding to the transmission signal and the error signal stored in the error signal storage unit according to the transmission signal, and the distortion compensation coefficient of the distortion compensation coefficient storage unit is calculated. A distortion compensation coefficient calculation unit to be updated,

A distortion compensating device comprising:

2. An arithmetic unit for calculating the error signal,

A signal delay unit for delaying the transmission signal and inputting it to the error signal calculation unit during a period from when the transmission signal is input to when the feedback signal reaches the error signal calculation unit. The distortion compensator according to claim 1, wherein

3. The distortion compensation coefficient storage unit and the error signal storage unit store the distortion compensation coefficient and the error signal according to the power value of the transmission signal, and the distortion compensation coefficient calculation unit receives the transmission signal of the same power continuously. However, it has distortion compensation coefficient convergence means for converging the distortion compensation coefficient to a constant value.

-The distortion compensator according to claim 1 or 2, wherein:

4. The distortion compensation coefficient convergence means stores the correspondence between the power value of the transmission signal and the step size parameter (μ) used in the adaptive operation, and outputs the step size parameter according to the power value of the transmission signal. The distortion compensation coefficient calculating unit adaptively calculates a distortion compensation coefficient using the step size parameter and updates a distortion compensation coefficient of the distortion compensation coefficient storage unit; 4. The distortion compensator according to claim 3, wherein:

5. The distortion compensation coefficient convergence means includes a counting means according to the power value of the transmission signal, and when the distortion compensation coefficient of the predetermined power value is updated, the clock pallet is counted by the counting means according to the power value. And updating of the distortion compensation coefficient according to the power value is prohibited until the count value of the counter reaches the set value.

4. The distortion compensator according to claim 3, wherein:

6. The distortion compensation coefficient collecting means includes a timer indicating a reference time, and update time storage means for recording an update time of the distortion compensation coefficient according to a power value of a transmission signal, and the update time according to a predetermined power value. When the difference between the reference time and the reference time is equal to or less than a set time, updating of the distortion compensation coefficient corresponding to the power value is prohibited.

4. The distortion compensator according to claim 3, wherein:

7. The distortion compensation coefficient convergence means includes a pulse signal generation unit that periodically generates a high-level and low-level pulse signal, and sets the distortion compensation coefficient storage unit to a light-to-naple state when the pulse signal is at one level. When the distortion compensation coefficient corresponding to the predetermined power value is updated, the error signal in the error signal storage unit corresponding to the power value is set to zero, and when the pulse signal is at the other level, the error signal is stored in the error signal storage unit. Means,

4. The distortion compensating device according to claim 3, comprising:

8. The pulse signal generating section varies a period of one level of the pulse signal based on an average value of the error signal,

8. The distortion compensator according to claim 7, wherein:

9. A training signal generator that generates a training signal,

Signal switching means for inputting a training signal at the initial stage to the distortion compensating unit, and for inputting a transmission signal to the distortion compensating unit when an average value of the error signal is equal to or less than a set value,

3. The distortion compensating device according to claim 1, comprising:

10.An error signal, which is the difference between the transmission signal before distortion compensation and the feedback signal fed back from the output side of the distortion device, after performing distortion compensation processing on the transmission signal using the distortion compensation coefficient and inputting it to the distortion device. A distortion compensation coefficient that is adaptively calculated based on the following, and the calculated distortion compensation coefficient is stored in association with the transmission signal.

A distortion compensation coefficient storage unit that stores a distortion compensation coefficient according to a transmission signal, A distortion compensation unit that performs distortion compensation processing on the transmission signal using the distortion compensation coefficient,

An error signal calculation unit that calculates an error signal that is a difference between a transmission signal before distortion compensation and a feedback signal fed-packed from an output side of the distortion device;

A signal delay unit for delaying the transmission signal and inputting the resulting signal to the error signal calculation unit for a period of time from when the distortion compensation processing is performed on the transmission signal to when the feed pack signal arrives at the error signal calculation unit;

An error signal storage unit that stores the error signal in association with the transmission signal output from the signal delay unit;

A distortion compensation coefficient is adaptively calculated using the distortion compensation coefficient and the error signal stored in the distortion compensation coefficient storage section and the error signal storage section, respectively, in accordance with a transmission signal, and input to the distortion compensation section. 1 distortion compensation coefficient calculator,

The distortion compensation coefficient is adaptively calculated using the distortion compensation coefficient and the error signal stored in the distortion compensation coefficient storage unit and the error signal storage unit according to the transmission signal output from the signal delay unit, and the error is calculated. When the difference between the error signal output from the signal operation unit and the error signal stored in the error signal storage unit is equal to or greater than a set value, the distortion compensation coefficient in the compensation coefficient storage unit is updated with the calculated distortion compensation coefficient. A second distortion compensation coefficient calculator,

A distortion compensating device comprising: