WO2002103800A3 - Integration of two memory types - Google Patents

Integration of two memory types Download PDF

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Publication number
WO2002103800A3
WO2002103800A3 PCT/US2002/014440 US0214440W WO02103800A3 WO 2002103800 A3 WO2002103800 A3 WO 2002103800A3 US 0214440 W US0214440 W US 0214440W WO 02103800 A3 WO02103800 A3 WO 02103800A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectrics
tunnel
semiconductor substrate
integration
memory types
Prior art date
Application number
PCT/US2002/014440
Other languages
French (fr)
Other versions
WO2002103800A2 (en
Inventor
Robert E Jones
Bruce E White
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2002259157A priority Critical patent/AU2002259157A1/en
Priority to KR10-2003-7016432A priority patent/KR20040007728A/en
Priority to JP2003506010A priority patent/JP2005520318A/en
Priority to EP02729146A priority patent/EP1402577A2/en
Publication of WO2002103800A2 publication Critical patent/WO2002103800A2/en
Publication of WO2002103800A3 publication Critical patent/WO2002103800A3/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Abstract

Both a non-volatile memory (NVM) and a dynamic nanocrystal memory (DNM) are integrated on a semiconductor substrate. Control gates and control dielectrics with embedded nanocrystals or discrete storage elements are formed over differing thicknesses of tunnel dielectrics to form the two memories. Source and drain regions are formed within the semiconductor substrate adjacent to the tunnel dielectrics. Various methods can be used to form a thin tunnel oxide and a thick tunnel oxide by adding minimum processing steps.
PCT/US2002/014440 2001-06-15 2002-05-07 Integration of two memory types WO2002103800A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002259157A AU2002259157A1 (en) 2001-06-15 2002-05-07 Integration of two memory types
KR10-2003-7016432A KR20040007728A (en) 2001-06-15 2002-05-07 Integration of two memory types on the same integrated circuit
JP2003506010A JP2005520318A (en) 2001-06-15 2002-05-07 Integration of two memory types on the same integrated circuit
EP02729146A EP1402577A2 (en) 2001-06-15 2002-05-07 Integration of two memory types

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/881,332 2001-06-15
US09/881,332 US6531731B2 (en) 2001-06-15 2001-06-15 Integration of two memory types on the same integrated circuit

Publications (2)

Publication Number Publication Date
WO2002103800A2 WO2002103800A2 (en) 2002-12-27
WO2002103800A3 true WO2002103800A3 (en) 2003-06-05

Family

ID=25378257

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/014440 WO2002103800A2 (en) 2001-06-15 2002-05-07 Integration of two memory types

Country Status (8)

Country Link
US (2) US6531731B2 (en)
EP (1) EP1402577A2 (en)
JP (1) JP2005520318A (en)
KR (1) KR20040007728A (en)
CN (1) CN100362663C (en)
AU (1) AU2002259157A1 (en)
TW (1) TW541664B (en)
WO (1) WO2002103800A2 (en)

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US8927370B2 (en) * 2006-07-24 2015-01-06 Macronix International Co., Ltd. Method for fabricating memory
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Also Published As

Publication number Publication date
JP2005520318A (en) 2005-07-07
TW541664B (en) 2003-07-11
CN1509501A (en) 2004-06-30
KR20040007728A (en) 2004-01-24
US6790727B2 (en) 2004-09-14
CN100362663C (en) 2008-01-16
AU2002259157A1 (en) 2003-01-02
US20020190343A1 (en) 2002-12-19
EP1402577A2 (en) 2004-03-31
US20030132500A1 (en) 2003-07-17
US6531731B2 (en) 2003-03-11
WO2002103800A2 (en) 2002-12-27

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