WO2003041158A3 - Semiconductor package device and method of formation and testing - Google Patents

Semiconductor package device and method of formation and testing Download PDF

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Publication number
WO2003041158A3
WO2003041158A3 PCT/US2002/033083 US0233083W WO03041158A3 WO 2003041158 A3 WO2003041158 A3 WO 2003041158A3 US 0233083 W US0233083 W US 0233083W WO 03041158 A3 WO03041158 A3 WO 03041158A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
testing
package device
formation
semiconductor package
Prior art date
Application number
PCT/US2002/033083
Other languages
French (fr)
Other versions
WO2003041158A2 (en
Inventor
Mark A Gerber
Shawn M O'connor
Trent A Thompson
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to JP2003543094A priority Critical patent/JP2005535103A/en
Priority to AU2002337875A priority patent/AU2002337875A1/en
Priority to EP02773779A priority patent/EP1481421A2/en
Publication of WO2003041158A2 publication Critical patent/WO2003041158A2/en
Publication of WO2003041158A3 publication Critical patent/WO2003041158A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

A package device (10, 100) has one integrated circuit (22, 122) in a cavity (20, 120) in a package substrate (12. 122) and electrically coupled to one side (50, 150) of the package substrate. A second integrated circuit (32, 132) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit (38, 138) or more may be mounted on the second integrated circuit. Pads (16, 116, 116) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.
PCT/US2002/033083 2001-11-08 2002-10-16 Semiconductor package device and method of formation and testing WO2003041158A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003543094A JP2005535103A (en) 2001-11-08 2002-10-16 Semiconductor package device and manufacturing and testing method
AU2002337875A AU2002337875A1 (en) 2001-11-08 2002-10-16 Semiconductor package device and method of formation and testing
EP02773779A EP1481421A2 (en) 2001-11-08 2002-10-16 Semiconductor package device and method of formation and testing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/008,800 US6916682B2 (en) 2001-11-08 2001-11-08 Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing
US10/008,800 2001-11-08

Publications (2)

Publication Number Publication Date
WO2003041158A2 WO2003041158A2 (en) 2003-05-15
WO2003041158A3 true WO2003041158A3 (en) 2003-10-23

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PCT/US2002/033083 WO2003041158A2 (en) 2001-11-08 2002-10-16 Semiconductor package device and method of formation and testing

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Country Link
US (1) US6916682B2 (en)
EP (1) EP1481421A2 (en)
JP (1) JP2005535103A (en)
KR (1) KR100926002B1 (en)
CN (1) CN100477141C (en)
AU (1) AU2002337875A1 (en)
TW (1) TWI260076B (en)
WO (1) WO2003041158A2 (en)

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US20030085463A1 (en) 2003-05-08
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