WO2003049488A1

WO2003049488A1 - Interface to operate groups of inputs/outputs

Info

Publication number: WO2003049488A1
Application number: PCT/US2002/038482
Authority: WO
Inventors: Oluf Bagger
Original assignee: Vitesse Semiconductor Company; Tagore-Brage, Jens P.; Thomsen, Bo B.
Priority date: 2001-12-03
Filing date: 2002-12-03
Publication date: 2003-06-12
Also published as: AU2002365837A1

Abstract

An interface comprising a plurality of means for serializing parallel data,(10) each serializing means being adapted to output a serial data signal,(70), first means for providing a plurality of independent first parallel data, (10) one first parallel data for each serializing means, second means for providing second parallel data, for dividing the second parallel data into a plurality of third parallel data and for providing a third parallel data (10) to each of the serializing means, and means for aligning and/or synchronizing serial data signals output from the serializing means in order to obtain a predetermined timing relationship between the plurality of serial data signals.

Description

INTERFACE TO OPERATE GROUPS OF INPUTS/OUTPUTS

The present application hereby claims priority under 35 U.S.C. §119 on US patent publication number 60/338,274 filed December 3, 2001 , the entire contents of which are hereby incorporated by reference.

The present invention relates to an interface and a switch having the interface, where the interface may be used for both one or more higher data rate communications and a larger number of lower rate data communications.

Currently, high-speed Ethernet ports are either dedicated 10 GbE or 1 GbE, each interface requiring a different number of pins on a chip. One aspect of this invention relates to how to reduce the necessary pin-count on multi-rate chips having both such interfaces.

That aspect of the present invention relates to the use of one standardized interface to support also a plurality of other interfaces using the same inputs/outputs.

The data to be transported on the interface may be provided in any form. Presently, it is preferred that the data is in XG Ml I format (32 bit serial data interface) for 10Gbit/s Ethernet data traffic and GMII for the lower bit rate traffic. On the actual interface, the 10Gbit/s data is preferably transmitted as a XAUI signal and four iGbit/s signals are transmitted as serial communication. Naturally, it is also preferred that data received on the interface be transmitted in those formats.

In general, this represents a bonus compared to previous multi-rate Ethernet (industry) standards, where one high-speed port is degraded to a single low-speed port.

The main advantage is to the Customer, who will be able to configure each port of e.g. a switch or MAC into either 10 GbE mode or into a set of 1 GbE ports. For the manufacturer, the benefits are:

- The ability to use the same macro for several purposes. - The reduction in chip runs, testing, and stock gained from folding multiple chips into one. A first aspect of the invention relates to an interface comprising:

- a plurality of means for serializing parallel data, each serializing means being adapted to output a serial data signal, - first means for providing a plurality of independent first parallel data, one first parallel data for each serializing means,

- second means for providing second parallel data, for dividing the second parallel data into a plurality of third parallel data and for providing a third parallel data to each of the serializing means, and - means for aligning and/or synchronizing serial data signals output from the serializing means in order to obtain a predetermined timing relationship between the plurality of serial data signals.

In the present context, the aligning and/or synchronizing is an alignment or synchronizing in time so that a predetermined timing relationship exists between the data input and/or output. Preferably, aligned/synchronized signals will be operated at a common frequency and using a common data protocol.

Also, providing signals which are independent of each other will mean that the data represented is to be, or can meaningful be, interpreted independently.

Thus, individual data may be provided, serialized, transmitted etc. at e.g. different frequencies and some individual data may be treated independently of each other while others may be aligned/synchronized.

Preferably, the aligning/synchronizing means are adapted to not align/synchronize serial data signals output from the serializing means when receiving the first parallel data. In that manner, the individual first parallel data may be transmitted individually - such as with different or just free running clock frequencies.

Normally, the data will be presented as either a constant stream of data or as separate packets/frames/cells. Parallel data may represent a full packet/frame/cell across the width thereof - or a packet/frame/cell may be transmitted over a number of clock cycles on the parallel bus.

A second aspect of the invention relates to an interface comprising: - a plurality of means for serializing parallel data, each serializing means being adapted to output a serial data signal,

- first means for providing a plurality of independent first parallel data, one first parallel data for each serializing means, - second means for providing second parallel data, for dividing the second parallel data into a plurality of third parallel data and for providing a third parallel data to each of the serializing means, and

- means for aligning and/or synchronizing the third parallel data in order to obtain a predetermined timing relationship between the plurality of third serial data signals.

Preferably the aligning/synchronizing means are adapted to be disabled - such as when the first providing means are active.

It is presently preferred that the first and second providing means are not operated concurrently or simultaneously - so that only one of the first and second parallel data are provided to the serializing means at the time.

In the preferred embodiment, the first providing means is adapted to output each first parallel data along a first parallel data bus having a first predetermined number of conductors, wherein the second providing means is adapted to output the second parallel data along a second data bus having a second predetermined number of conductors, and wherein the first and second data busses have at least one conductor in common.

In this situation, the dividing of the second parallel data may simply be the dividing of the conductors of the second bus into a plurality of groups of conductors.

Preferably, the first predetermined number of conductors differs from the second number of conductors, and the first parallel data busses could be comprised in the second parallel data bus.

In fact, the plurality of serializing means times the first predetermined number of conductors is preferably identical to the second predetermined number of conductors.

It is desired that the first providing means is adapted to output first parallel data conforming to the GMII standard, wherein the second providing means could be adapted to output second parallel data conforming to the XGMII standard, and the serializing means be adapted to output a plurality of serial data signals conforming to the XAUI or the Infiniband standards - such as when the serial signals thereof are aligned. Otherwise, the output of the serializing means may be independently running serial communication - such as for communication over a plurality of SERDES connections or optical fibers.

Another aspect of the invention relates to an interface comprising:

- a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, - means for aligning/synchronizing the serial data signals prior to deserialization in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled, means for, when the aligning/synchronizing means are not disabled, combining the parallel data relating to deserialized aligned/synchronized serial signals into a single parallel piece of data or a single parallel stream of data.

A fourth aspect relates to an interface comprising:

- a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data,

- means for aligning/synchronizing the plurality of parallel data in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled,

- means for, when the aligning/synchronizing means are not disabled, combining the aligned/synchronized parallel data into a single parallel piece of data or a single parallel stream of data.

In the third and fourth aspects, preferably, the deserializing means are adapted to output each parallel data along a first parallel data bus having a first predetermined number of conductors, wherein combining means is adapted to output the single parallel data along a second data bus having a second predetermined number of conductors, and wherein the first and second data busses have at least one conductor in common. Again, the first predetermined number of conductors may differ from the second number of conductors. Also, the first parallel data busses are preferably comprised in the second parallel data bus, and the plurality of deserializing means times the first predetermined number of conductors is desirably identical to the second predetermined number of conductors. In the preferred embodiment, the deserializing means are adapted to output first parallel data conforming to the GMII standard, wherein the combining means is adapted to output second parallel data conforming to the XGMII standard, and wherein the deserializing means are adapted to receive a plurality of serial data signals conforming to the XAUI or the Infiniband standards (when alignment makes sense - or else the data may be independent free running communication).

Preferably, in all the above aspects of the invention, a means for providing a clocking signal for use in the serializing/deserializing means is provided. This clocking providing means could be adapted to provide a clocking signal having one of two clocking signal frequencies, where a clocking signal having one of the clocking signal frequencies is provided when each group of inputs/outputs are operated independently of each other and the other of the clocking signal frequencies is provided when the aligning means is operated. The one and the other clocking frequencies are preferably selected from the group consisting of 3.25 GHz, 1.25 GHz, and 2.5 GHz. The frequency of the one signal could be 1.25 GHz and the frequency of the other signal could be 3.25 GHz or 2.5 GHz.

It should be noted that the disabling of the aligning/synchronizing means may simply be means which route or transfer data around or "not via" the aligning/synchronizing means. Thus, an aligning/synchronizing means may be fully operable all the time - but it the disabling means may cause no data to be transmitted thereto, whereby it will, in effect, have no "apparent" operation. Alternatively, the first or second providing means and/or the combining means may be constantly operated at all times, where the routing/transferring of data simply routes the correct data to and from the serializing/deserializing means.

A fifth aspect of the invention relates to a communication system comprising a first interface according to the first or second aspects and a second interface according to the third or fourth aspects and means for transporting the plurality of serial signals from the first interface to the second interface, the system comprising means for processing the plurality of parallel data and/or the single parallel data output by the second interface, the processing means being adapted to process the plurality of parallel data independently of each other.

This system could be adapted to be operated in one of two modes of operation, comprising: - a first mode of operation wherein the aligning/synchronizing means of the first and second interfaces are operated, and a second mode of operation wherein the aligning/synchronizing means of the first and second interfaces are disabled. These two modes of operation will be one receiving/transmitting one stream of data or a single piece of data (at a point in time) or one receiving/transmitting a plurality of independent streams or pieces of data (at a point in time) - using the same serializing/deserializing means and the same transporting means.

Another aspect of the invention relates to a method of operating the interface of any of the first to fourth aspects, the method comprising:

- determining whether the serial data signal(s) to be received and/or output is/are to be aligned and/or synchronized and - operating the aligning/synchronizing means accordingly.

Then, the determining step might comprise determining an overall data rate to be output or input via the interface and aligning/synchronizing the data if the data rate exceeds a predetermined threshold. Thus, the number of paths or connections to external computers, networks, network elements, chips or the like may be tailored as may the overall bandwidth of the system. Trunking may be used to reduce the number of connections or to increase the bandwidth - and this combined with the present choice of data rate and number of connections brings about a very powerful tailoring tool.

Thus, the determining step may comprise determining an overall data rate of the plurality of serial data signals and operating the aligning/synchronizing means if the data rate exceeds a predetermined threshold.

Naturally, the opposite situation, where e.g. the quality of one of the serial "channels" has a maximum possible data rate lower than others, a higher data rate may be obtained by not "locking" the data rates of the paths but allowing the other data rates to be higher than that possible by the "lower quality" data path.

Yet another aspect relates to a method of operating the interface according to the third or fourth aspects, the method comprising: altering between two modes of operation wherein: in a first mode of operation, the deserializing means receive data independently of each other and output the parallel data independently of each other, and - in a second mode of operation, the single parallel data is output. The invention also relates to a method of operating the interface according to the first or second aspects, the method comprising: altering between two modes of operation wherein:

- in a first mode of operation, the serializing means receive the first parallel data independently of each other and output the serial data independently of each other, and

- in a second mode of operation, the plurality of serial data signals output have the predetermined timing relationship.

An important aspect of the invention relates to a switch having: - a number of devices each comprising an interface according to the first or second aspect and an interface according to the third or fourth aspect and each being adapted to receive a plurality of serial data signals from and output a plurality of serial data signals to one or more network connections, a data bus on which the devices are adapted to interchange data,

wherein at least one of the devices is adapted to alter between operation in one of at least two modes of operation comprising:

- a first mode of operation wherein the device is adapted to receive serial data signals from and transmit serial data signals to a first number of network connections via the interface, and

- a second mode of operation wherein the device is adapted to receive serial data signals from and transmit serial data signals to a second number of network connections via the interface, the second number being higher than the first number.

In the present context, a "network connection" would be a connection for data communication to one or more computers or computer networks, such as the WWW or Internet, a single computer, and everything there between.

Preferably, the at least one device comprises a processing means adapted to process the data received from the interface before transmission to the data bus, the processing means being adapted to alter between operation in one of at least two modes of operation comprising:

a first mode of operation wherein the means is adapted to process the data from each of the first number of network connections independently of each other, and a second mode of operation wherein the means is adapted to process the data from the second number of network connections independently of each other.

This processing of the data will depend on the actual use of the switch. A processing may be the checking for errors, performing standardization or normalization of the data, determining where the data is to be transmitted to (such as using a look-up table) or from where it comes, what type of data it is, and what priority it has. Other processing is alteration of the data, such as converting an encapsulation of the packet, removing, adding or replacing parts of the data, and correcting e.g. errors in the data.

In this situation, the processing means may comprise, in the second mode of operation, separate memory for each of the second number of independent processes and logic shared between the second number of independent processes. Thus, a saving in logic may be obtained. This may be obtained by either synthesizing VHDL code from all processing processes into a single block in e.g. a chip

Thus, also through the processing means, the data to or from the paths of the interface may be treated independently of each other.

Preferably, the processing means comprises, in the second mode of operation, separate memory for each of the second number of independent processes and logic shared between the second number of independent processes.

Also, the at least one device preferably further comprises a storage means adapted to store data between receipt thereof at the interface and transmission thereof on the bus, the storage means being adapted to alter between operation in one of at least two modes of operation comprising:

a first mode of operation for use when the device operates in its first mode of operation and wherein the storage means is adapted to store received data in a number of queues corresponding to the first number of network connections times a first predetermined number, and - a second mode of operation for use when the device operates in its second mode of operation and wherein the storage means is adapted to store received data in a number of queues corresponding to the second number of network connections times a second predetermined number. The first and second predetermined numbers can differ from one when it is desired to be able to store data in a queue relating to e.g. a priority thereof. Thus, the predetermined number may relate to the number of priorities.

Another aspect of the invention relates to a method of operating a switch having: a number of devices each comprising an interface according to the first or second aspect and an interface according to the third or fourth aspects and each being adapted to receive a plurality serial data signals from and output serial data signals to one or more network connections via the interface, - a data bus on which the devices are adapted to interchange data,

the method comprising altering, in at least one of the devices, between at least two modes of operation comprising:

- a first mode of operation wherein the device receives serial data signals from and/or transmits serial data signals to a first number of network connections via the interface, and a second mode of operation wherein the device receives serial data signals from and/or transmits serial data signals to a second number of network connections via the interface, the second number being higher than the first number.

The method preferably also comprises the step of processing the data received from the interface before transmission to the data bus, the method comprising altering the processing between at least two modes of operation comprising:

- a first mode of operation wherein the data from each of the first number of network connections is processed independently of each other, and a second mode of operation wherein the data from the second number of network connections is processed independently of each other.

In addition, a step may be added for storing data between receipt thereof at the interface and transmission thereof on the bus, the method comprising altering the storing between at least two modes of operation comprising:

a first mode of operation for use when the device operates in its first mode of operation and wherein data is stored in a number of queues corresponding to the first number of network connections times a first predetermined number, and a second mode of operation for use when the device operates in its second mode of operation and wherein received data is stored in a number of queues corresponding to the second number of network connections paths times a second predetermined number.

A final aspect of the invention relates to a method of operating the above switch, the method comprising:

- determining, for at least one of the devices, whether to use the first or the second mode of operation, and - operating the device in the mode of operation determined.

The present interface may be an interface between different parts of an electronic circuit or of a communication system. Thus, the interface may comprise pins, balls, or pads of a chip, where the aligning and operating means could then form part of the chip. In that situation, the interface could define the communication into and out of the chip. In this particular situation, the interface of the chip may define, using the same pads/pins/balls, both a wider interface and a number of more narrow interfaces - and where the interfaces may be run with different frequencies. This will reduce the pin/ball/pad count of the chip. In that situation, the parallel data and the parallel data busses may be internal to the chip.

Naturally, the interface may also interconnect with the networks, chips, computers or the like using connectors or plugs - or via soldering.

Even though it is presently preferred that the first mode of operation merely receives/transmits a single piece of or stream of data in the first mode of operation, any number of parallel transmissions/receptions may be used. The overall invention relates to the use of the same interface for two different numbers of data streams or pieces - preferably transmitted at two different overall data rates. The actual choice may relate to the overlap in connectors between the individual sub-interfaces.

In the following, the preferred embodiment will be described with reference to the drawing, wherein:

Fig. 1 illustrates a box diagram of the most important parts of the preferred embodiment,

- Fig. 2 is a more detailed illustration of a combined MAC of Fig. 1 , and

- Fig. 3 is a more detailed illustration of part of Fig. 1. Fig. 1 illustrates the overall system, which is an Ethernet switch having a plurality of combined devices/ports, here one combined port is designated by four fat double arrows 10.

The switch acts by receiving Ethernet packets at the ports, performing a processing thereof (to be explained later) and forwarding the packets (as fixed-size cells) on a bus via a bus interface 70 to another combined port which performs additional processing on the packet and outputs it.

Thus, the switch will comprise a plurality of the devices illustrated in Fig.1 - all devices being interconnected by the bus illustrated at the top of the figure. The functionality of all devices of the switch being the same.

To be more specific, but skipping for the moment the lower part of Fig. 1 , an Ethernet packet is received and forwarded to a MAC 40 which performs the standard MAC processing thereof and forwards the packet to a classifier/analyser 50 for classification and analysis (deriving a priority for the packet and determining which other system to transmit the packet to via the bus). Naturally, this classifier/analyser 50 may be shared (or part thereof may be shared) between multiple or all devices in the switch.

In the preferred embodiment, the classifier is provided in the individual device but the analyser is shared between all devices in the switch. Headers of the packets are transmitted from the devices to the analyser, which will then perform a centralized look-up and return an ID of the receiving device.

After analysis/classification, the packet is stored in an ingress queue system 60 prior to transmission on the bus via a bus interface 70. Preferably, the packet is divided into fixed- size cells prior to transmission.

The bus interface 70 on the receiving device will receive the cells and transfer these to an egress queue system 80 and further to a rewriter, which may perform amendments to the final packet before transmission to the MAC 40 for outputting.

The switch also comprises an arbiter for arbitrating between the devices' accesses to the bus. This functionality is, however, not important for the understanding of the present invention. It should be noted that it may be desired to provide additional formatting, such as the 8b/10b encoding, of the signal between the MAC 40 and the lane alignment, and that the individual encoders may communicate in order to encode the 32 bit XGMII word in the 10G case.

The above typical functionality of a switch is enhanced in the present embodiment in that the device is software configurable between two modes:

- a first mode where the device acts as a single 10 Gbit s I/O port of the switch and

- a second mode where the device acts as four 1 Gbit/s I/O ports of the switch.

This, naturally, requires amendments of the individual elements in order to obtain this functionality.

As to the MAC 40, a more detailed view thereof may be seen from Fig. 2, where it is seen that, in fact, 5 MACs are at least functionally present. Four 1 Gbit/s MACs and one 10Gbit/s MAC. The 1 Gbit/s MACs communicate using the GMII 1 Gbit/s standard to a lane aligner 30, the functionality of which will be described later. The 10 Gbit/s MAC communicates using the XGMII 10 Gbit/s standard.

The MACs may 1 ) be fully separate units in the system and on a chip defining the device. Alternatively, they may 2) be combined by combining the four 1 Gbit/s MACs and leaving the 10Gbit/s MAC as a separate part. Also, the five MACs may 3) be fully separated into a single block on the chip. In this situation, combination would mean that the logics/storage thereof are either combined or in some situations actually shared between combined MACs

These solutions have the following advantages/disadvantages:

1): A single block has to be defined. However, all MACs (that is, all 4 1 Gbit/s MACs operated at the same time) operated must be in the same clock domain and be synchronized. This may be a problem when each MAC feeds an OE to an optical fibre. Also, an overall block size reduction will be obtained in that the synthesized block will reuse logic across the MACs, whereby the overall size of the block will be smaller than the combined size of individual blocks.

2): The above synchronization disadvantage is seen - and two blocks now have to be defined. Again, a certain reduction in size and logics will be seen. 3): The synchronization disadvantage is removed but now 5 individual blocks have to be defined. Also, the size of the MACs on the chip will be the largest.

In fact, yet another solution may be used: providing a MAC (for the 1 Gbit/s MACs), which is able to perform the operation of the four 1 Gbit/s MACs by time multiplexing. In that situation, compared to four individual 1 Gbit/s MACs, the same logic may be used and only the storage for holding the states of the individual time multiplexed MACs needs be provided in four copies.

As to the analyser/categorizer 50, a number of manners exist as to how to provide that unit with the present multi-functionality. It will be possible to provide storage adapted to hold packets received from the MAC(s) 40 and to operate on each packet on a serial basis. In that situation, the analyser/categorizer must simply be able to handle a packet rate of 10 Gbit s.

If it is not desired to provide this much storage at this position in the system, the categorizer/analyser 50 may be run as four separate (in the 4x1 Gbit/s mode) analysers/categorizers which may, just as the MACs, be synthesized into a single block having four state memories but combined logic.

The preferred embodiment is adapted to handle a number of priorities and to store the packets/cells in the ingress queue system 60 in prioritized queues. Thus, the queue system 60 is already able to handle a plurality of queues, and the shift from the 1x10Gbit/s mode and the 4x1 Gbit/s mode will simply entail a change in the number of queues. This alteration is quite simple.

The same is the case for the egress queue system 80.

The rewriter 90 may be altered or prepared in the same manner as the MAC 40 and the analyzer/categorizer 50.

So, now to the lower part of Fig. 1.

It is clear from Fig. 2 that the MAC(s) output either four GMII signals or one XGMII signal. These signals are to be formatted and output from the system.

The basic idea of an important feature of the invention is the following observation: - XAUI is based on 4 (synchronized) 3.125 GHz PECL channels.

- Quad SGMII uses 4 (unsynchronized) 1.25 GHz PECL channels.

- Also, 1 GbE serdes is based on a 1.25 GHz LVDS channel, which is potentially related to tri-speed SGMII.

5

Thus, it will be possible to share the same set of pins between a single XAUI port and four (e.g. tri-speed) 1 GbE ports.

Thus, the GMII/XGMII signals are output on a port adapted to output XAUI when all four 10 l/O's are used or as 4x1 Gbit/s SGMII/SERDES when used individually.

XAUI requires that the four lanes be aligned. A time skewing may take place between the signals either in the transport medium (copper cables or optical cables) or even between the 10Gbit/s MAC and the XAUI port. Therefore, for use in the 10 Gbit/s mode, a Lane alignment 15 30 is provided for performing this alignment - preferably both in the RX mode and the TX mode.

The XGMII/GMII signals output from the MAC(s) are parallel signals which need to be serialized both for use in XAUI and SERDES/SGMII. For that use, four SERDES units 20 are 0 provided.

An important aspect of this part of the system is the fact that both 1 Gbit/s operation and 10Gbit/s operation may be obtained using the same SERDES circuits, which are quite complex circuits. 5

In the 10Gbit/s mode, the lane alignment 30 will ensure line alignment of the XAUI signals received or the XGMII signals to be transmitted. In the 1 Gbit/s mode, the lane alignment is not used.

0 For use in most of the modes, a Clock Data Recovery CDR 15 is provided for each lane. This circuit derives the clock embedded in the XAUI/SERDES/SGMII signals.

The CDRs 15 will be fed by a PLL, which is able to provide the 1.25 GHz, 2.5 GHz, and 3.125 GHz signals used in SERDES/SGMII, Infiniband, and XAUI, respectively. This span 5 could be reduced by using a 1 :2 prescaler in the 1 GbE case. The Infiniband communication may also be used in the present system in that it is quite similar to XAUI.

In certain embodiments of SGMII, a separate clocking signal may be provided on the link, and it may be desirable that the present system outputs the derived clocking signal from the link in order to also be useful in systems expecting this signal.

The Serdes circuits are standard Serdes circuits, and the CDR will only be required in the SGMII case where a clock is embedded in the signal.

A concern could be power: As the high-speed logic is made for 3.125 GHz, it could burn excessive power at 1 .25 GHz; this can be fixed, however, by adjusting the bias current provided to the high-speed logic so that the chip or at least the relevant parts thereof are adapted to operate at two bias currents.

It should be noted that a likely development in the market is a quad SGMII copper PHY, with a single clock towards to MAC (paralleling similar developments at lower speeds); in this case, the CDR blocks can be simplified considerably.

Claims

1. An interface comprising:

- a plurality of means for serializing parallel data, each serializing means being adapted to output a serial data signal,

- first means for providing a plurality of independent first parallel data, one first parallel data for each serializing means,

- second means for providing second parallel data, for dividing the second parallel data into a plurality of third parallel data and for providing a third parallel data to each of the serializing means, and

- means for aligning and/or synchronizing serial data signals output from the serializing means in order to obtain a predetermined timing relationship between the plurality of serial data signals.

2. An interface according to claim 1 , wherein the aligning/synchronizing means are adapted to not align/synchronize serial data signals output from the serializing means when receiving the first parallel data.

3. An interface comprising:

4. An interface according to claim 1 , wherein the aligning/synchronizing means are adapted to be disabled.

5. An interface according to claim 1 , wherein the first providing means is adapted to output each first parallel data along a first parallel data bus having a first predetermined number of conductors, wherein the second providing means is adapted to output the second parallel data along a second data bus having a second predetermined number of conductors, and wherein the first and second data busses have at least one conductor in common.

6. An interface according to claim 5, wherein the first predetermined number of conductors differs from the second number of conductors.

7. An interface according to claim 5, wherein the first parallel data busses are comprised in the second parallel data bus.

8. An interface according to claim 5, wherein the plurality of serializing means times the first predetermined number of conductors is identical to the second predetermined number of conductors.

9. An interface according to claim 1 , wherein the first providing means is adapted to output first parallel data conforming to the GMII standard, wherein the second providing means is adapted to output second parallel data conforming to the XGMII standard, and wherein the serializing means are adapted to output a plurality of serial data signals conforming to the XAUI or the Infiniband standards.

10. An interface comprising:

- a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, - means for aligning/synchronizing the serial data signals prior to deserialization in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled,

- means for, when the aligning/synchronizing means are not disabled, combining the parallel data relating to deserialized aligned/synchronized serial signals into a single parallel piece of data or a single parallel stream of data.

11. An interface comprising:

a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, - means for aligning/synchronizing the plurality of parallel data in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled,

- means for, when the aligning/synchronizing means are not disabled, combining 5 the aligned/synchronized parallel data into a single parallel piece of data or a single parallel stream of data.

12. An interface according to claim 10, wherein the deserializing means are adapted to output each parallel data along a first parallel data bus having a first predetermined number

10 of conductors, wherein combining means is adapted to output the single parallel data along a second data bus having a second predetermined number of conductors, and wherein the first and second data busses have at least one conductor in common.

13. An interface according to claim 12, wherein the first predetermined number of conductors 15 differs from the second number of conductors.

14. An interface according to claim 12, wherein the first parallel data busses are comprised in the second parallel data bus.

20 15. An interface according to claim 12, wherein the plurality of deserializing means times the first predetermined number of conductors is identical to the second predetermined number of conductors.

16. An interface according to claim 10, wherein the deserializing means are adapted to 25 output first parallel data conforming to the GMII standard, wherein the combining means is adapted to output second parallel data conforming to the XGMII standard, and wherein the deserializing means are adapted to receive a plurality of serial data signals conforming to the XAUI or the Infiniband standards.

30 17. An interface according to claim 1 , further comprising a means for providing a clocking signal, and wherein the serializing/deserializing means are adapted to perform the serializing/deserializing in accordance with the clocking signal.

18. An interface according to claim 17, wherein the clocking providing means are adapted to 35 provide a clocking signal having one of two clocking signal frequencies, where a clocking signal having one of the clocking signal frequencies is provided when the aligning/synchronizing means is disabled and the other when the aligning/synchronizing means is not disabled.

19. An interface according to claim 18, wherein the one and the other clocking frequencies 5 are selected from the group consisting of 3.25 GHz, 1.25 GHz, and 2.5 GHz.

20. An interface according to claim 19, wherein the frequency of the one signal is 1.25 GHz and wherein frequency of the other signal is 3.25 GHz or 2.5 GHz.

10 21. A communication system comprising a first interface according to claim 1 , a second interface including a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, means for aligning/synchronizing the serial data signals prior to deserialization in order to obtain a predetermined timing relationship between the plurality of parallel data, the 15 aligning/synchronizing means being adapted to be disabled, means for, when the aligning/synchronizing means are not disabled, combining the parallel data relating to deserialized aligned/synchronized serial signals into a single parallel piece of data or a single parallel stream of data, and means for transporting the plurality of serial signals from the first interface to the 0 second interface, the system comprising means for processing the plurality of parallel data and/or the single parallel data output by the second interface, the processing means being adapted to process the plurality of parallel data independently of each other.

22. A communication system according to claim 21 , the system being adapted to be 5 operated in one of two modes of operation, comprising:

- a first mode of operation wherein the aligning/synchronizing means of the first and second interfaces are operated, and

- a second mode of operation wherein the aligning/synchronizing means of the first and second interfaces are disabled. 0

24. A method of operating the interface of claim 1 , the method comprising:

determining whether the serial data signal(s) to be received and/or output is/are to be aligned and/or synchronized and 5 - operating the aligning/synchronizing means accordingly.

25. A method according to claim 24, wherein the determining step comprises determining an overall data rate of the plurality of serial data signals and operating the aligning/synchronizing means if the data rate exceeds a predetermined threshold.

26. A method of operating the interface according to claim 10, the method comprising: altering between two modes of operation wherein:

- in a first mode of operation, the deserializing means receive data independently of each other and output the parallel data independently of each other, and

- in a second mode of operation, the single parallel data is output.

27. A method of operating the interface according to claim 1 , the method comprising: altering between two modes of operation wherein: in a first mode of operation, the serializing means receive the first parallel data independently of each other and output the serial data independently of each other, and

28. A switch having: - a number of devices each comprising an interface according to claim 1 , an interface including a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, means for aligning/synchronizing the serial data signals prior to deserialization in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled, means for, when the aligning/synchronizing means are not disabled, combining the parallel data relating to deserialized aligned/synchronized serial signals into a single parallel piece of data or a single parallel stream of data, each being adapted to receive a plurality of serial data signals from and output a plurality of serial data signals to one or more network connections, and - a data bus on which the devices are adapted to interchange data, wherein at least one of the devices is adapted to alter between at least two modes of operation comprising: a first mode of operation wherein the device is adapted to receive serial data signals from and transmit serial data signals to a first number of network connections via the interface, and a second mode of operation wherein the device is adapted to receive serial data signals from and transmit serial data signals to a second number of network connections via the interface, the second number being higher than the first number.

5 29. A switch according to claim 28, wherein the at least one device comprises a processing means adapted to process the data received from the interface before transmission to the data bus, the processing means being adapted to alter between operation in one of at least two modes of operation comprising:

10 - a first mode of operation wherein the means is adapted to process the data from each of the first number of network connections independently of each other, and a second mode of operation wherein the means is adapted to process the data from the second number of network connections independently of each other.

15 30. A switch according to claim 29, wherein the processing means comprises, in the second mode of operation, separate memory for each of the second number of independent processes and logic shared between the second number of independent processes.

31. A switch according to claim 28, wherein at least one device further comprises a storage 0 means adapted to store data between receipt thereof at the interface and transmission thereof on the bus, the storage means being adapted to alter between at least two modes of operation comprising:

a first mode of operation for use when the device operates in its first mode of 5 operation and wherein the storage means is adapted to store received data in a number of queues corresponding to the first number of network connections times a first predetermined number, and a second mode of operation for use when the device operates in its second mode of operation and wherein the storage means is adapted to store received data in a number of 0 queues corresponding to the second number of network connections times a second predetermined number.

32. A method of operating a switch having: a number of devices each comprising an interface according to claim 1 , and an 5 interface including a plurality of means for each receiving a serial data signal and for deserializing the serial data signal into parallel data, means for aligning/synchronizing the serial data signals prior to deserialization in order to obtain a predetermined timing relationship between the plurality of parallel data, the aligning/synchronizing means being adapted to be disabled, means for, when the aligning/synchronizing means are not disabled, combining the parallel data relating to deserialized aligned/synchronized serial signals into a single parallel piece of data or a single parallel stream of data, 5 each being adapted to receive a plurality serial data signals from and output serial data signals to one or more network connections via the interface, and a data bus on which the devices are adapted to interchange data, the method comprising altering, in at least one of the devices, between at least two modes of operation comprising: 10 - a first mode of operation wherein the device receives serial data signals from and/or transmits serial data signals to a first number of network connections via the interface, and a second mode of operation wherein the device receives serial data signals from and/or transmits serial data signals to a second number of network connections via the interface, the second number being higher than the first number. 15

33. A method according to claim 32, further comprising the step of processing the data received from the interface before transmission to the data bus, the method comprising altering the processing between at least two modes of operation comprising:

20 - a first mode of operation wherein the data from each of the first number of network connections is processed independently of each other, and a second mode of operation wherein the data from the second number of network connections is processed independently of each other.

25 34. A method according to claim 32, further comprising the step of storing data between receipt thereof at the interface and transmission thereof on the bus, the method comprising altering the storing between at least two modes of operation comprising:

a first mode of operation for use when the device operates in its first mode of 30 operation and wherein data is stored in a number of queues corresponding to the first number of network connections times a first predetermined number, and a second mode of operation for use when the device operates in its second mode of operation and wherein received data is stored in a number of queues corresponding to the second number of network connections paths times a second predetermined number. 35

5. A method of operating the switch according to claim 28, the method comprising: