WO2003052831A1 - A method for fabricating high aspect ratio electrodes - Google Patents
A method for fabricating high aspect ratio electrodes Download PDFInfo
- Publication number
- WO2003052831A1 WO2003052831A1 PCT/NO2002/000425 NO0200425W WO03052831A1 WO 2003052831 A1 WO2003052831 A1 WO 2003052831A1 NO 0200425 W NO0200425 W NO 0200425W WO 03052831 A1 WO03052831 A1 WO 03052831A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrodes
- electrode
- barrier layer
- layer
- electrode material
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 96
- 238000000059 patterning Methods 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims description 59
- 239000007772 electrode material Substances 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000001747 exhibiting effect Effects 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 239000002322 conducting polymer Substances 0.000 claims description 2
- 229920001940 conductive polymer Polymers 0.000 claims description 2
- 229920001577 copolymer Polymers 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000011147 inorganic material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 239000011368 organic material Substances 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000009413 insulation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 108091081062 Repeated sequence (DNA) Proteins 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Definitions
- the present invention concerns a method for building high aspect ratio electrodes in an electrode means comprising parallel electrodes in a dense arrangement, wherein the method comprises successive process steps for a) depositing a first global layer of electrode material with height h on a substrate, b) patterning the electrode material to form first parallel electrodes of the electrode means, said first electrodes having a width w and height h and being separated by a recess of width d, and wherein the method is characterized by comprising successive further process steps for c) covering the first electrodes with a barrier layer of thickness ⁇ , ⁇ being a fraction of width w, whereby the width d of the recess becomes equal to 2w+2 ⁇ , d) depositing a second global layer of electrode material over the first electrodes with the barrier layer and filling the recesses therewith, e) patterning a second layer of electrode material to form second parallel electrodes of the electrode means in the recesses between the electrodes and the barrier layer covering the latter, said second electrodes extending above the first electrodes
- the present invention is related to a method for manufacturing an electrode means as disclosed in the co-pending international patent application No. PCT/NO02/00414 and belonging to the same applicant.
- This patent application teaches a method for making an electrode means comprising parallel strip-like electrodes in a first and second electrode layers respectively, and contacting a global layer of a functional medium provided therebetween.
- the electrodes of the second layer are oriented orthogonally to the electrodes of the first layer, forming a matrix of electrodes that is capable of addressing functional elements in the functional medium, said elements being defined as volume element thereof between the respective crossing electrodes of the first and second layer.
- the parallel strip-like electrodes in each layer are provided in a very dense arrangement, allowing a very high fill factor of electrode material in a given device area.
- Electrode means of this kind are suited for use in matrix-addressable devices, for instance a memory device with a functional medium in the form of a ferroelectric memory material sandwiched between two electrode layers, such that the electrodes of the first electrode layer may form word lines and the electrodes in the second electrode layer bit lines in the electrode means, such that a memory cell can be defined and addressed at the crossing between an electrode of respectively the first and the second electrode layers.
- the dense electrode arrangement in electrode means of this kind can e.g. be applied to a memory device of the kind disclosed in the co-pending international patent application PCT/NO02/00390, wherein memory material is not only provided in sandwich, but also additionally applied over the side edges of the addressing electrodes or in recesses provided therein, thus allowing the switching of memory cells not only in the vertical direction, as will be the case with the ferroelectric memory material sandwiched between electrode means, but also in lateral directions such that multidirectionally switchable ferroelectric memory cells are obtained.
- Similar electrode means with the electrodes in a dense arrangement are also discussed in the co-pending international patent application PCT/NO02/00397 belonging to the same applicant and disclosing a field-effect transistor structure with extremely short channel length.
- a method for fabricating dense electrodes are generally disclosed in US patent No. 5 017 515 (Gill, assigned to Texas Instruments Inc.). This publication discloses how a dense electrode pattern can be formed as an electrode layer with parallel strip-like electrodes having a width corresponding to a minimum definable feature obtainable in a photolithographic process. Adjacent parallel strip-like electrodes are insulated by barrier of mutually insulated by a barrier of thin barrier of insulating material, and the thickness of this barrier is not constrained by design rules as applicable to photomicrolithographic and etching processes.
- Every second strip-like electrode is formed in a photolithographic process while the traditional electrodes provided between these by providing electrode material over the parallel strip-like electrode structures already in place and filling the recesses therebetween, whereafter a planarization step leaves a single electrode layer of parallel strip-like elektrodes with a low aspect ratio and mutually isolated by a thin barrier of isolating material.
- Electrodes with a high aspect ratios i.e. with a ratio between the electrode height h and the electrode width w as large as possible.
- a high aspect ratio is of great importance when the memory cells are provided in geometrical configurations that shall allow their definition in three dimensions and permit not only a vertical switching direction, but also lateral switching directions. In such cases the memory cell height will be equal or almost equal to the height of the addressing electrodes.
- the ferroelectric material is provided between the source and drain electrodes of a field-effect transistor provided on e.g. a silicon substrate with appropriately doped regions.
- the ferroelectric memory material now provides a memory cell that is switchable in lateral directions and which moreover also functions as a gate insulator, as it will not only be present between the source and drain electrodes, but also covers the top surfaces thereof and ensures that the gate electrode is properly insulated from the former.
- Such a configuration moreover offers the possibility of a three-bit or triple memory cell, as using the electrodes of the transistors for addressing the ferroelectric memory material now shall allow the storage of three separately addressable bits therein, or, as given by a protocol, a three-bit word.
- the height dimension of the cell is of course important and will be equal to the electrode height.
- the electrode height does not scale with the electrode density, but as it will be important to improve the signal noise ratio and signal strength in general by increasing the electrode height and thus also the height of a cell of a functional material contacting the electrode at sides thereof, it is desirable to have electrodes with very high aspect ratios.
- high aspect rations of the electrodes is important for instance with the view to obtaining high capacitance which translates into correspondingly improved signal strength and signal/noise ratios in memory devices.
- a second object of the present invention is to simplify any masking and planarization step involved in the fabrication of electrodes with high aspect ratio in electrode means of the above kind.
- a third object of the present invention is to fabricate electrode means with high aspect ratio without the application of, e.g. a barrier and memory material between the electrodes creating problems, when considering that the electrodes in dense electrode arrangements in separated by a very small distance, thus forming recesses therebetween which when the aspect ratio is high, causes problems of obtaining the desired filling of any material therein.
- a method according to the invention characterized by comprising successive further process steps for c) covering the first electrodes with a barrier layer of thickness ⁇ , ⁇ being a fraction of the width w, whereby the width d of the recess becomes equal to w+2 ⁇ , d) depositing a second global layer of electrode material over the first electrodes with the barrier layer and filling the recesses therewith, e) patterning a second layer of electrode material to form second parallel electrodes of the electrode means in the recesses between the electrodes and the barrier layer covering the latter, said second electrodes extending above the first electrodes to a height H-h and being insulated therefrom by means of the barrier layer; whereafter the sequence of process steps c)-e) are alternatingly applied as required to the first and second electrodes respectively until the desired aspect ratio (n+l)(H-h)/w for all electrodes is obtained in a final process step after performing n sequences of the successive process steps
- the substrate is a semiconducting material, e.g. silicon, which is processed to form an insulating layer against material or covered by an insulating thin film applied to the surface thereof.
- a semiconducting material e.g. silicon
- the barrier material can advantageously be selected as an insulating inorganic or organic material, and the barrier material can then preferably be selected as a polarizable dielectric material capable of exhibiting hysteresis, e.g. a ferroelectric or electret material, and in case it is a ferroelectric or electret material, this can even more preferably is selected as a polymer or copolymer material.
- the patterning of the electrode material to form electrodes takes place respectively by microlithography and etching, and it is then considered advantageous to use one and the same photomask for the patterning step, said photomask being displaced back and forth in translation over the same distance w+ ⁇ in the alternating process step sequences when patterning the electrodes and electrodes respectively.
- the final process step comprises covering the top surface of the electrodes with a global barrier layer, while in a second preferred embodiment the final process step leaves the barrier layer covering the top of every second electrode in the electrode means as applicable.
- the final process step leaves the electrodes as well as the barrier layers flush and exposed in the top surface of the electrode means.
- the height H of the electrode layers can be selected from the second electrode layer on inclusive, as 2h.
- the electrode width can be selected as the minimum process-definable feature subject to the design rule of the applied patterning process.
- fig. 1 shows a cross section of global electrode layer deposited on a substrate
- fig. 2 a cross section of a first set of parallel electrodes patterned in the layer of electrode material in fig. 1
- fig. 3a a cross section of the electrodes in fig. 2 provided with a barrier layer
- fig. 3b a cross section of the embodiment in fig. 3a now covered with the global layer of electrode material, fig. 3c the patterning of the global layer of electrode material shown in fig. 3b to form second electrodes between the first electrodes,
- fig. 9 in partial cross section a second preferred embodiment of the top surface of the finished electrode means
- fig. 10 in partial cross section a third preferred embodiment of the top surface of the finished electrode means
- fig. 11a in full cross section the finished electrode means as embodied and shown in fig. 10
- fig. 1 lb a plan view of the electrode means in fig. 1 la.
- a global layer of electrode material ⁇ is provided with a height h on a suitable substrate 1, which for instance could be a semiconducting material like silicon and appropriately surface-treated to provide insulation against the electrode material ⁇ . Then a photomicrolithographic process with etching is applied to the layer of electrode material ⁇ to provide patterned first electrodes ⁇ i as shown in fig. 2. This leaves, as shown in cross section, the electrodes i approximately as rectangular or square ridges on the substrate 1, the electrodes ⁇ i having of course the height h and the width w corresponding to a mask width.
- Recesses 2 are formed between the electrodes ⁇ i and with a width not smaller than a minimum process-constrained feature obtainable in the photomicrolithographic process as given by the design rule thereof. If this minimum process-constrained feature is equal to the electrode width w, the width of the recess 2 could be also equal to w.
- the patterned electrodes ⁇ i are now covered by an extremely thin barrier layer 3 with e.g. dielectric or insulating properties as shown in fig. 3a.
- This barrier layer 2 could e.g. be made of a ferroelectric or electret material, i.e. material which is polarizable and capable of exhibiting hysteresis when subjected to an applied electric field.
- the mask width could now be selected such as to leave the recesses 2' with a width w similar to that of the electrodes ⁇ and similarly it will be evident that a distance d between an electrode ⁇ r and the following parallel electrode ⁇ i will be w+2 ⁇ , the resulting so-called pitch then obtaining the value 2w+2 ⁇ , as this pitch corresponds to the repetition distance of the electrode pattern as shown in fig. 3a, where all the relevant dimensions have been depicted. It is, of course, to be understood that the values of these dimensions, i.e. w, ⁇ and h may be freely selected but subject to constraint by any applicable design rule.
- the electrodes & ⁇ covered with barrier layer 3 are now covered by applying another global layer of electrode material ⁇ , preferably to a height H-2h and above the substrate as shown in fig. 3b.
- the same photomask as used for patterning the electrodes ⁇ i in the process step shown in fig. 2 is now shifted laterally, with a distance w+ ⁇ corresponding to the width of the original recess 2 between the electrodes ⁇ i less the barrier thickness ⁇ .
- the electrode material ⁇ of the globally applied layer as well as the barrier layer 3 covering the electrodes i are removed e.g. in etching process down to the top surface of the electrodes Z ⁇ , creating second electrodes ⁇ 2 in the recesses 2' shown in figs.
- the barrier layer 3 is left providing insulation between the electrodes ⁇ i and electrodes ⁇ 2 .
- Fig. 4b renders a process step similar to that in fig. 3b, i.e. another global layer of electrode material ⁇ is applied above the already formed electrodes ⁇ i, ⁇ 2 and filling the recesses 2" between the latter, this layer of electrode material ⁇ preferably being applied with the same height as shown in fig. 3b, i.e.
- Fig. 4c corresponds to the process step depicted in fig. 3c and differs only by shifting the same photomask as before by the distance w+ ⁇ and then removing the electrode material ⁇ above the electrodes ⁇ 2 as well as the barrier layer 3 down to the top surface thereof, thus creating a recess 2'" between the raised portions of the electrodes Sj. As will be seen this now adds another portion ⁇ i' to the electrodes ⁇ i and increases their aspect ratio, as clearly seen in fig. 4c.
- the photomask is now once more shifted in the necessary distance and the electrode material ⁇ above the electrodes ⁇ ⁇ and the barrier layer 3 is removed, creating a structure as shown in cross section in fig. 5c.
- the aspect ratio of the electrodes ⁇ 2 is now increased by adding the portion ⁇ 2 ' thereof and leaving recesses 2 IV therebetween down to the top surface of the already provided electrodes ⁇ i. Again can the process steps as shown e.g. in any of the figures 3, 4 and 5 above now be repeated.
- the barrier layer 3 is provided above the raised and exposed portions of the electrodes ⁇ 2 , and then another layer of electrode material ⁇ is applied over the electrodes and filling the recesses 2 1V , as shown in fig. 6b.
- the photomask is then again shifted as before and the excess electrode material ⁇ etched away above the electrodes ⁇ 2 , leaving the barrier layer between the electrodes ⁇ ls ⁇ 2 and forming a recess 2 V between the electrodes ⁇ i as shown in fig. 6c and extending to the height of the electrodes ⁇ j being increased by an amount corresponding to the height of the portion ⁇ i', thus also increasing the aspect ratio of the electrodes ⁇ All the time the barrier material 3 remains providing insulation between the electrodes ⁇ l5 ⁇ 2 and as shown in fig. 6c.
- a final and concluding process step is performed as shown in fig. 7 whereby the barrier layer 3 is applied covering the raised portion of the electrodes ⁇ i and then a global layer of electrode material ⁇ is applied over the electrodes ⁇ ]5 ⁇ 2 and filling the recesses 2 V between the electrodes i and above the electrodes ⁇ 2 .
- This electrode material ⁇ is deposited with an excess thickness of about ⁇ which now is removed in a planarization step as e.g.
- the electrodes ⁇ ! are still covered with a planarized top surface of the barrier layer 3, while the top surfaces of the electrode ⁇ 2 is exposed therebetween.
- the planarization step is carried out so as to remove the barrier layer 3 covering the top surface of the electrodes ⁇ i and the portion of excess electrode material ⁇ on the top of the electrodes ⁇ 2 , thus obtaining all the electrodes ⁇ 1; ⁇ 2 in the electrode means with the same height and mutually isolated by the barrier layer 3.
- the top surfaces of the electrodes ⁇ ⁇ , ⁇ 2 and the barrier layers 3 between the electrodes i, ⁇ 2 may be covered by another barrier layer 4 which can be the same material as that of the barrier layers 3 or a different material.
- Barrier layer 4 can e.g. also be a ferroelectric or electret material or e.g. a ferroelectric polymer, but could as well be another insulating material.
- a third embodiment of the finished electrode means are shown in fig. 10, which again only renders the cross section of the top portion of the electrode means.
- the electrodes ⁇ i as well as ⁇ 2 and the mutually insulating barrier layers 3 therebetween have been planarized in a final step to provide the electrodes ⁇ 1?
- the method of building electrodes with a high aspect ratio according to the present invention removes all disadvantages and weaknesses inherent in prior art technology.
- the barrier layer material 3 is provided in situ after each sequence of process steps and thus the problem of having to fill a very narrow and deep recess in a final process step is completely eliminated.
- the method according to the present invention not only removes the problems inherent in prior art when used to fabricate the electrodes with as high aspect ratio as desired, but also leads to much reduced costs, as only a single photomask is used and only a final planarization step is involved.
- the electrode means with parallel electrodes in a very dense arrangement and high aspect ratio can be applied in all circumstances where such electrodes with high aspect ratio are desired, be it memory devices or transistor devices or integrated transistor/memory devices where geometries are involved that shall benefit from such high aspect ratio electrodes.
- the resulting electrode means e.g. as depicted in fig. 11a and fig. 1 lb, can be combined to form a stack of volumetric devices and with e.g. the electrode means arranged such that the electrodes in alternating electrode means are oriented crosswise, preferably orthogonally to each other and with functional material provided and made addressable as given by any geometry obtainable with electrode means of this kind. It is, however, understood that specific geometrical configurations considered advantageous for use with high aspect ratio electrode in various memory and switching devices can be obtained in various post-processing operations and hence are not made a subject of the present application.
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002353669A AU2002353669B2 (en) | 2001-12-14 | 2002-11-18 | A method for fabricating high aspect ratio electrodes |
EP02789028A EP1454358A1 (en) | 2001-12-14 | 2002-11-18 | A method for fabricating high aspect ratio electrodes |
CA002466151A CA2466151A1 (en) | 2001-12-14 | 2002-11-18 | A method for fabricating high aspect ratio electrodes |
JP2003553629A JP2005513784A (en) | 2001-12-14 | 2002-11-18 | Manufacturing method of high aspect ratio electrode |
KR1020047009166A KR100543077B1 (en) | 2001-12-14 | 2002-11-18 | A method for fabricating high aspect ratio electrodes |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NO20016096A NO315884B1 (en) | 2001-12-14 | 2001-12-14 | Method for producing high aspect ratio electrodes |
NO20016096 | 2001-12-14 |
Publications (1)
Publication Number | Publication Date |
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WO2003052831A1 true WO2003052831A1 (en) | 2003-06-26 |
Family
ID=19913147
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/NO2002/000425 WO2003052831A1 (en) | 2001-12-14 | 2002-11-18 | A method for fabricating high aspect ratio electrodes |
Country Status (9)
Country | Link |
---|---|
EP (1) | EP1454358A1 (en) |
JP (1) | JP2005513784A (en) |
KR (1) | KR100543077B1 (en) |
CN (1) | CN1605129A (en) |
AU (1) | AU2002353669B2 (en) |
CA (1) | CA2466151A1 (en) |
NO (1) | NO315884B1 (en) |
RU (1) | RU2271591C2 (en) |
WO (1) | WO2003052831A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4900987A (en) * | 1983-12-09 | 1990-02-13 | Fujitsu Limited | Method for driving a gas discharge display panel |
US4952031A (en) * | 1987-06-19 | 1990-08-28 | Victor Company Of Japan, Ltd. | Liquid crystal display device |
EP0685832A1 (en) * | 1994-06-01 | 1995-12-06 | Sharp Kabushiki Kaisha | A ferroelectric liquid crystal display device and a driving method of effecting gradational display thereof |
US6072716A (en) * | 1999-04-14 | 2000-06-06 | Massachusetts Institute Of Technology | Memory structures and methods of making same |
EP1187123A2 (en) * | 2000-08-31 | 2002-03-13 | Hewlett-Packard Company | Information storage device |
-
2001
- 2001-12-14 NO NO20016096A patent/NO315884B1/en unknown
-
2002
- 2002-11-18 RU RU2004120778/09A patent/RU2271591C2/en not_active IP Right Cessation
- 2002-11-18 CN CNA028249070A patent/CN1605129A/en active Pending
- 2002-11-18 EP EP02789028A patent/EP1454358A1/en active Pending
- 2002-11-18 JP JP2003553629A patent/JP2005513784A/en not_active Abandoned
- 2002-11-18 KR KR1020047009166A patent/KR100543077B1/en not_active IP Right Cessation
- 2002-11-18 AU AU2002353669A patent/AU2002353669B2/en not_active Ceased
- 2002-11-18 CA CA002466151A patent/CA2466151A1/en not_active Abandoned
- 2002-11-18 WO PCT/NO2002/000425 patent/WO2003052831A1/en active IP Right Grant
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4900987A (en) * | 1983-12-09 | 1990-02-13 | Fujitsu Limited | Method for driving a gas discharge display panel |
US4952031A (en) * | 1987-06-19 | 1990-08-28 | Victor Company Of Japan, Ltd. | Liquid crystal display device |
EP0685832A1 (en) * | 1994-06-01 | 1995-12-06 | Sharp Kabushiki Kaisha | A ferroelectric liquid crystal display device and a driving method of effecting gradational display thereof |
US6072716A (en) * | 1999-04-14 | 2000-06-06 | Massachusetts Institute Of Technology | Memory structures and methods of making same |
EP1187123A2 (en) * | 2000-08-31 | 2002-03-13 | Hewlett-Packard Company | Information storage device |
Also Published As
Publication number | Publication date |
---|---|
KR20040065269A (en) | 2004-07-21 |
AU2002353669A1 (en) | 2003-06-30 |
NO20016096L (en) | 2003-06-16 |
AU2002353669B2 (en) | 2006-01-12 |
EP1454358A1 (en) | 2004-09-08 |
KR100543077B1 (en) | 2006-01-20 |
CN1605129A (en) | 2005-04-06 |
NO20016096D0 (en) | 2001-12-14 |
RU2271591C2 (en) | 2006-03-10 |
CA2466151A1 (en) | 2003-06-26 |
RU2004120778A (en) | 2005-10-27 |
NO315884B1 (en) | 2003-11-03 |
JP2005513784A (en) | 2005-05-12 |
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