WO2003061006A3 - Stacked die in die bga package - Google Patents

Stacked die in die bga package Download PDF

Info

Publication number
WO2003061006A3
WO2003061006A3 PCT/US2003/000569 US0300569W WO03061006A3 WO 2003061006 A3 WO2003061006 A3 WO 2003061006A3 US 0300569 W US0300569 W US 0300569W WO 03061006 A3 WO03061006 A3 WO 03061006A3
Authority
WO
WIPO (PCT)
Prior art keywords
die
bga package
stacked
stacked die
devices
Prior art date
Application number
PCT/US2003/000569
Other languages
French (fr)
Other versions
WO2003061006A2 (en
WO2003061006B1 (en
Inventor
Hock Chuan Tan
Thiam Chye Lim
Victor Cher Khng Tan
Chee Peng Neo
Michael Kian Shing Tan
Beng Chye Chew
Cheng Poh Pour
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SG200200134A external-priority patent/SG121702A1/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU2003207484A priority Critical patent/AU2003207484A1/en
Publication of WO2003061006A2 publication Critical patent/WO2003061006A2/en
Publication of WO2003061006A3 publication Critical patent/WO2003061006A3/en
Publication of WO2003061006B1 publication Critical patent/WO2003061006B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/1319Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32014Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83193Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/8388Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852Applying energy for connecting
    • H01L2224/85201Compression bonding
    • H01L2224/85205Ultrasonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01061Promethium [Pm]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10156Shape being other than a cuboid at the periphery
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.
PCT/US2003/000569 2002-01-09 2003-01-09 Stacked die in die bga package WO2003061006A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003207484A AU2003207484A1 (en) 2002-01-09 2003-01-09 Stacked die in die bga package

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
SG200200134-5 2002-01-09
SG200200134A SG121702A1 (en) 2002-01-09 2002-01-09 Stacked die in die bga package
US10/068,159 US7332819B2 (en) 2002-01-09 2002-02-05 Stacked die in die BGA package
US10/068,159 2002-02-05

Publications (3)

Publication Number Publication Date
WO2003061006A2 WO2003061006A2 (en) 2003-07-24
WO2003061006A3 true WO2003061006A3 (en) 2004-06-17
WO2003061006B1 WO2003061006B1 (en) 2004-08-26

Family

ID=26665232

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/000569 WO2003061006A2 (en) 2002-01-09 2003-01-09 Stacked die in die bga package

Country Status (3)

Country Link
US (12) US7332819B2 (en)
AU (1) AU2003207484A1 (en)
WO (1) WO2003061006A2 (en)

Families Citing this family (190)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841412B1 (en) * 1999-11-05 2005-01-11 Texas Instruments Incorporated Encapsulation for particle entrapment
US7064447B2 (en) * 2001-08-10 2006-06-20 Micron Technology, Inc. Bond pad structure comprising multiple bond pads with metal overlap
US20030042615A1 (en) 2001-08-30 2003-03-06 Tongbi Jiang Stacked microelectronic devices and methods of fabricating same
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
SG167661A1 (en) * 2002-01-09 2011-01-28 Micron Technology Inc Stacked die in die bga package
US6896760B1 (en) * 2002-01-16 2005-05-24 Micron Technology, Inc. Fabrication of stacked microelectronic devices
DE10209204B4 (en) * 2002-03-04 2009-05-14 Infineon Technologies Ag Electronic component comprising a stack of semiconductor chips and method of making the same
US7323767B2 (en) * 2002-04-25 2008-01-29 Micron Technology, Inc. Standoffs for centralizing internals in packaging process
US6809416B1 (en) * 2002-05-28 2004-10-26 Intersil Corporation Package for integrated circuit with thermal vias and method thereof
US6927497B2 (en) * 2002-08-22 2005-08-09 Intel Corporation Multi-die semiconductor package
TWI322448B (en) 2002-10-08 2010-03-21 Chippac Inc Semiconductor stacked multi-package module having inverted second package
US7034387B2 (en) 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
KR100618812B1 (en) * 2002-11-18 2006-09-05 삼성전자주식회사 Multi chip package having increased reliability
KR20040086869A (en) * 2003-03-22 2004-10-13 삼성전자주식회사 Wafer dicing method for making the semiconductor chip having various shape
JP4705748B2 (en) * 2003-05-30 2011-06-22 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
US7042098B2 (en) * 2003-07-07 2006-05-09 Freescale Semiconductor,Inc Bonding pad for a packaged integrated circuit
DE10339487B4 (en) * 2003-08-27 2007-03-15 Infineon Technologies Ag Method for applying a semiconductor chip to a carrier
US7071421B2 (en) 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods
JP4130167B2 (en) * 2003-10-06 2008-08-06 日東電工株式会社 Semiconductor wafer peeling method
EP1501126A1 (en) * 2003-11-05 2005-01-26 Infineon Technologies AG Semiconductor chip having a cavity for stacked die application
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
TWI278947B (en) * 2004-01-13 2007-04-11 Samsung Electronics Co Ltd A multi-chip package, a semiconductor device used therein and manufacturing method thereof
TWI247371B (en) * 2004-02-06 2006-01-11 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
US20050194698A1 (en) * 2004-03-03 2005-09-08 St Assembly Test Service Ltd. Integrated circuit package with keep-out zone overlapping undercut zone
US7145249B2 (en) * 2004-03-29 2006-12-05 Intel Corporation Semiconducting device with folded interposer
US7378725B2 (en) * 2004-03-31 2008-05-27 Intel Corporation Semiconducting device with stacked dice
JP2005308629A (en) * 2004-04-23 2005-11-04 Canon Inc Miller unit and manufacturing method therefor
US20050247894A1 (en) * 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
DE102004025279B4 (en) * 2004-05-19 2011-04-28 Infineon Technologies Ag System for equipping substrates with ball contacts and method for equipping substrates with ball contacts
US20050285254A1 (en) * 2004-06-23 2005-12-29 Buot Joan R V Semiconducting device having stacked dice
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7242101B2 (en) * 2004-07-19 2007-07-10 St Assembly Test Services Ltd. Integrated circuit die with pedestal
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US20060051912A1 (en) * 2004-09-09 2006-03-09 Ati Technologies Inc. Method and apparatus for a stacked die configuration
JP4601365B2 (en) * 2004-09-21 2010-12-22 ルネサスエレクトロニクス株式会社 Semiconductor device
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
TW200612345A (en) * 2004-10-07 2006-04-16 Advanced Flash Memory Card Technology Co Ltd Structure of memory card and producing method thereof
US7816182B2 (en) * 2004-11-30 2010-10-19 Stmicroelectronics Asia Pacific Pte. Ltd. Simplified multichip packaging and package design
TWI250629B (en) * 2005-01-12 2006-03-01 Ind Tech Res Inst Electronic package and fabricating method thereof
US20070109756A1 (en) * 2005-02-10 2007-05-17 Stats Chippac Ltd. Stacked integrated circuits package system
US7160798B2 (en) * 2005-02-24 2007-01-09 Freescale Semiconductor, Inc. Method of making reinforced semiconductor package
KR100618892B1 (en) * 2005-04-13 2006-09-01 삼성전자주식회사 Semiconductor package accomplishing a fan-out structure through wire bonding
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US20070026573A1 (en) * 2005-07-28 2007-02-01 Aminuddin Ismail Method of making a stacked die package
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7622377B2 (en) * 2005-09-01 2009-11-24 Micron Technology, Inc. Microfeature workpiece substrates having through-substrate vias, and associated methods of formation
US7605476B2 (en) 2005-09-27 2009-10-20 Stmicroelectronics S.R.L. Stacked die semiconductor package
US20070111399A1 (en) * 2005-11-14 2007-05-17 Goida Thomas M Method of fabricating an exposed die package
TW200723495A (en) * 2005-12-07 2007-06-16 Chipmos Technologies Inc Chip package structure
US7663232B2 (en) 2006-03-07 2010-02-16 Micron Technology, Inc. Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems
US7384819B2 (en) * 2006-04-28 2008-06-10 Freescale Semiconductor, Inc. Method of forming stackable package
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
DE102006031405B4 (en) * 2006-07-05 2019-10-17 Infineon Technologies Ag Semiconductor module with switching functions and method of making the same
US7719096B2 (en) * 2006-08-11 2010-05-18 Vishay General Semiconductor Llc Semiconductor device and method for manufacturing a semiconductor device
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7659143B2 (en) * 2006-09-29 2010-02-09 Intel Corporation Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same
US7531383B2 (en) 2006-10-31 2009-05-12 Freescale Semiconductor, Inc. Array quad flat no-lead package and method of forming same
SG166773A1 (en) * 2007-04-24 2010-12-29 United Test & Assembly Ct Lt Bump on via-packaging and methodologies
JP4489094B2 (en) * 2007-04-27 2010-06-23 株式会社東芝 Semiconductor package
US7977778B2 (en) * 2007-05-04 2011-07-12 Stats Chippac Ltd. Integrated circuit package system with interference-fit feature
SG148054A1 (en) 2007-05-17 2008-12-31 Micron Technology Inc Semiconductor packages and method for fabricating semiconductor packages with discrete components
TWI335059B (en) * 2007-07-31 2010-12-21 Siliconware Precision Industries Co Ltd Multi-chip stack structure having silicon channel and method for fabricating the same
US8859396B2 (en) 2007-08-07 2014-10-14 Semiconductor Components Industries, Llc Semiconductor die singulation method
JP4504401B2 (en) * 2007-08-07 2010-07-14 株式会社東芝 Semiconductor package
SG150410A1 (en) 2007-08-31 2009-03-30 Micron Technology Inc Partitioned through-layer via and associated systems and methods
US8704379B2 (en) 2007-09-10 2014-04-22 Invensas Corporation Semiconductor die mount by conformal die coating
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7825502B2 (en) * 2008-01-09 2010-11-02 Fairchild Semiconductor Corporation Semiconductor die packages having overlapping dice, system using the same, and methods of making the same
FR2928491A1 (en) * 2008-03-06 2009-09-11 Commissariat Energie Atomique METHOD AND DEVICE FOR MANUFACTURING AN ASSEMBLY OF AT LEAST TWO MICROELECTRONIC CHIPS
CN101999167B (en) * 2008-03-12 2013-07-17 伊文萨思公司 Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US8470640B2 (en) * 2008-06-30 2013-06-25 Sandisk Technologies Inc. Method of fabricating stacked semiconductor package with localized cavities for wire bonding
US8294251B2 (en) * 2008-06-30 2012-10-23 Sandisk Technologies Inc. Stacked semiconductor package with localized cavities for wire bonding
US7888776B2 (en) * 2008-06-30 2011-02-15 Texas Instruments Incorporated Capacitor-based method for determining and characterizing scribe seal integrity and integrity loss
US8539408B1 (en) 2008-07-29 2013-09-17 Clarkson University Method for thermal simulation
US8923004B2 (en) * 2008-07-31 2014-12-30 Micron Technology, Inc. Microelectronic packages with small footprints and associated methods of manufacturing
US8084301B2 (en) * 2008-09-11 2011-12-27 Sanyo Electric Co., Ltd. Resin sheet, circuit device and method of manufacturing the same
KR20100059487A (en) * 2008-11-26 2010-06-04 삼성전자주식회사 Package structure
US7977802B2 (en) * 2009-03-05 2011-07-12 Stats Chippac Ltd. Integrated circuit packaging system with stacked die and method of manufacture thereof
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
JP5590814B2 (en) * 2009-03-30 2014-09-17 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and manufacturing method thereof
JP2010245337A (en) * 2009-04-07 2010-10-28 Elpida Memory Inc Semiconductor device and manufacturing method for the same
US8174131B2 (en) * 2009-05-27 2012-05-08 Globalfoundries Inc. Semiconductor device having a filled trench structure and methods for fabricating the same
US8119447B2 (en) * 2009-06-17 2012-02-21 Stats Chippac Ltd. Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof
TWI409932B (en) * 2009-08-04 2013-09-21 Chipsip Technology Co Ltd Package structure with cavity and manufacturing method thereof
US9466561B2 (en) 2009-08-06 2016-10-11 Rambus Inc. Packaged semiconductor device for high performance memory and logic
US8058706B2 (en) * 2009-09-08 2011-11-15 Texas Instruments Incorporated Delamination resistant packaged die having support and shaped die having protruding lip on support
KR101086972B1 (en) 2009-10-01 2011-11-29 앰코 테크놀로지 코리아 주식회사 Wafer Level Package having Through Silicon Via
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
TWI442053B (en) * 2009-12-01 2014-06-21 Mpi Corporaion Probe card, apparatus and method for maintaining the same
US8384231B2 (en) * 2010-01-18 2013-02-26 Semiconductor Components Industries, Llc Method of forming a semiconductor die
US9299664B2 (en) 2010-01-18 2016-03-29 Semiconductor Components Industries, Llc Method of forming an EM protected semiconductor die
US8574960B2 (en) * 2010-02-03 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming cavity adjacent to sensitive region of semiconductor die using wafer-level underfill material
US8372666B2 (en) * 2010-07-06 2013-02-12 Intel Corporation Misalignment correction for embedded microelectronic die applications
US8598695B2 (en) * 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
FR2966901B1 (en) 2010-10-29 2014-10-31 Tmc Innovation LIGHTING MATTING DEVICE
US7977231B1 (en) * 2010-11-08 2011-07-12 Asm Assembly Automation Ltd Die bonder incorporating dual-head dispenser
CN102738022B (en) 2011-04-15 2017-05-17 飞思卡尔半导体公司 Method for assembling semiconductor device containing insulating substrate and heat sink
KR101622930B1 (en) * 2011-05-19 2016-05-31 벌시테크 리미티드 Chip stacking
KR101801945B1 (en) * 2011-08-09 2017-11-28 에스케이하이닉스 주식회사 Semiconductor chip and semiconductor package having the same
US9040348B2 (en) 2011-09-16 2015-05-26 Altera Corporation Electronic assembly apparatus and associated methods
US9190391B2 (en) * 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US9147670B2 (en) 2012-02-24 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Functional spacer for SIP and methods for forming the same
US8658473B2 (en) 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
US20130264721A1 (en) * 2012-04-05 2013-10-10 Infineon Technologies Ag Electronic Module
US9666452B2 (en) 2012-05-25 2017-05-30 Infineon Technologies Ag Chip packages and methods for manufacturing a chip package
KR101958831B1 (en) * 2012-06-08 2019-07-02 삼성전자주식회사 Double Side Adhesive Tape, Semiconductor packages and methods of fabricating the same
US9198282B2 (en) * 2012-06-25 2015-11-24 Honeywell International Inc. Printed circuit board
CN102832189B (en) * 2012-09-11 2014-07-16 矽力杰半导体技术(杭州)有限公司 Multi-chip packaging structure and multi-chip packaging method
US9484260B2 (en) 2012-11-07 2016-11-01 Semiconductor Components Industries, Llc Heated carrier substrate semiconductor die singulation method
US9136173B2 (en) 2012-11-07 2015-09-15 Semiconductor Components Industries, Llc Singulation method for semiconductor die having a layer of material along one major surface
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
US8796072B2 (en) * 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US10714378B2 (en) 2012-11-15 2020-07-14 Amkor Technology, Inc. Semiconductor device package and manufacturing method thereof
US9209080B2 (en) * 2012-12-14 2015-12-08 Infineon Technologies Ag Semiconductor device comprising a protective structure on a chip backside and method of producing the same
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9824924B2 (en) * 2013-03-29 2017-11-21 Stmicroelectronics Pte Ltd. Semiconductor packages having an electric device with a recess
GB2514547A (en) 2013-05-23 2014-12-03 Melexis Technologies Nv Packaging of semiconductor devices
US9318451B2 (en) 2013-10-31 2016-04-19 Freescale Semiconductor, Inc. Wirebond recess for stacked die
ITTO20130967A1 (en) * 2013-11-28 2015-05-29 Stmicroelectronics Malta Ltd METHOD OF STACKING A PLURALITY OF PLATES TO FORM A STACKED SEMICONDUCTOR DEVICE, AND A STACKED SEMICONDUCTOR DEVICE
EP2947692B1 (en) * 2013-12-20 2020-09-23 Analog Devices, Inc. Integrated device die and package with stress reduction features
US9034694B1 (en) 2014-02-27 2015-05-19 Freescale Semiconductor, Inc. Embedded die ball grid array package
US9418894B2 (en) 2014-03-21 2016-08-16 Semiconductor Components Industries, Llc Electronic die singulation method
TWI591707B (en) * 2014-06-05 2017-07-11 東琳精密股份有限公司 Packaging structure for thin die and method for manufacturing the same
US9385041B2 (en) 2014-08-26 2016-07-05 Semiconductor Components Industries, Llc Method for insulating singulated electronic die
TWI552293B (en) * 2014-09-26 2016-10-01 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10028380B2 (en) * 2014-10-22 2018-07-17 Sandisk Technologies Llc Semiconductor package with dual second level electrical interconnections
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US20160181180A1 (en) * 2014-12-23 2016-06-23 Texas Instruments Incorporated Packaged semiconductor device having attached chips overhanging the assembly pad
US20160229689A1 (en) * 2015-02-11 2016-08-11 Analog Devices, Inc. Packaged Microchip with Patterned Interposer
US9397078B1 (en) * 2015-03-02 2016-07-19 Micron Technology, Inc. Semiconductor device assembly with underfill containment cavity
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
KR20170065397A (en) * 2015-12-03 2017-06-13 삼성전자주식회사 Semiconductor device
US9859382B2 (en) * 2015-12-04 2018-01-02 Globalfoundries Inc. Integrated CMOS wafers
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
KR20170120752A (en) * 2016-04-21 2017-11-01 한국전자통신연구원 Semiconductor devices and Methods for manufacturing the same
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10366923B2 (en) 2016-06-02 2019-07-30 Semiconductor Components Industries, Llc Method of separating electronic devices having a back layer and apparatus
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
WO2018031999A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
EP3497717A1 (en) 2016-08-12 2019-06-19 Qorvo Us, Inc. Wafer-level package with enhanced performance
CN109844937B (en) 2016-08-12 2023-06-27 Qorvo美国公司 Wafer level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10943792B2 (en) 2016-09-27 2021-03-09 Intel Corporation 3D stacked-in-recess system in package
WO2018063196A1 (en) * 2016-09-28 2018-04-05 Intel IP Corporation Systems, methods, and apparatuses for implementing reduced height semiconductor packages for mobile electronics
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
CN108022845B (en) * 2016-11-02 2020-06-26 中芯国际集成电路制造(上海)有限公司 Chip packaging method and packaging structure
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
FR3062237B1 (en) * 2017-01-23 2020-05-01 Commissariat A L'energie Atomique Et Aux Energies Alternatives METHOD FOR PRODUCING AN INTEGRATED CIRCUIT CHIP AND INTEGRATED CIRCUIT CHIP.
KR102255758B1 (en) 2017-04-26 2021-05-26 삼성전자주식회사 Semiconductor device package and method for fabricating the same
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10366972B2 (en) * 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10892212B2 (en) * 2017-11-09 2021-01-12 Stmicroelectronics, Inc. Flat no-lead package with surface mounted structure
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US11139255B2 (en) * 2018-05-18 2021-10-05 Stmicroelectronics (Rousset) Sas Protection of integrated circuits
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
FR3083643B1 (en) * 2018-07-04 2023-01-13 Commissariat Energie Atomique METHOD FOR MAKING AN ELECTRONIC DEVICE
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US10867880B2 (en) * 2018-12-23 2020-12-15 Texas Instruments Incorporated Multi-die module with substrate cavity assembly
US10818551B2 (en) 2019-01-09 2020-10-27 Semiconductor Components Industries, Llc Plasma die singulation systems and related methods
US11705428B2 (en) 2019-01-23 2023-07-18 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
KR20210129656A (en) 2019-01-23 2021-10-28 코르보 유에스, 인크. RF semiconductor device and method of forming same
US11195740B2 (en) * 2019-04-17 2021-12-07 Micron Technology, Inc. Methods and apparatus for wafer handling and processing
US11721657B2 (en) 2019-06-14 2023-08-08 Stmicroelectronics Pte Ltd Wafer level chip scale package having varying thicknesses
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US20230017286A1 (en) * 2021-07-13 2023-01-19 Texas Instruments Incorporated Semiconductor die with stepped side surface

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571611A (en) * 1982-03-31 1986-02-18 Fujitsu Limited Semiconductor chip with a metal heat radiator
JPS62185348A (en) * 1986-02-12 1987-08-13 Oki Electric Ind Co Ltd Bonding method for chip part
JPH02109410A (en) * 1988-10-18 1990-04-23 Clarion Co Ltd Resin seal type semiconductor device
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
US5904497A (en) * 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly
US5910686A (en) * 1998-07-23 1999-06-08 Vlsi Technology, Inc. Cavity down HBGA package structure
JPH11289023A (en) * 1998-04-02 1999-10-19 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
DE10209204A1 (en) * 2002-03-04 2003-10-02 Infineon Technologies Ag Electronic component comprises a stack of semiconductor chips of different size with one chip having a recess on its passive rear side
JP2003282818A (en) * 2002-03-27 2003-10-03 Matsushita Electric Ind Co Ltd Semiconductor device

Family Cites Families (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3449640A (en) * 1967-03-24 1969-06-10 Itt Simplified stacked semiconductor device
US5138438A (en) 1987-06-24 1992-08-11 Akita Electronics Co. Ltd. Lead connections means for stacked tab packaged IC chips
US5019943A (en) 1990-02-14 1991-05-28 Unisys Corporation High density chip stack having a zigzag-shaped face which accommodates connections between chips
JP2953899B2 (en) 1993-02-17 1999-09-27 松下電器産業株式会社 Semiconductor device
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5705483A (en) * 1993-12-09 1998-01-06 Eli Lilly And Company Glucagon-like insulinotropic peptides, compositions and methods
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
JP3479121B2 (en) 1994-08-05 2003-12-15 アピックヤマダ株式会社 Resin molding method for BGA package
US5512549A (en) * 1994-10-18 1996-04-30 Eli Lilly And Company Glucagon-like insulinotropic peptide analogs, compositions, and methods of use
US5874781A (en) 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5886412A (en) * 1995-08-16 1999-03-23 Micron Technology, Inc. Angularly offset and recessed stacked die multichip device
US5952725A (en) 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US7166495B2 (en) * 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
US5859475A (en) 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5986340A (en) 1996-05-02 1999-11-16 National Semiconductor Corporation Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same
US5917242A (en) 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US6784023B2 (en) * 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5760478A (en) 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US6458924B2 (en) * 1996-08-30 2002-10-01 Novo Nordisk A/S Derivatives of GLP-1 analogs
EP0954589A1 (en) * 1997-01-24 1999-11-10 Novo Nordisk A/S Synthetic leader peptide sequences
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
US6081997A (en) 1997-08-14 2000-07-04 Lsi Logic Corporation System and method for packaging an integrated circuit using encapsulant injection
US6441495B1 (en) * 1997-10-06 2002-08-27 Rohm Co., Ltd. Semiconductor device of stacked chips
US6055778A (en) * 1997-12-01 2000-05-02 Aoyama Seisakusho Co., Ltd. Guide slider for window regulator
US6052287A (en) 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier
US6207474B1 (en) 1998-03-09 2001-03-27 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
FR2777283B1 (en) * 1998-04-10 2000-11-24 Adir NOVEL GLUCAGON-PEPTIDE- 1 (7-37) ANALOGUE PEPTIDE COMPOUNDS, PROCESS FOR THEIR PREPARATION AND THE PHARMACEUTICAL COMPOSITIONS CONTAINING THE SAME
US6020629A (en) 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6297548B1 (en) * 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
JP3670853B2 (en) 1998-07-30 2005-07-13 三洋電機株式会社 Semiconductor device
JP3643705B2 (en) 1998-07-31 2005-04-27 三洋電機株式会社 Semiconductor device and manufacturing method thereof
US6720407B1 (en) * 1998-08-28 2004-04-13 Eli Lilly And Company Method for administering insulinotropic peptides
BR9915961A (en) * 1998-12-07 2001-08-21 Sod Conseils Rech Applic Glp-1 analogs
US6351028B1 (en) 1999-02-08 2002-02-26 Micron Technology, Inc. Multiple die stack apparatus employing T-shaped interposer elements
US6239484B1 (en) 1999-06-09 2001-05-29 International Business Machines Corporation Underfill of chip-under-chip semiconductor modules
KR100333388B1 (en) 1999-06-29 2002-04-18 박종섭 chip size stack package and method of fabricating the same
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
US6294839B1 (en) 1999-08-30 2001-09-25 Micron Technology, Inc. Apparatus and methods of packaging and testing die
TW456005B (en) 1999-10-12 2001-09-21 Agilent Technologies Inc Integrated circuit package with stacked dies
US6731009B1 (en) * 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips
US6528393B2 (en) * 2000-06-13 2003-03-04 Advanced Semiconductor Engineering, Inc. Method of making a semiconductor package by dicing a wafer from the backside surface thereof
US6476475B1 (en) * 2000-06-29 2002-11-05 Advanced Micro Devices, Inc. Stacked SRAM die package
TW456013B (en) 2000-07-04 2001-09-21 Advanced Semiconductor Eng Heat spreader substrate structure and the process thereof
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
US6890065B1 (en) * 2000-07-25 2005-05-10 Lexmark International, Inc. Heater chip for an inkjet printhead
JP3533159B2 (en) * 2000-08-31 2004-05-31 Nec化合物デバイス株式会社 Semiconductor device and manufacturing method thereof
US20020096754A1 (en) 2001-01-24 2002-07-25 Chen Wen Chuan Stacked structure of integrated circuits
KR100407472B1 (en) 2001-06-29 2003-11-28 삼성전자주식회사 Chip-Stacked Package Device Having Upper Chip Provided With Corner Trenchs And Method For Manufacturing the Same
US6573592B2 (en) * 2001-08-21 2003-06-03 Micron Technology, Inc. Semiconductor die packages with standard ball grid array footprint and method for assembling the same
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6847105B2 (en) * 2001-09-21 2005-01-25 Micron Technology, Inc. Bumping technology in stacked die configurations
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7332819B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US20030111720A1 (en) 2001-12-18 2003-06-19 Tan Lan Chu Stacked die semiconductor device
JP3507059B2 (en) 2002-06-27 2004-03-15 沖電気工業株式会社 Stacked multi-chip package
US6833287B1 (en) * 2003-06-16 2004-12-21 St Assembly Test Services Inc. System for semiconductor package with stacked dies

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571611A (en) * 1982-03-31 1986-02-18 Fujitsu Limited Semiconductor chip with a metal heat radiator
JPS62185348A (en) * 1986-02-12 1987-08-13 Oki Electric Ind Co Ltd Bonding method for chip part
JPH02109410A (en) * 1988-10-18 1990-04-23 Clarion Co Ltd Resin seal type semiconductor device
US5804004A (en) * 1992-05-11 1998-09-08 Nchip, Inc. Stacked devices for multichip modules
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5904497A (en) * 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly
JPH11289023A (en) * 1998-04-02 1999-10-19 Oki Electric Ind Co Ltd Semiconductor device and manufacture thereof
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US5910686A (en) * 1998-07-23 1999-06-08 Vlsi Technology, Inc. Cavity down HBGA package structure
DE10209204A1 (en) * 2002-03-04 2003-10-02 Infineon Technologies Ag Electronic component comprises a stack of semiconductor chips of different size with one chip having a recess on its passive rear side
JP2003282818A (en) * 2002-03-27 2003-10-03 Matsushita Electric Ind Co Ltd Semiconductor device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 026 (E - 577) 26 January 1988 (1988-01-26) *
PATENT ABSTRACTS OF JAPAN vol. 014, no. 328 (E - 0952) 13 July 1990 (1990-07-13) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 01 31 January 2000 (2000-01-31) *

Also Published As

Publication number Publication date
US20030148597A1 (en) 2003-08-07
US20030207516A1 (en) 2003-11-06
US7332819B2 (en) 2008-02-19
AU2003207484A1 (en) 2003-07-30
US20080096316A1 (en) 2008-04-24
US7332820B2 (en) 2008-02-19
US20060216864A1 (en) 2006-09-28
US7282392B2 (en) 2007-10-16
US20060292745A1 (en) 2006-12-28
US7371608B2 (en) 2008-05-13
WO2003061006A2 (en) 2003-07-24
US20080136045A1 (en) 2008-06-12
US20060292746A1 (en) 2006-12-28
US7282390B2 (en) 2007-10-16
US20080032449A1 (en) 2008-02-07
US7358117B2 (en) 2008-04-15
US20030207515A1 (en) 2003-11-06
US7344969B2 (en) 2008-03-18
US20030162325A1 (en) 2003-08-28
US20060292743A1 (en) 2006-12-28
US20130154117A1 (en) 2013-06-20
WO2003061006B1 (en) 2004-08-26
US7575953B2 (en) 2009-08-18
US8373277B2 (en) 2013-02-12
US7309623B2 (en) 2007-12-18
US7799610B2 (en) 2010-09-21

Similar Documents

Publication Publication Date Title
WO2003061006A3 (en) Stacked die in die bga package
AU2002311762A1 (en) Semiconductor chip having multiple conductive layers in an opening, and method for fabricating same
SG115456A1 (en) Semiconductor die packages with recessed interconnecting structures and methods for assembling the same
AU2003242012A1 (en) Semiconductor device and method for fabricating the same
TW200520190A (en) Fan out type wafer level package structure and method of the same
SG102638A1 (en) Lead frame, semiconductor package having the same, and semiconductor package manufacturing method
AU2003218322A1 (en) Method and apparatus for stacking multiple die in a flip chip semiconductor package
EP1513198A4 (en) Semiconductor substrate manufacturing method and semiconductor device manufacturing method, and semiconductor substrate and semiconductor device manufactured by the methods
AU2003279215A1 (en) Components, methods and assemblies for multi-chip packages
EP1657748A4 (en) Semiconductor device, method for manufacturing same, and power converter using such semiconductor device
WO2002047162A3 (en) Microelectronic package having an integrated heat sink and build-up layers
WO2007006001A3 (en) Iii-nitride enhancement mode devices
EP1617483A4 (en) Semiconductor device and process for fabricating the same
SG111069A1 (en) Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
EP1555690A4 (en) Pasted soi substrate, process for producing the same and semiconductor device
AU2002355015A1 (en) Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus
EP1482561A4 (en) Organic semiconductor structure, process for producing the same, and organic semiconductor device
AU2003211575A1 (en) Semiconductor substrate, semiconductor chip, and semiconductor device manufacturing method
AU2003275614A1 (en) Semiconductor device and method for manufacturing semiconductor device
AU2003275615A1 (en) Semiconductor device and method for manufacturing semiconductor device
AU5109000A (en) Semiconductor package, semiconductor device, electronic device and production method for semiconductor package
WO2005050701A8 (en) Stressed semiconductor device structures having granular semiconductor material
EP1620894A4 (en) Substrate, manufacturing method therefor, and semiconductor device
AU2002219529A1 (en) Semiconductor device and method for fabricating the same
EP1708276A4 (en) Vertical gate semiconductor device and process for fabricating the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
B Later publication of amended claims

Effective date: 20040628

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP