WO2003094341A1

WO2003094341A1 - Integrated circuit for correcting an offset voltage.

Info

Publication number: WO2003094341A1
Application number: PCT/IB2003/001589
Authority: WO
Inventors: Patrick Mone
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2002-04-30
Filing date: 2003-04-22
Publication date: 2003-11-13
Also published as: AU2003216685A1; TW200402948A

Abstract

The invention relates to an integrated circuit (IC) comprising a circuit (DEVICE) having an offset voltage (VOS/VOFF) and designed for receiving an input voltage (VIN), and calibration means (CAL) of said circuit (DEVICE) for correcting the offset voltage (VOS/VOFF). It is characterized in that the calibration means (CAL) comprise: - interruption means (SWITCH) for short-circuiting the input voltage (VIN) of a circuit (DEVICE), - detection means (COMP) for detecting the sign (S SIGN) of the offset voltage VOS/VOFF), - definition means (SAR) for defining a digital correction signal defined by successive steps (S MOT) as a function of the sign (S SIGN) of the offset voltage (VOS/VOFF), and - correction means (D/A) for correcting the offset voltage (VOS/VOFF) as a function of the digital correction signal (S MOT).

Description

Integrated circuit for correcting an offset voltage

DESCRIPTION Field of the invention

The invention relates to an integrated circuit comprising a circuit which has an offset voltage and designed for receiving an input voltage, and calibration means of said circuit for correcting the offset voltage. It also relates to a method of calibrating a circuit.

It finds its application in particular in mobile telephones at the level of their receiver part.

Prior art A receiver of a mobile telephone receives input signals transmitted by one or several base stations. The receiver comprises an integrated circuit capable of processing these transmitted signals. Such an integrated circuit comprises a number of internal circuits. Unfortunately, each internal circuit has an inherent offset voltage caused by the transistors from which it is built up. Such a voltage is detrimental to the receiver because it diminishes its sensitivity by approximately 10 to 15 dB. As a result, the receiver will no longer detect and process the received signals correctly.

The publication entitled 'High Speed CMOS Comparator for Use in an ADC published in the journal IEEE <Solid State Circuits> vol. 23, no. 1, February 1988, describes an analog calibration system capable of correcting an offset voltage, which system is based on capacitors and on an amplifier stage, also referred to as a buffer. The calibration system supplies a correction voltage which is transformed into a current by the amplifier stage, thus providing a correction of said offset voltage, said capacitors serving as memories for the correction voltage.

Although this prior art renders possible a correction of the offset voltage, it does not do so until after a delay of several microseconds after reception of the signal. The capacitors in fact have an intrinsic leakage current which prevents them from memorizing the correction voltage for a long period, which is disadvantageous in the operation of the integrated circuit because the offset voltage or voltages will be present again in said integrated circuit after a few microseconds. Furthermore, the prior art system dissipates much power because of the use of the capacitors.

Summary of the invention

A problem to be resolved by the object of the present invention is accordingly to propose an integrated circuit comprising a circuit having an offset voltage and designed for receiving an input voltage, and calibration means of said circuit for correcting the offset voltage in which it is possible to correct the offset voltage throughout the operation of said integrated circuit and without consuming a considerable amount of power.

One solution to the technical problem posed, according to a first object of the invention, is characterized in that the calibration means comprise:

- interruption means for short-circuiting the input voltage of a circuit,

- detection means for detecting the sign of the offset voltage, - definition means for defining a digital correction signal defined by successive steps as a function of the sign of the offset voltage, and

- correction means for correcting the offset voltage as a function of the digital correction signal.

According to a second object of the invention, this solution is characterized in that the calibration procedure of the system comprises the steps of:

- short-circuiting the input voltage of a circuit,

- detecting the sign of the offset voltage,

- defining a digital correction signal in successive steps as a function of the sign of the offset voltage, and - correcting the offset voltage as a function of the digital correction signal.

As will be seen in detail further below, the detection, definition, and correction means thus define a digital compensation loop for the offset voltage, correcting the offset voltage with very fine tuning down to practically zero thanks to the determination of a digital correction signal in successive steps. The fact that no capacitors are used, furthermore, renders it possible to reduce the power consumption of the calibration means.

Advantageously, in a non-limitative embodiment, such a calibration is performed at each initialization, i.e. each time the power for the integrated circuit is switched on. The calibration is furthermore advantageously performed cyclically when said circuit is not in a communication phase. Thus the correction of the offset voltage is not lost when the power is switched on. In addition, it takes place while taking into account the evolving qualities of the electrical components of the circuit, whose characteristics change over time, the ambient temperature, etc.

Brief description of the Figures

The following description given with reference to the annexed drawings, all by way of example to which the invention is by no means limited, will make it clear of what the invention consists.

- Fig. 1 diagrammatically shows an architecture of the integrated circuit comprising a first embodiment of calibration means according to the invention,

- Fig. 2 shows digital signals used for controlling the calibration means of Fig. 1,

- Fig. 3 is a time diagram showing the control signals and the signals processed by the calibration means of Fig. 1,

- Fig. 4 is a time diagram showing the signals generated by means for defining a digital voltage correction signal, means for detecting the sign of a voltage, and voltage correction means, forming part of the calibration means of Fig. 1,

- Fig. 5 is a diagram representing a correction current generated by the voltage correction means which are part of the calibration means of Fig. 1, and

- Fig. 6 diagrammatically shows the architecture of the integrated circuit comprising a second embodiment of the calibration means according to the invention.

Description of the invention Functions or structures known to those skilled in the art will not be described in detail in the following description so as not to make the latter unnecessarily bulky.

The present discussion of the invention relates to an example of an integrated circuit used in the field of mobile telephony, in particular integrated in a receiver of a portable or mobile telephone, which receiver is designed for receiving one or several input signals transmitted by one or several base stations.

Such an integrated circuit is shown in Fig. 1. This circuit IC comprises at least one circuit DENICE. The latter is designed for receiving an input voltage NIΝ and supplying an output voltage VOUT. Such a circuit DEVICE has an offset voltage which is inherent in the components such as the transistors from which it is formed. Said voltage is referenced VOS at the input and NOFF at the output, for which it is true that VOS = A*VOFF, A being the gain of the circuit DEVICE.

The integrated circuit IC further has calibration means CAL comprising:

- interruption means (SWITCH) for short-circuiting the input voltage (VIΝ) of a circuit (DEVICE),

- detection means (COMP) for detecting the sign (S_SIGΝ) of the offset voltage VOS/NOFF),

- definition means (SAR) for defining a digital correction signal defined by successive steps (S_MOT) as a function of the sign (S_SIGΝ) of the offset voltage (VOS/NOFF), and

- correction means (D/A) for correcting the offset voltage (VOS/NOFF) as a function of the digital correction signal (S_MOT).

The integrated circuit IC in addition comprises a logic and/or hardware control system CΝTRL designed for controlling the calibration means CAL. The interruption means SWITCH are preferably formed by an analog switch, the detection means COMP are a comparator, the definition means SAR are a successive approximate logic circuit known to those skilled in the art, and the correction means D/A are a digital-analog converter.

The comparator COMP is located at the output of the circuit DEVICE. This has the advantage that it enables said comparator to operate at a high voltage, i.e. the offset voltage at the output VOFF, which is more convenient. The offset voltage VOFF at the output is in fact greater than the offset voltage VOS at the input because it has been amplified by the gain A of the circuit DEVICE. It can be seen that the comparator also has its own offset voltage. The fact that it is placed at the output of the circuit DEVICE has the second advantage that it has its own offset divided by the gain A of the circuit DEVICE. Said voltage thus becomes very low and will not interfere with the general operation of the calibration means CAL.

As for the D/A converter, which also has its own offset voltage, the latter will be the lower and accordingly the more negligible as the steps for determining the correction signal S_MOT are smaller, i.e. as the resolution of the correction signal is higher.

It can be seen that the integrated circuit IC operates at a certain frequency defined by a clock CLK as a function of the desired application. The frequency may be defined in a manner known to those skilled in the art, for example by means of frequency dividers in the integrated circuit IC. It may further be noted that the integrated circuit IC is a mixed one, i.e. digital-analog, since it comprises analog elements (the comparator COMP) and digital elements (The logic circuit SAR, the converter D/A). When the receiver and subsequently the integrated circuit IC receive an input signal (not shown) transmitted by a base station (not shown), they will process this signal such that it is detected and received without errors by the mobile telephone. To achieve this, the sensitivity of the receiver must remain substantially constant so as to be able to detect the input signal correctly. It is therefore necessary, so as not to disturb this sensitivity, to correct the offset voltage VOS NOFF of each circuit DEVICE of the integrated circuit IC which would involve a risk of covering said input signal. An offset voltage in fact corresponds to a noise usually referred to as DC noise in which the received input signal could be drowned.

The integrated circuit IC will accordingly be calibrated such that the offset voltage VOS/NOFF is corrected.

In a first step 1), the calibration is carried out.

In a first sub-step la) shown in Fig. 1, the control system CΝTRL of the integrated circuit IC emits a first signal OΝCAL. It is in the high state then. This first signal OΝCAL triggers the following: - firstly, initializing of the element SWITCH such that the input of the circuit

DEVICE is short-circuited. This prevents the reception of any input signal from interfering with the calibration, and

- secondly, activating of the comparator COMP which detects the sign of the offset voltage VOFF at the output of the integrated circuit IC. This comparator COMP need only be active, i.e. energized, during the calibration period. The first signal OΝCAL activating this comparator is accordingly in the high state throughout the entire calibration period.

In a second sub-step lb), the control system CΝTRL triggers the calibration by means of a start signal STARTCAL. The calibration is started on a rising edge. The signal STARTCAL then returns to the low state, whereupon the integrated circuit begins the calibration phase.

It will be noted that no calibration is triggered as long as the signal STARTCAL is in the low state. It will also be noted that the integrated circuit IC operates on a rising or falling edge of the clock CLK. Said signal STARTCAL must also be at least equal in length to one cycle of the clock CLK in order to make sure that the start signal STARTCAL will be taken up by the clock CLK.

In a second step 2), the calibration is carried out as follows. With the element SWITCH in the closed position, the input and output voltages VIN and VOUT of the circuit DEVICE are zero. The offset voltages at the input VOS and at the output VOFF, however, remain.

In a first sub-step 2a), the sign of the output voltage offset VOFF is determined by the comparator COMP. This comparator COMP emits a sign signal S_SIGN in dependence on the sign of the offset voltage VOFF.

This sign signal S SIGN is represented here by a logic bit and is transmitted to the successive approximate logic circuit SAR. Such a logic circuit SAR is based on a word S_MOT of N bits. At each reception of a result from the comparator COMP, such as the sign signal S_SIGN in this case, it verifies one of the N bits of the word and sets it for 1 or 0. If the sign signal S SIGN of the comparator COMP is positive, i.e. set for 1, the bit current associated with the word S_MOT is set to 0 and the next bit is set for 1. In the opposite case the associated bit current is set for 1. The logic circuit requires only N iterations for N bits, i.e. one for each bit of the word.

The logic circuit SAR thus generates a digital correction signal S_MOT which is a word of N bits, N defining a number of steps, as a function of the sign signal S_SIGN. Preferably, N = 8 bits. Said word S_MOT renders it possible to determine a precise correction for the offset voltage VOFF at the output, as will become clear further below.

The logic circuit SAR is also capable of retaining these 8 compensation bits in its memory while the calibration phase is active. This enables the D/A converter to use these 8 bits subsequently as an input and to derive a voltage correction signal from them.

In a second sub-step 2b), therefore, the word S_MOT of N bits is sent to the digital/analog converter D/A, which converts said word S_MOT into an analog signal which corrects the offset voltage VOFF at the output of the circuit DEVICE. The correction takes place progressively because it is effected as a function of the digital correction signal S_MOT which is fed cyclically to the D/A converter until the offset voltage VOFF is substantially zero, as will be seen further below. It may thus be said that the assembly of the comparator COMP, the logic circuit SAR, and the digital/analog converter D/A form a compensation loop for the offset voltage VOS/NOFF of the circuit DEVICE.

Preferably, the digital/analog converter D/A converts the word S_MOT into an analog current rather than a voltage. This analog current is capable of correcting the offset voltage.

It will be noted that a circuit DEVICE usually comprises a differential stage which supplies carries two currents and delivers a corresponding voltage at the output. These two currents are identical if the offset voltage VOS at the input is zero. If the latter in not zero, however, there will be an imbalance in the output currents of the differential stage, which imbalance is to be eliminated.

The D/A converter is also preferably differential and thus delivers two currents IDACP and IDACΝ, which are positive and negative, respectively, at its output. These two currents render it possible to obtain an imbalance inverse to that of the circuit DEVICE, thus correcting the offset voltage thereof. The difference between these two currents IDACP and IDACΝ then represents a correction current ICORR.

It will be noted that the use of a digital/analog converter D/A offers the advantage that no capacitors are used. On the one hand, this means a saving in space on the silicon of the integrated circuit IC, and on the other hand a saving in energy, while finally the errors caused by inherent capacitor imperfections are avoided. Furthermore, the presence of a current instead of a voltage offers as a second advantage that this current is directly injected into the circuit DEVICE without passing through a buffer which usually serves to convert a voltage into a current. Even more space is saved on the silicon of the integrated circuit IC thereby. It will also be noted that the digital/analog converter D/A is designed such that a monotonic converter D/A is obtained. There will be no risk then of the converter providing a negative output instead of a positive output.

Finally, the combination of the logic circuit SAR and the digital/analog converter D/A renders it possible to correct an offset voltage throughout the entire period when the integrated circuit IC is under power. The correction values represented by the word S_MOT are safeguarded throughout its period under power, i.e. longer than if capacitors were used, the latter being known to have a shorter memory time because of their leakage currents. On the other hand, capacitors reduce the efficacy of integrated circuits owing to manufacturing defects in the gate oxide leading to gate oxide breakthrough. It may thus be seen that the integrated circuit IC according to the invention comprises exclusively simple elements. The comparator COMP, which does not require a very high gain, may be composed, for example, of a differential pair followed by an inverter. In addition, the integrated circuit IC according to the invention does not require any external element or expensive special treatment such as a laser calibration.

An example of a calibration is shown in Figs. 3 and 4. In Fig. 3, the circuit DEVICE operates at a supply voltage of 1.8 V. Before a moment Tl, i.e. before the calibration phase, the input voltage VIN oscillates between deviation peaks of 10 mV, which peaks are centered on a central voltage of -35 mV. Because of this high voltage, the output voltage VOUT is zero and the input signal is not detected.

The trigger signal STARTCAL for the calibration is activated at the moment Tl . The input voltage VIN ought to be zero now, but instead it has a value of -35 mV corresponding to the offset voltage VOS at the input of the circuit DEVICE. Between the moments T2 and T2, the calibration means CAL obtain the compensation bits at the output of the converter D/A for compensating the offset voltage VOFF at the output at accordingly VOS at the input. When the calibration has been completed, at moment T3, the calibration means CAL send a signal CALDONE signaling the end of the calibration to the control system CNTRL of the integrated circuit IC. This notifies to the integrated circuit IC that it can return to its operational state. After that, at moment T4, it can be seen that the input voltage VIN is no longer short-circuited and that the output voltage VOUT is detected. It is noted that the first signal ONCAL is activated well before the trigger signal STARTCAL.

Fig. 4 shows the internal signals such as the signal S_SIGN provided by the comparator COMP, the digital correction signal S MOT provided by the logic circuit SAR to the input of the converter D/A in the form of N = 8 bits BIT, and the output of the converter D/A represented by the two currents IDACN (negative) and IDACP (positive).

These currents are programmed in software and/or hardware in the converter D/A in dependence on the values of the N bits BIT.

Each bit BIT represents a weighting factor for a correction current ICORR resulting from the negative and positive currents IDACN and IDACP. The 8 bits BIT thus have respective weights of ^lΔ, VA, 1/8, 1/16, 1/32, 1/64, 1/128, and 1/256, the seventh bit BIT7 being the most significant bit MSB because it has the highest weight factor 1/2.

In this example, the central point for the sign S_SIGN of the offset voltage is 0.9 V, the supply voltage being 1.8 V. Before the calibration starts, at moment TO, the seventh bit BIT7 is set for 1 and all the other bits are set for 0. Similarly, the sign signal S_SIGN is set for 1.

At the start of calibration, at moment Tl, the offset voltage at the output VOFF is lower than the central point of 0.9 V and is accordingly regarded as negative. The bit 7 of the sign signal S_SIGN is subsequently set for zero. At the same time the bit 6 is set for 1. The converter D/A calculates the correction current ICORR and the corresponding negative and positive currents, injecting the latter two into the circuit DEVICE. Then the offset voltage VOFF at the output is modified.

The comparator COMP determines the sign of the new offset voltage value VOFF. At moment T2 the value VOFF is always lower than the central point of 0.9 V. Subsequently the bit 6 of the sign signal S_SIGN is set for 0. At the same time the bit 5 is set for 1. The converter D/A calculates the new correction current ICORR and the corresponding negative and positive currents and injects the latter two into the circuit DEVICE. The offset voltage VOFF at the output is then modified again.

The comparator COMP determines the sign of the new value of the offset voltage VOFF. At moment T3 the value of VOFF is now lower than the central point of 0.9 V and is accordingly regarded as positive. Bit 5 of S_SIGN remains at 1 after this. At the same time the bit 4 is set for 1. The converter D/A calculates the new correction current ICORR and the corresponding negative and positive currents and injects the latter two into the circuit DEVICE. The offset voltage VOFF at the output is again modified after this. The comparator COMP determines the sign of the new value of the offset voltage VOFF ..., etc., up to the moment T8 at which all 8 bits have been correctly calibrated and the offset voltage VOFF at the output has been corrected. The Table below is an example of the calibration of the 8 bits BIT of the digital voltage correction signal S_MOT.

Fig. 5 is a graph showing the correction current ICORR calculated by the converter D/A as a function of the weightings of the 8 bits BIT which form the digital voltage correction signal S_MOT. It is apparent that the instantaneous value of the correction current ICORR is plotted on the ordinate and the number of the iteration step on the abscissa. The correction current ICORR can assume a maximum value of IMAX. The following equations are valid: IDACP = lb + IM AX/2

IDACN = lb - IMAX 2

IDACP - IDACN = IMAX lb herein represents the bias current of the converter D/A.

The parameters for this maximum value IMAX are determined in the design of the integrated circuit IC as a function of the circuit DEVICE to be corrected, of the maximum offset voltage to be corrected, etc.. Thus, for example, if the circuit DEVICE is a limiter and the maximum offset voltage is 60 mV in the application considered of a mobile telephone, IMAX will be equal to 15 μA. Before the first iteration step the instantaneous value of the correction current ICORR corresponds to the maximum value IMAX/2. During the first iteration step its value is IMAX/4. Then it is IMAX/8 in the third step, and so on until the final step 8 where it is IMAX/8 + IMAX/16 + IMAX/64 + IMAX/ 128. The value of the offset voltage VOFF to be corrected is thus approached progressively as a result of this stepwise definition of the digital correction signal S_MOT and thus of the correction current ICORR. The higher the number of bits N in the digital correction signal S_MOT, the smaller the steps and the higher the resolution of this signal; as a result the offset voltage will be better corrected and accordingly eliminated.

At the end of the calibration process, therefore, the offset voltage VOFF at the output has been very accurately corrected so as to be substantially eliminated; and as a result the offset voltage VOS at the input, which is dependent on the offset voltage VOFF at the output (VOS = VOFF/ A), in its turn is also corrected.

In a third step3), when the calibration, i.e. the correction of the offset voltage VOS/NOFF, has been completed, all bits of the word S_MOT have been used (they are counted by an internal counter which is not shown), a stop signal CALDONE is sent to the control system CNTRL of the integrated circuit IC. This may be a pulse or a change in state. The calibration is then stopped. Subsequently, cf. Fig. 3, the first signal ONCAL is no longer emitted, it is deactivated and accordingly set for the low state. The element SWITCH is switched off thereby, i.e. opened, and the integrated circuit returns to its operational state. Furthermore, the comparator COMP is deactivated , i.e. extinguished. The comparator

COMP no longer consumes power then when not in use, which provides a saving in energy.

It will be noted the calibration is carried out upon each initialization or power switch-on of the receiver comprising the integrated circuit IC, i.e. the calibration means CAL are energized at each switch-on of the integrated circuit IC. This renders it possible to reinitialize the word S_MOT, which is deleted from the memory of the logic circuit SAR at each power switch-on.

It will further be noted that this calibration phase is repeated cyclically (in a programmable cycle), preferably of the order of a minute, whenever the receiver does not communicate with a base station. These periods of non-communication are known in the receiver at the level of a communication controller (not shown) of the mobile telephone. This renders it possible to make adaptations in time and to take into account the variations in offset voltage of a circuit DEVICE, said voltage varying as a function of developments of the components of said circuit over time, as a function of temperature, etc.. The fact that the calibration is not continually carried out, furthermore, leads to a reduction in the power consumption at the level of the integrated circuit IC (especially because the comparator COMP is off). Obviously, the scope of the invention is by no means limited to the embodiments described above, and variations or modifications may be applied without departing from the spirit and scope of the invention. Thus there may be several circuits DEVICE in series in the integrated circuit IC, each having an offset voltage that is to be corrected, for example two circuits DEVICE 1 and DEVICE2 as shown in Fig. 5, in which case the calibration means CAL will be configured so as to eliminate the interference caused by two input offset voltages VOS1 and VOS2 of the two circuits DEVICE 1 and DEVICE2 such that the second offset voltage VOS2 takes into account the first offset voltage VOS1.

It suffices to connect the element SWITCH to the input of the first circuit DEVICE 1 and the compensation loop comprising the comparator COMP, the logic circuit SAR, and the converter D/A to the second circuit DEVICE2. The second offset voltage VOS2 of the second circuit DEVICE2 is corrected thereby, and as a result the interference caused by the offset voltages VOS1 and VOS2 of the two circuits is eliminated. The first circuit DEVICE 1 is, for example, a channel filter, and the second circuit DEVICE2 a limiter.

It is noted that in practice the integrated circuit IC may be implemented, for example, in theθ.18 μm CMOS technology. The element SWITCH then is an analog CMOS complementary switch, and the comparator COMP is an NMOS differential pair followed by a differential conversion stage with one output.

Obviously, the invention is by no means limited to the field of mobile telephony, but may be applied to other fields, in particular all those in which an integrated circuit comprising circuits such as limiters, operational amplifiers, fields relating to telecommunications, imaging technology, television, etc.. Reference symbols used in the present text should not be interpreted as limiting said text in any way.

The verb "comprise" in all its forms should not be interpreted in a limiting manner, i.e. it should not be interpreted as excluding the presence of elements or steps other than those defined in the description or indeed excluding the presence of a plurality of elements or steps listed after said verb and preceded by the article "a" or "an".

Claims

CLAIMS:

1. An integrated circuit (IC) comprising a circuit (DEVICE) having an offset voltage (VOS/VOFF) and designed for receiving an input voltage (VIN), and calibration means (CAL) of said circuit (DEVICE) for correcting the offset voltage (VOS/NOFF), characterized in that the calibration means (CAL) comprise: - interruption means (SWITCH) for short-circuiting the input voltage (VIΝ) of a circuit (DEVICE),

- detection means (COMP) for detecting the sign (S_SIGΝ) of the offset voltage VOS/VOFF),

- definition means (SAR) for defining a digital correction signal defined by successive steps (S_MOT) as a function of the sign (S_SIGN) of the offset voltage (VOS/NOFF), and

2. An integrated circuit as claimed in claim 1, characterized in that the digital correction signal (S_MOT) is a word of Ν bits, Ν defining the number of steps.

3. An integrated circuit as claimed in claim 1, characterized in that the correction means (D/A) deliver an analog current (IDACP, IDACΝ).

4. An integrated circuit as claimed in claim 1, characterized in that the integrated circuit (IC) in addition comprises a control system (CΝTRL) designed for emitting a first signal (OΝCAL) to initialize/switch off the interruption means (SWITCH) and to activate/deactivate the detection means (COMP) for the sign of the offset voltage (VOS/VOFF), and a trigger signal (STARTCAL) for starting a calibration.

5. An integrated circuit as claimed in claim 4, characterized in that the control system (CΝTRL) is in addition designed for receiving a stop signal (CALDONE) for the calibration.

6. A method of calibrating a circuit (DEVICE) contained in an integrated circuit (IC), which circuit (DEVICE) has an offset voltage (VOS/NOFF) and is designed for receiving an input voltage (VIΝ), characterized in that it comprises the steps of: - short-circuiting the input voltage (VIΝ) of a circuit (DEVICE),

- detecting the sign (S_SIGΝ) of the offset voltage (VOS/NOFF),

- defining a digital correction signal (S_MOT) in successive steps as a function of the sign (S_SIGΝ) of the offset voltage (VOS/NOFF), and

- correcting the offset voltage (NOS/NOFF) as a function of the digital correction signal (S_MOT).

7. A method of calibrating a circuit (DEVICE) contained in an integrated circuit (IC) as claimed in claim 6, characterized in that it is performed upon each initialization of the integrated circuit (IC).

8. A method of calibrating a circuit (DEVICE) contained in an integrated circuit (IC) as claimed in claim 6, characterized in that it is performed cyclically when the integrated circuit (IC) is not in a communication phase.

9. A method of calibrating a circuit (DEVICE) contained in an integrated circuit

(IC) as claimed in claim 6, characterized in that it comprises the following further steps:

- emitting a first signal (OΝCAL) for initializing/switching off the interruption means (SWITCH) and for activating/deactivating the detection means (COMP) for the sign of the offset voltage (VOS/VOFF), and - emitting a trigger signal (STARTCAL) for starting said calibration.

10. A receiver designed for receiving an input signal processed by an integrated circuit (IC) as claimed in any one of the claims 1 to 5.