WO2004013897A3 - Memory hub and access method having internal row caching - Google Patents

Memory hub and access method having internal row caching Download PDF

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Publication number
WO2004013897A3
WO2004013897A3 PCT/US2003/024242 US0324242W WO2004013897A3 WO 2004013897 A3 WO2004013897 A3 WO 2004013897A3 US 0324242 W US0324242 W US 0324242W WO 2004013897 A3 WO2004013897 A3 WO 2004013897A3
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WO
WIPO (PCT)
Prior art keywords
memory
read
data
row
memory hub
Prior art date
Application number
PCT/US2003/024242
Other languages
French (fr)
Other versions
WO2004013897A2 (en
Inventor
Joseph M Jeddeloh
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2004526350A priority Critical patent/JP4517237B2/en
Priority to EP03767100.5A priority patent/EP1546885B1/en
Priority to AU2003258015A priority patent/AU2003258015A1/en
Publication of WO2004013897A2 publication Critical patent/WO2004013897A2/en
Publication of WO2004013897A3 publication Critical patent/WO2004013897A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Abstract

A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.
PCT/US2003/024242 2002-08-05 2003-08-01 Memory hub and access method having internal row caching WO2004013897A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004526350A JP4517237B2 (en) 2002-08-05 2003-08-01 Memory hub with internal row caching and access method.
EP03767100.5A EP1546885B1 (en) 2002-08-05 2003-08-01 Memory hub and access method having internal row caching
AU2003258015A AU2003258015A1 (en) 2002-08-05 2003-08-01 Memory hub and access method having internal row caching

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/213,038 US7117316B2 (en) 2002-08-05 2002-08-05 Memory hub and access method having internal row caching
US10/213,038 2002-08-05

Publications (2)

Publication Number Publication Date
WO2004013897A2 WO2004013897A2 (en) 2004-02-12
WO2004013897A3 true WO2004013897A3 (en) 2004-05-06

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/024242 WO2004013897A2 (en) 2002-08-05 2003-08-01 Memory hub and access method having internal row caching

Country Status (8)

Country Link
US (2) US7117316B2 (en)
EP (1) EP1546885B1 (en)
JP (1) JP4517237B2 (en)
KR (1) KR100950871B1 (en)
CN (1) CN100334564C (en)
AU (1) AU2003258015A1 (en)
TW (1) TWI325110B (en)
WO (1) WO2004013897A2 (en)

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US8954687B2 (en) 2015-02-10
WO2004013897A2 (en) 2004-02-12
US20040024978A1 (en) 2004-02-05
EP1546885A2 (en) 2005-06-29
CN100334564C (en) 2007-08-29
TW200421087A (en) 2004-10-16

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