WO2004032144A3 - Spacer integration scheme in mram technology - Google Patents

Spacer integration scheme in mram technology Download PDF

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Publication number
WO2004032144A3
WO2004032144A3 PCT/EP2003/010678 EP0310678W WO2004032144A3 WO 2004032144 A3 WO2004032144 A3 WO 2004032144A3 EP 0310678 W EP0310678 W EP 0310678W WO 2004032144 A3 WO2004032144 A3 WO 2004032144A3
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WO
WIPO (PCT)
Prior art keywords
spacer
layer
etch
formation
integration scheme
Prior art date
Application number
PCT/EP2003/010678
Other languages
French (fr)
Other versions
WO2004032144A2 (en
Inventor
Greg Costrini
John P Hummel
Kia-Seng Low
Frank Findeis
Igor Kasko
Wolfgang Raberg
Original Assignee
Infineon Technologies Ag
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Ibm filed Critical Infineon Technologies Ag
Priority to EP03779791A priority Critical patent/EP1547148B1/en
Publication of WO2004032144A2 publication Critical patent/WO2004032144A2/en
Publication of WO2004032144A3 publication Critical patent/WO2004032144A3/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment

Abstract

A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
PCT/EP2003/010678 2002-10-01 2003-09-24 Spacer integration scheme in mram technology WO2004032144A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP03779791A EP1547148B1 (en) 2002-10-01 2003-09-24 Spacer integration scheme in mram technology

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/261,709 2002-10-01
US10/261,709 US6985384B2 (en) 2002-10-01 2002-10-01 Spacer integration scheme in MRAM technology

Publications (2)

Publication Number Publication Date
WO2004032144A2 WO2004032144A2 (en) 2004-04-15
WO2004032144A3 true WO2004032144A3 (en) 2004-08-05

Family

ID=32030041

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2003/010678 WO2004032144A2 (en) 2002-10-01 2003-09-24 Spacer integration scheme in mram technology

Country Status (4)

Country Link
US (2) US6985384B2 (en)
EP (1) EP1547148B1 (en)
TW (1) TWI243430B (en)
WO (1) WO2004032144A2 (en)

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US8747680B1 (en) * 2012-08-14 2014-06-10 Everspin Technologies, Inc. Method of manufacturing a magnetoresistive-based device
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KR102259870B1 (en) 2014-07-30 2021-06-04 삼성전자주식회사 Memory device and forming the same
KR102276541B1 (en) 2014-11-27 2021-07-13 삼성전자주식회사 Magnetic memory devices and method of manufacturing the same
US9793470B2 (en) 2015-02-04 2017-10-17 Everspin Technologies, Inc. Magnetoresistive stack/structure and method of manufacturing same
US10483460B2 (en) 2015-10-31 2019-11-19 Everspin Technologies, Inc. Method of manufacturing a magnetoresistive stack/ structure using plurality of encapsulation layers
US9502640B1 (en) 2015-11-03 2016-11-22 International Business Machines Corporation Structure and method to reduce shorting in STT-MRAM device
EP3319134B1 (en) * 2016-11-02 2021-06-09 IMEC vzw An sot-stt mram device and a method of forming an mtj
US10069064B1 (en) * 2017-07-18 2018-09-04 Headway Technologies, Inc. Memory structure having a magnetic tunnel junction (MTJ) self-aligned to a T-shaped bottom electrode, and method of manufacturing the same
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CN110176535A (en) * 2019-04-08 2019-08-27 复旦大学 A kind of three-dimensional storage and preparation method thereof in self-positioning resistive region
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Also Published As

Publication number Publication date
US20050146927A1 (en) 2005-07-07
US20040063223A1 (en) 2004-04-01
US6985384B2 (en) 2006-01-10
EP1547148A2 (en) 2005-06-29
TW200406034A (en) 2004-04-16
EP1547148B1 (en) 2012-11-28
WO2004032144A2 (en) 2004-04-15
TWI243430B (en) 2005-11-11

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