WO2004074977A2 - Memory system in a dual processor device and a method of initialising memory in a dual processor device - Google Patents

Memory system in a dual processor device and a method of initialising memory in a dual processor device Download PDF

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Publication number
WO2004074977A2
WO2004074977A2 PCT/PL2004/000009 PL2004000009W WO2004074977A2 WO 2004074977 A2 WO2004074977 A2 WO 2004074977A2 PL 2004000009 W PL2004000009 W PL 2004000009W WO 2004074977 A2 WO2004074977 A2 WO 2004074977A2
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WO
WIPO (PCT)
Prior art keywords
memory
processor
software
master processor
slave
Prior art date
Application number
PCT/PL2004/000009
Other languages
French (fr)
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WO2004074977A3 (en
Inventor
Michal Polak
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Advanced Digital Broadcast Ltd.
Advanced Digital Broadcast Polska Sp. Z O.O.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Digital Broadcast Ltd., Advanced Digital Broadcast Polska Sp. Z O.O. filed Critical Advanced Digital Broadcast Ltd.
Publication of WO2004074977A2 publication Critical patent/WO2004074977A2/en
Publication of WO2004074977A3 publication Critical patent/WO2004074977A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4405—Initialisation of multiprocessor systems

Definitions

  • the invention relates to a memory system in a dual processor device and a method of initiating memory in a dual processor device, in which the processors operate the same software, executed in separate memory blocks.
  • the device may be a digital television decoder.
  • TV 2 Independent reception of television signal in two television receivers TV 1 , TV 2 typically requites independent signals to be supplied from two independent sources.
  • these sources may be digital television decoders, also called integrated receiver decoders (IRD), or set-top boxes (STB).
  • IRD integrated receiver decoders
  • STB set-top boxes
  • the signal to television receivers TV 1 , TV 2 can be supplied from one decoder STB, which has a possibility of independent processing of two television signal streams.
  • Such digital television decoder STB is usually equipped with two interfaces of a remote control unit RCU INT 1 , RCU INT 2. Each interface is linked to one remote control unit RCU 1 , RCU 2.
  • RCU INT 1 remote control unit
  • RCU 2 remote control unit
  • one of the possible solutions is to install in the decoder a signal-receiving block with a processor, which can independently process two signals.
  • processors offering such functionality are advanced and quite expensive devices. Moreover, they require special software. Such software is not known to an engineer, who is acquainted in his day-to-day work with typical processors for processing only one television signal.
  • Another solution to provide the above functionality is to use in the digital television decoder STB two independent signal processing blocks SPB 1 and SPB 2, with an independent processor in each block.
  • the processor which is the main part of the signal-processing block SPB 1.
  • SPB 2 performs descrambling, decompression and other operations on the processed signal.
  • the operation of the processor is controlled by software, stored in memory.
  • FIG. 2 A typical and obvious configuration of a memory system in a dual processor decoder is shown in FIG. 2. This configuration can also be used in other dual processor devices.
  • the system incorporates two processors, linked bidirectionally, i.e. processor P 1 and processor P 2.
  • Processor P 1 is bidirectionally linked with a memory block RAM 1 with the capacity of 8MB and a memory block Flash 1 with the capacity of 4MB.
  • processors for example processor P 1 , serves as a master processor, and the other serves as a slave processor.
  • Processor P 2 is linked with memory block RAM 2 with the capacity of 8MB and with memory block Flash 2 with the capacity of 4MB.
  • each of the processors P 1 and P 2 uses two types memory: a non-volatile memory, for example Flash-type memory, for storing software code, and a volatile memory, for example a RAM memory, used for storing data and processing of the received signal.
  • a non-volatile memory for example Flash-type memory
  • a volatile memory for example a RAM memory
  • the cost of memory of a dual processor device is twice as high as the cost of memory system for a uniprocessor device.
  • the memory of the master processor is a non-volatile memory
  • the memory of the slave processor is a volatile memory
  • handling of a fast data transmission port is activated and the software of the master processor is copied to the memory of the slave processor through the activated fast data transmission port.
  • the first memory block also stores a file, which describes differences between the code, which should be in the second memory block, and the primary code of the first memory block. Based on that file changes are implemented in the code copied to the second memory.
  • Such method allows eliminating a separate memory block to store the code for the slave processor, thanks to which the cost of the whole system is decreased.
  • the presented system is designed particularly for digital television decoders, but it can be applied to other dual processor devices as well.
  • FIG. 1 shows a dual processor digital television decoder known from the prior art
  • FIG. 2 shows a typical memory system of a decoder shown in FIG. 1 ,
  • FIG. 3 shows a configuration of memory system according to the present invention
  • FIG. 4 presents the procedure of preparing the memory system according to the invention
  • FIG. 5 shows the procedure of initializing the memory system according to the invention
  • FIG. 6 illustrates exemplary contents of the volatile and non-volatile memory in the memory system in a dual processor device according to the invention.
  • the memory system according to the invention is designed for a dual processor device, which includes two identical processors, operating the same software.
  • the first processor is the master processor MP
  • the second processor is the slave processor SP. Both processors are coupled bidirectionally with each other.
  • the master processor MP is bidirectionally coupled with a volatile memory block RAM M with a capacity of 8MB, which serves as its operating memory and with a non-volatile memory block Flash M, which stores the software code, with a capacity of 4MB.
  • the slave processor SP is linked bidirectionally with a volatile memory block RAM S with a capacity of 8MB, which serves as its operating memory and with a volatile memory block RAM S1. which stores the software code, with a capacity of 4MB.
  • the conventional Flash memory of the slave processor SP is replaced with a RAM memory with the same capacity - marked as RAM S1.
  • the RAM S1 memory block may have the same capacity as the other two blocks RAM M and RAM S (8MB each), which allows, for example, storing additional data therein.
  • the maximum capacity of this memory is not limited. However, the minimum capacity cannot be smaller than the size of the software to be located there. Those skilled in the art will find that it is obvious to combine RAM S and RAM S1 into one block.
  • Flash-type memory is presented here only as an example of a non-volatile memory. It is evident that other types of non-volatile memory can be used as well.
  • the advantage of this system is a lower cost in comparison to the system from FIG. 2, because the RAM memory can be several times cheaper than the Flash-type memory. In this configuration, the cost of the memory system for a dual processor device is only slightly higher than the cost of memory system for a uniprocessor device.
  • Flash M memory the software for the main processor is stored, which is later (during memory initialization) copied to the RAM S1 memory of the slave processor.
  • the address space of the Flash-type memory is different than that of the RAM-type memory.
  • the code copied to RAM memory contains addresses referring to the address space of Flash memory. Since a memory of another type is connected to the slave processor, this would cause errors. In order to solve this problem, the values of addresses, to which the code instructions refer, should be changed so that they refer to the correct addresses space of RAM-type memory.
  • the Difference file may be as small as 30kB, which constitutes only 1% of the whole code.
  • the source of the differences between the code of the master processor ME and the slave processor SP is irrelevant.
  • the essence of the invention is such a memory configuration, in which in Flash M memory of the master processor MP there is stored the software of the master processor MP and the difference file, describing changes, which should be implemented in the main code, so that it can be executed from RAM S1 memory of the slave processor SP.
  • the procedure of initializing the decoder with the above described organization of memory is illustrated in FIG. 5 and includes the following steps:
  • the starting application of the master processor MP is activated, which is read from Flash M memory , and which initiates further actions.
  • a simple code of the starting application of the slave processor SP is sent to the slave processor SP.
  • This program allows the slave processor to perform basic functions, including the functionality of handling RAM S1 memory and handling other protocol, for sending the program code later.
  • the starting application can be sent by means of a JTAG port.
  • the code from Flash M memory is sent to RAM S1 memory by means of the slave processor SP.
  • the code can be sent by means of another, faster port - for example, UART or a shared memory port.
  • FIG. 6 presents exemplary contents of the Flash M memory of the master processor ME and RAM S1 memory of the slave processor SE.
  • the Flash M memory contains:
  • FIG. 6 Their placement in FIG. 6 is shown as an example only.
  • the arrows 1 , 2 and 3 indicate the subsequent steps of procedure shown in FIG. 5.
  • the starting application for the slave processor SJP is copied to the RAM S1 memory.
  • the code of the master processor ME is copied.
  • changes to the master processor code in the RAM S1 memory are implemented, on the basis of the difference file.
  • the correct code of the slave processor SE is stored in RAM S1 memory.
  • FIG. 6 also shows the memory addresses, from which separate fragments of codes begin.
  • the initial addresses AF1 and AR1 of these memories are different, due to different Flash and RAM memory address spaces used by the processors.
  • the addresses AF2 and AR2, which indicate the beginning of the appropriate codes for the master processor ME and the slave processor SE are different as well.

Abstract

A memory system in a dual processor device, in which one of the processors is a master processor (MP) and the second is a slave processor (SP). These processors have separate memory blocks, and the software of the master processor (MP) is stored in the memory block (Flash M) of the master processor (MP). By the invention, the memory block (Flash M) includes additionally data describing the differences between the software of the master processor (MP) and the software of the slave processor (SP). According to a method of initializing a memory system of a dual processor device, in the memory block (Flash M) of the master processor (MP) there are located additional data, describing differences between the software of the master processor (MP) and the software of the slave processor (SP), and during initialization of the system the starting application of the master processor (MP) is activated, the starting application of the slave processor (SP) is copied to the slave processor (SP) and next the software of the master processor (MP) is copied to the memory (RAM S1) of the slave processor (SP) from the memory (Flash M), and basing on the data, describing differences between the software of the master processor (MP) and the software of the slave processor (SP), changes are made in the content of the memory (RAM SI) of the slave processor (SP).

Description

MEMORY SYSTEM IN A DUAL PROCESSOR DEVICE AND A METHOD OF INITIATING MEMORY IN A DUAL PROCESSOR DEVICE
TECHNICAL FIELD
The invention relates to a memory system in a dual processor device and a method of initiating memory in a dual processor device, in which the processors operate the same software, executed in separate memory blocks. In particular, the device may be a digital television decoder.
BACKGROUND ART
Independent reception of television signal in two television receivers TV 1 , TV 2 typically requites independent signals to be supplied from two independent sources. For digital television, these sources may be digital television decoders, also called integrated receiver decoders (IRD), or set-top boxes (STB).
In order to minimize the costs of two decoders, the signal to television receivers TV 1 , TV 2 can be supplied from one decoder STB, which has a possibility of independent processing of two television signal streams.
Such digital television decoder STB is usually equipped with two interfaces of a remote control unit RCU INT 1 , RCU INT 2. Each interface is linked to one remote control unit RCU 1 , RCU 2. Such a configuration allows the user, for example, to receive the signal in the second receiver TV 2 in a room other than that in which the digital television decoder STB and the first receiver TV 1 are located.
To enable such functionality, one of the possible solutions is to install in the decoder a signal-receiving block with a processor, which can independently process two signals.
However, processors offering such functionality are advanced and quite expensive devices. Moreover, they require special software. Such software is not known to an engineer, who is acquainted in his day-to-day work with typical processors for processing only one television signal. Another solution to provide the above functionality is to use in the digital television decoder STB two independent signal processing blocks SPB 1 and SPB 2, with an independent processor in each block.
This solution is much simpler, because the processors can work independently from each other, based on the software similar to the one, which is used in a typical single processor system. Also the cost of a system using known processors can be lower from the system, in which a modem processor is installed. Configuration of such digital television decoder STB is presented in FIG. 1.
The processor, which is the main part of the signal-processing block SPB 1. SPB 2 performs descrambling, decompression and other operations on the processed signal. The operation of the processor is controlled by software, stored in memory.
A typical and obvious configuration of a memory system in a dual processor decoder is shown in FIG. 2. This configuration can also be used in other dual processor devices.
The system incorporates two processors, linked bidirectionally, i.e. processor P 1 and processor P 2. Processor P 1 is bidirectionally linked with a memory block RAM 1 with the capacity of 8MB and a memory block Flash 1 with the capacity of 4MB. One of these processors, for example processor P 1 , serves as a master processor, and the other serves as a slave processor. Processor P 2 is linked with memory block RAM 2 with the capacity of 8MB and with memory block Flash 2 with the capacity of 4MB.
Therefore, each of the processors P 1 and P 2 uses two types memory: a non-volatile memory, for example Flash-type memory, for storing software code, and a volatile memory, for example a RAM memory, used for storing data and processing of the received signal.. The most popular digital television decoders, at present, use the Flash-type memory of the capacity of 4MB and RAM memory of the capacity of 8MB.
However, installing two Flash memory blocks is not optimal in view of the high cots of this memory, which is especially higher than the cost of RAM memory.
Therefore, in the configuration presented in FIG. 2, the cost of memory of a dual processor device is twice as high as the cost of memory system for a uniprocessor device. DISCLOSURE OF THE INVENTION
It is an object of the invention to provide a memory system in a dual processor device, in which one of the processors is a master processor and the second is a slave processor, where the processors have separate memory blocks, and the software of the master processor is stored in the memory block of the master processor, characterized in that the memory block of the master processor includes additionally data describing the differences between the software of the master processor and the software of the slave processor.
Preferably, the memory of the master processor is a non-volatile memory, and the memory of the slave processor is a volatile memory.
It is another object of the invention to provide a method of initializing a memory system of a dual processor device, in which one of the processors is a master processor and the second is a slave processor, where the processors have separate memory blocks, and the software of the master processor is stored in the memory block of the master processor, characterized in that in the memory block of the master processor there are located additional data, describing differences between the software of the master processor and the software of the slave processor, and during initialization of the system the starting application of the master processor is activated, the starting application of the slave processor is copied to the slave processor and next the software of the master processor is copied to the memory of the slave processor from the memory of the master processor, and basing on the data, describing differences between the software of the master processor and the software of the slave processor, changes are made in the content of the memory of the slave processor.
Preferably, after activating the starting application of the slave processor, handling of a fast data transmission port is activated and the software of the master processor is copied to the memory of the slave processor through the activated fast data transmission port.
In the embodiment according to the present invention, because of the independent work of these processors, software is executed in separate memory blocks. In this configuration, in the first memory block there is stored the code of the software designated for the master processor, which is copied to the second memory block, used by the slave processor, at the initialization of the memory system, i.e. at start-up of the device.
The first memory block also stores a file, which describes differences between the code, which should be in the second memory block, and the primary code of the first memory block. Based on that file changes are implemented in the code copied to the second memory.
Such method allows eliminating a separate memory block to store the code for the slave processor, thanks to which the cost of the whole system is decreased.
The presented system is designed particularly for digital television decoders, but it can be applied to other dual processor devices as well.
BRIEF DESCRIPTION OF DRAWINGS
The object of the invention is shown in implementation examples shown in the drawings, in which:
FIG. 1 shows a dual processor digital television decoder known from the prior art,
FIG. 2 shows a typical memory system of a decoder shown in FIG. 1 ,
FIG. 3 shows a configuration of memory system according to the present invention,
FIG. 4 presents the procedure of preparing the memory system according to the invention,
FIG. 5 shows the procedure of initializing the memory system according to the invention,
FIG. 6 illustrates exemplary contents of the volatile and non-volatile memory in the memory system in a dual processor device according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
The memory system according to the invention is designed for a dual processor device, which includes two identical processors, operating the same software. The first processor is the master processor MP, and the second processor is the slave processor SP. Both processors are coupled bidirectionally with each other. The master processor MP is bidirectionally coupled with a volatile memory block RAM M with a capacity of 8MB, which serves as its operating memory and with a non-volatile memory block Flash M, which stores the software code, with a capacity of 4MB.
The slave processor SP is linked bidirectionally with a volatile memory block RAM S with a capacity of 8MB, which serves as its operating memory and with a volatile memory block RAM S1. which stores the software code, with a capacity of 4MB.
Therefore, in the system according to the invention, the conventional Flash memory of the slave processor SP is replaced with a RAM memory with the same capacity - marked as RAM S1.
In order to unify the construction of the memory system, the RAM S1 memory block may have the same capacity as the other two blocks RAM M and RAM S (8MB each), which allows, for example, storing additional data therein.
The maximum capacity of this memory is not limited. However, the minimum capacity cannot be smaller than the size of the software to be located there. Those skilled in the art will find that it is obvious to combine RAM S and RAM S1 into one block.
The Flash-type memory is presented here only as an example of a non-volatile memory. It is evident that other types of non-volatile memory can be used as well.
The advantage of this system is a lower cost in comparison to the system from FIG. 2, because the RAM memory can be several times cheaper than the Flash-type memory. In this configuration, the cost of the memory system for a dual processor device is only slightly higher than the cost of memory system for a uniprocessor device.
In Flash M memory the software for the main processor is stored, which is later (during memory initialization) copied to the RAM S1 memory of the slave processor.
In most of the known processors, the address space of the Flash-type memory is different than that of the RAM-type memory.
Since a typical software code of a digital television decoder cannot be relocated (which means that it has permanently written memory addresses, to which individual instructions of the code refer), a simple copy of the code from Flash memory to RAM memory is insufficient.
The code copied to RAM memory contains addresses referring to the address space of Flash memory. Since a memory of another type is connected to the slave processor, this would cause errors. In order to solve this problem, the values of addresses, to which the code instructions refer, should be changed so that they refer to the correct addresses space of RAM-type memory.
Therefore in the process of preparing the software for the decoder, it is necessary to make two separate versions: one, assigned to the master processor and executed in its Flash M memory, and the second, assigned to the slave processor and executed in the RAM S1 memory.
Because both processors use the same type of software is identical, there are only slight differences between the two versions, originating from different address space of Flash and RAM memory.
The content of the two code versions has to be analyzed and differences have to be found and written to a separate file, called in further description "a difference file". The procedure is illustrated in FIG. 4 and it comprises the following steps:
- Prepare master processor software,
- Prepare slave processor software,
- Find differences, \
- Create the difference file.
For a typical 3MB code the Difference file may be as small as 30kB, which constitutes only 1% of the whole code.
The differences originating from different address spaces of different memory types are given here as examples only. There may be also other differences present in the software of the slave processor SP - for example, other identifiers of devices, with which the slave processor SP cooperates.
However, for the method according to the invention, the source of the differences between the code of the master processor ME and the slave processor SP is irrelevant.
The essence of the invention is such a memory configuration, in which in Flash M memory of the master processor MP there is stored the software of the master processor MP and the difference file, describing changes, which should be implemented in the main code, so that it can be executed from RAM S1 memory of the slave processor SP.
It, is evident that such a method is useful mostly when the difference file is not too large - for example, not larger than 10% of the main code.
If the difference file had a capacity comparable to the main code, it would be more optimal to apply a typical solution, i.e. individual Flash memory block for each processor.
The procedure of initializing the decoder with the above described organization of memory is illustrated in FIG. 5 and includes the following steps:
- activate the master processor starting application
- send and activate slave processor starting application
- send the code from Flash M to RAM S1
- make changes in RAM S1
- activate code from Flash M
- activate code from RAM S1.
In the first step, the starting application of the master processor MP, is activated, which is read from Flash M memory , and which initiates further actions.
Using a low-level protocol, in the next step a simple code of the starting application of the slave processor SP is sent to the slave processor SP.
This program allows the slave processor to perform basic functions, including the functionality of handling RAM S1 memory and handling other protocol, for sending the program code later.
For example, the starting application can be sent by means of a JTAG port. After executing the starting application, in the next step the code from Flash M memory is sent to RAM S1 memory by means of the slave processor SP.
The code can be sent by means of another, faster port - for example, UART or a shared memory port.
After the code is sent, changes are made in the content of RAM S1 memory, based on information from the difference file, written in Flash M memory.
After making these changes, software from memory Flash M and RAM S1 can be executed, which results in a start of normal operation of both processors. For a better explanation of the method according to the invention, FIG. 6 presents exemplary contents of the Flash M memory of the master processor ME and RAM S1 memory of the slave processor SE. The Flash M memory contains:
- Starting program for the master processor ME,
- Starting program for the slave processor S_E,
- The code of the master processor,
- the difference file.
Their placement in FIG. 6 is shown as an example only.
The arrows 1 , 2 and 3 indicate the subsequent steps of procedure shown in FIG. 5.
In the first step the starting application for the slave processor SJP is copied to the RAM S1 memory. Next, the code of the master processor ME is copied. In the third step, changes to the master processor code in the RAM S1 memory are implemented, on the basis of the difference file. As a result, the correct code of the slave processor SE is stored in RAM S1 memory.
FIG. 6 also shows the memory addresses, from which separate fragments of codes begin. The initial addresses AF1 and AR1 of these memories are different, due to different Flash and RAM memory address spaces used by the processors. The addresses AF2 and AR2, which indicate the beginning of the appropriate codes for the master processor ME and the slave processor SE are different as well.

Claims

1. A memory system in a dual processor device, in which one of the processors is a master processor and the second is a slave processor, where the processors have separate memory blocks, and the software of the master processor is stored in the memory block of the master processor, characterized in that the memory block (Flash Ml of the master processor (MP) includes additionally data describing the differences between the software of the master processor (MP) and the software of the slave processor
(SE).
2. A memory system according to claim 1., characterized in that the memory (Flash M) of the master processor (MP) is a non-volatile memory, and the memory (RAM SD of the slave processor is a volatile memory.
3. A method of initializing a memory system of a dual processor device, in which one of the processors is a master processor and the second is a slave processor, where the processors have separate memory blocks, and the software of the master processor is stored in the memory block of the master processor, characterized in that in the memory block (Flash M) of the master processor (MP) there are located additional data, describing differences between the software of the master processor (MP) .and the software of the slave processor (SP). and during initialization of the system the starting application of the master processor (MP) is activated, the starting application of the slave processor is copied to the slave processor (SP) and next the software of the master processor (MP) is copied to the memory (RAM SD of the slave processor (SP) from the memory (Flash M) of the master processor (MP), and basing on the data, describing differences between the software of the master processor (MP) and the software of the slave processor (SP), changes are made in the content of the memory (RAM SD of the slave processor (SP).
4. The method, according to claim 3, characterized in that after activating the starting application of the slave processor (SP), handling of a fast data transmission port is activated and the software of the master processor (MP) is copied to the memory (RAM SD of the slave processor (SP) through the activated fast data transmission port.
PCT/PL2004/000009 2003-02-24 2004-02-20 Memory system in a dual processor device and a method of initialising memory in a dual processor device WO2004074977A2 (en)

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WO1990011567A1 (en) * 1989-03-21 1990-10-04 Siemens Nixdorf Informationssysteme Aktiengesellschaft Multiprocessor system
EP0483433A1 (en) * 1990-10-31 1992-05-06 International Business Machines Corporation Initialization method for the initialization of secondary stations in an information processing system
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PL358855A1 (en) 2004-09-06

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