WO2004097689A1

WO2004097689A1 - Activity profiling for controlling integrated circuit operation

Info

Publication number: WO2004097689A1
Application number: PCT/IB2004/050514
Authority: WO
Inventors: Francesco Pessolano; Jose D. J. Pineda De Gyvez; Rohini Krishnan
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-04-28
Filing date: 2004-04-26
Publication date: 2004-11-11

Abstract

Apparatus and method for controlling integrated circuit operation, comprising software means for generating simulated or estimated activity, and hardware control means for monitoring real-time activity of the integrated circuit. For every clock period the hardware retrieves (at step 200) the activity estimation for the next operation. This value may be adjusted (at step 202) with an offset previously calculated which is intended to correct the estimation so as to correspond with real, monitored activity of the chip. This value (i.e. the estimation value with the offset) is used (at step 204) to control the chip (module) as it is considered to better represent the activity of the next operation. When the next operation is being executed, the activity of the chip is also measured (at step 206), and this value is then used to generate an average of the activity of all previous operations (step 208). The measured average and the estimated one are compared (at step 210) so as to determine how accurate the estimate was, and an adjusting offset may be generated (at step 212) which is the difference between the two compared values.

Description

ACTIVITY PROFILING FOR CONTROLLING INTEGRATED CIRCUIT OPERATION

This invention relates to activity profiling for use in the control of working conditions of an integrated circuit, or part of it, in order to optimize its performance.

An important consideration in integrated circuit design is reduction of on-chip power consumption. The implementation of circuits and systems, particularly in new deep submicron technologies, requires arrangements to make the system performance successfully feasible. For example, the performance of a system on a chip (SoC) implemented in, say, lOOnm technology or beyond, may be severely hampered by excessive transistor leakage, the impact of local and global process variability, and reduced noise margins.

Various design techniques can be used to reduce power consumption on a chip. However, a designer first needs accurate information regarding the dynamic and static power consumption of the circuit under realistic operating conditions.

Power is dissipated in a circuit whenever a cell instance switches a signal from one voltage level to another. This switch in voltage level causes charging or discharging of capacitances which include pin capacitances, interconnect capacitances, and transistor capacitances (e.g. coupling capacitances distributed between the gate and source/drain terminals). Overshooting/undershooting of output signals, known as capacitive feedthrough effects, also impact power loss. In addition, due to level shifters, leakage currents, pull-ups and pull-downs, power also dissipates statically when the circuit is in quiescent mode. In the past, simple power consumption models, which consider only the charging and discharging of the gate output capacitance, have been used. However, these methods ignore the power consumption of the internal nodes of the gate. Particularly in the move to deep sub-micron technologies, the number of parameters needed to accurately model power behavior of a transistor has increased exponentially, ranging from fewer than 50 parameters at 1 micron to more than 1000 parameters at 0.5 microns. The simple transistor models used in prior art arrangements cannot account for this type of complexity. Hence, new methods for modeling and characterizing power behavior are needed, particularly for sub-micron process technologies. It is an object of the present invention to provide a template for a microarchitecture which exploits information regarding the activity of a chip, or part of the chip, required to be controlled. By activity it is meant how many nodes switch in the chip (module) for a given operation at a given time. In a clocked design, this would generally correspond to the switching per clock period. In a non-clocked design, it would generally correspond to the switching per cycle.

As the activity is directly related to the power and speed required by the chip (module) in order to perform a particular operation, this information can be used to modify the chip operating conditions (i.e. voltage and frequency) so as to ensure that the chip (module) is always working with the minimum required performance, thereby enabling power consumption to be optimized and tailored to whatever application is currently running on the chip. In prior art arrangements, such control can be achieved in two ways. In one such arrangement, the hardware itself monitors its activity and performs the control. In this case, however, the control action is based on what has already happened on the chip (or module) and may bear no relation to what is happening in real-time.

In another prior art arrangement, software is provided to control the hardware based on information estimated with techniques such as profiling, in which an application is run on a hardware description language (HDL) description of the core and its activity is estimated or simulated by means of computer aided design (CAD) tools. One such method is described in US Patent No. 5,838,947 which relates generally to a method for modeling, characterizing and simulating the power behavior of VLSI MOS circuit design at the gate- level. In the proposed method, both the static and dynamic power consumed by a cell for different logic conditions is characterized on all ports. Exhibited power behavior is modeled in terms of power-coefficients of the power dissipation model. These power-coefficients provide a mechanism to capture the different power consumption dependencies under varying state-vector conditions, input ramp and output load for different types of cells. The coefficients are used during simulation to compute the power consumed by the cell under applicable state-vector and circuit-conditions to which each cell instance is subjected in the circuit.

However, one major disadvantage of the above-described arrangement and all other control methods employing simulation techniques, is that the control action is never actually based on the real behavior of the chip (module), only the simulated, estimated or expected behavior thereof.

We have now devised an improved arrangement. In accordance with the present invention, there is provided apparatus for controlling integrated circuit operation, the apparatus comprising: i) means for receiving data representative of simulated or estimated integrated circuit activity for an operation thereof; ii) control means for controlling one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the apparatus being characterized by: iii) means for measuring integrated circuit activity during operation thereof; and iv) means for comparing said measured activity with said simulated or estimated activity and, and if a difference therebetween (or a difference greater than or equal to a predetermined threshold value) is detected, adjusting or replacing said simulated or estimated activity accordingly, to produce an operation control activity signal; said control means being arranged to control one or more parameters of an operation of said integrated circuit based on said operation control activity signal.

Also in accordance with the present invention, there is provided a method for controlling integrated circuit operation, the method comprising the steps of: i) generating or receiving simulated or estimated integrated circuit activity for an operation thereof; and ii) controlling one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the method being characterized by the steps of: iii) measuring integrated circuit activity during an operation thereof; iv) comparing said simulated or estimated activity with said measured activity, and, if a difference therebetween (or a difference greater than or equal to a predetermined threshold value) is detected, adjusting or replacing said simulated or estimated activity accordingly to produce an operation control activity signal; and v) controlling one or more parameters of an operation of said integrated circuit based on said operation control activity signal.

The present invention further extends to an operation control activity signal created using the above-defined apparatus or method.

Thus, the present invention combines the use of control hardware and simulation software to achieve improved control over the prior art arrangements. In one embodiment of the invention, the software may provide estimated information to the hardware. The hardware compares the estimated information with information it has measured, and the result of the comparison could then be used to adjust the estimated information before the adjusted estimated information (i.e. the resultant operation control activity signal) is used to effect chip control.

The apparatus may include means for generating the simulated or estimated integrated circuit activity. Such means is preferably provided as software (e.g. a CAD tool) separate from the integrated circuit. The control means is preferably provided as hardware on the integrated circuit itself. In the case where the simulated or estimated activity is adjusted to produce the operation control activity circuit, such adjustment may be achieved by adding an offset value which may be equal to or proportional to the difference between the simulated or estimated activity and the measured activity.

In another embodiment, if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between the simulated or estimated activity and the measured activity, the simulated or estimated activity may be replaced by the measured activity or a value proportional or derived therefrom.

In yet another embodiment, the simulated or estimated activity may be replaced or adjusted according to an entry in a look-up table. Means may be provided for storing the simulated or estimated activity, and means may also be provided for encoding the simulated or estimated activity prior to storage thereof.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:

Figure 1 is a schematic flow chart representative of a method of estimating chip activity for use in an exemplary embodiment of the present invention;

Figure 2 is a schematic flow diagram representative of a method of chip control according to an exemplary embodiment of the present invention;

Figure 3 is a schematic block diagram of control hardware according to an exemplary embodiment of the present invention; Figure 4 is a schematic block diagram of control hardware according to another exemplary embodiment of the present invention; and

Figure 5 is schematic block diagram of control hardware according to yet another exemplary embodiment of the present invention.

Referring to Figure 1 of the drawings, there is illustrated an exemplary method of generating simulated or estimated switching activity for use in an embodiment of the present invention. Such a method would be familiar to a person skilled in the art and will not be described in great detail herein. Suffice to say that software can be provided to generate estimation activity, in which, first, the application and hardware description language (HDL) description of the chip (module) after synthesis are compiled (at steps 100, 102 respectively). The chip (module) is then simulated (at step 104) with this application, and a profile generated. Such profile is subsequently used by (known) power estimation tools to provide information about the switching activity for every operation of which the application is composed (step 106). This information is then encoded at step 108 (in any known manner, such as, for example, by means of a numeric value) and stored (at step 110) such that it can be retrieved by the hardware (for example, in the application itself).

The above-described process can be modified in a number of different ways to achieve the same outcome, namely an activity estimation that can be retrieved by the hardware. For example, a group of operations may be used for the estimation, instead of the estimation step being performed for each individual operation. The resultant value may be attached to each operation of the group or to just the group itself. This may affect the scope of control as well, in the sense that control may be effected in respect of each individual operation or in respect of a group of operations.

Additionally, there are many different ways in which the estimation activity can be encoded, in the sense that its numerical value can be used, or a value relative thereto (for example, a previous value), or solutions such as fuzzy logic may be employed. Storage of the information may be effected. For example, by attaching the activity estimation to each instruction with a dedicated instruction field, or to a group with a dedicated instruction, or with a separate parallel program, or otherwise.

The activity estimation may involve repetitive simulations with different applications and/or input patterns to generate a weighted estimation, if desired. Many other permutations and variations will be apparent to a person skilled in the art, provided the end result is that the software has produced an activity estimation that the hardware can retrieve. The hardware of such an exemplary embodiment may operate as illustrated in the flow diagram of Figure 2 of the drawings. For every clock period (or cycle), the hardware retrieves (at step 200) the activity estimation for the next operation. This value may be adjusted (at step 202) with an offset previously calculated which is intended to correct the estimation so as to correspond with real, monitored activity of the chip. This value (i.e. the estimation value with the offset) is used (at step 204) to control the chip (module) as it is considered to better represent the activity of the next operation. When the next operation is being executed, the activity of the chip is also measured at step 206, and this value is then used to generate an average of the activity of all previous operations (step 208). At step 210, the measured average and the estimated one are compared so as to determine how accurate the estimate was, and an adjusting offset may be generated (at step 212) which is the difference between the two compared values. As in the case of the software described with reference to Figure 1 of the drawings, the above-described hardware embodiment may be modified in a number of ways, including, for example, performing each step for a group of operations instead of for each individual operation. It will be appreciated by a person skilled in the art that there are many different methods of measuring and activity and obtaining an average thereof, any of which may be used to perform these functions in an arrangement according to the present invention. The manner in which the comparison is made between the measured and averaged values to generate the adjusting offset may be in accordance with any suitable method, and the invention is not intended to be limited in this regard. In fact, the use of an offset may be avoided altogether by employing the estimation, the measured values or their respective averaged values instead an adjusted estimation value to perform the required control.

These and other modifications can be made without departing from the scope of the present invention, such that the result is that the hardware is then able to control the chip (module) by using a better estimation for the next operation (or group of operations) based on both software estimation and real-time measurement of chip (module) activity. Referring to Figure 3 of the drawings, a schematic block diagram of an exemplary embodiment of hardware for performing a method, such as that described with reference to Figure 2 of the drawings, is illustrated. In the illustrated embodiment, the hardware comprises a controller 300 for receiving the activity code (from the software), a core 302 (of the chip or module) for receiving input signals and generating output signals upon application of a set of signals forming an operation, and average activity monitor 304 for monitoring the real-time activity of the core 302 and generating an average thereof, an analogue-to-digital converter 306 for converting the output of the average activity monitor 304 into a digital signal for application to a comparator 308. The comparator 308 compares the average activity value with the average estimated activity value and generates an offset corresponding to the difference therebetween. The offset is then fed back to the controller 300.

An activity monitor is basically a unit that measures the difference between the previous state of a system and the current one for the same system. The larger the difference, the greater is the system activity. There are several ways to implement an activity monitor. The simpler one involves monitoring the supply current, which also gives the activity for the system. It is normally possible to measure the average current with circuits well known in literature and, thus, monitor the average activity.

Another possibility is to monitor the input and output of every flip-flop in the system. When inputs and outputs differ, there is activity. An activity monitor could also be built from here in a way that is obvious to the skilled in the art.

The embodiment of the hardware illustrated with reference to Figure 4 of the drawings, is similar in most respects to that of Figure 3, except in this case, it is the controller 300, and not the comparator 308, which generates the adjusting offset. Thus, the comparator delivers the measured average activity back to the controller 300, which then generates an adjusting offset value accordingly.

The embodiment of the hardware illustrated in Figure 5 is similar in most respects to that described with reference to both Figures 3 and 4 of the drawings. However, in this case, no adjusting offset is generated. Instead, if the comparator 308 determines that there is a difference between the average estimation activity and the average (real) activity, it generates a selection signal which is fed to the controller, the selection signal representing a selection between the estimation activity or the measured activity value for use in controlling the chip (module) operation.

Thus, in summary, the present invention can be used to augment the static profile mechanism (i.e. the use of simulation software to produce estimated activity values for use in controlling a chip or module) by using activity monitoring information (obtained in real time). As a basic idea, the system is being controlled by information statically provided by the application to the hardware. Such information is a representation of how much activity is involved in the operation of the hardware units of the chip (module). At the same time, the hardware itself measures the average activity and checks that this value corresponds (possibly within certain limits) with the value provided by the application. If this is not the case, the profile information used to control the hardware may be discarded, augmented or replaced. For example, in one embodiment of the present invention, if the statistical information is found not to correspond with the measured information, the statistical information is disregarded and average measured activity is used instead to control the chip (module). In another embodiment of the invention, if the statistical (estimated) information does not correspond with the measured information, the statistical information may be augmented - i.e. the difference between the average measured activity and estimated profile information may be used as an offset to all subsequent profile information until a new error is detected. In yet another embodiment of the invention, a correspondence (look-up) table may be provided for use in the event that the estimated activity value does not correspond with the measured activity value. The look-up table may contain a new activity value for a given application point (in respect of a given scenario) for use in controlling the chip or module (for example, such a new value may comprise the average measured activity). This type of table may also be used for instruction types instead of application points, as required.

Embodiments of the present invention have been described above by way of examples only, and it will be apparent to a person skilled in the art that modifications and variations can be made to the described embodiments without departing from the scope of the invention as defined in the appended claims. It will be further understood that the term "comprising" used herein does not exclude other elements or steps, "a" or "an" does not exclude a plurality, and a single processor or other unit may fulfil the functions of several means recited in the claims, without departing from the scope of the invention.

Claims

CLAIMS:

1. Apparatus for controlling integrated circuit operation, the apparatus comprising: i) means (300) for receiving data representative of simulated or estimated integrated circuit activity for an operation thereof: and ii) control means (300) for controlling one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the apparatus being characterized by: iii) means (304) for measuring integrated circuit activity during operation thereof; and iv) means (308) for comparing said measured activity with said simulated or estimated activity and, if a difference therebetween is detected (or if a difference therebetween greater than or equal to a predetermined threshold value is detected), adjusting or replacing said simulated or estimated activity accordingly, to produce an operation control activity signal; said control means (300) being arranged to control one or more parameters of an operation of said integrated circuit based on said operation control activity signal.

2. Apparatus according to claim 1, including means for generating said simulated or estimated integrated circuit activity.

3. Apparatus according to claim 1 or claim 2, wherein if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between said measured activity and said simulated or estimated activity, the simulated or estimated activity is adjusted to produce said operation control activity signal.

4. Apparatus according to claim 3, wherein said simulated or estimated activity is adjusted by an offset value which is equal or proportional to said difference.

5. Apparatus according to claim 1 or claim 2, wherein if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between said measured activity and said simulated or estimated activity, said simulated or estimated activity is replaced by said measured activity or a value proportional thereto to produce said operation control activity signal.

6. Apparatus according to claim 1 or claim 2, wherein if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between said measured activity and said simulated or estimated activity, an operation control activity signal is selected or generated in accordance with an entry in a lock-up table.

7. Apparatus according to any one of claims 1 to 6, wherein said control means

(300) is provided in said integrated circuit.

8. Apparatus according to claim 2, wherein said means for generating said simulated or estimated integrated circuit activity comprises software means separate from said integrated circuit.

9. Apparatus according to any one of the preceding claims, including means (302) for storing said simulated or estimated integrated circuit activity.

10. Apparatus according to claim 9, including means for encoding said simulated or estimated integrated circuit activity prior to storage thereof.

11. Apparatus according to claim 4, wherein said offset value is equal or proportional to a difference between an average estimation of previous operations and average measured activity of a current operation.

12. A method for controlling integrated circuit operation, the method comprising the steps of: i) generating (106) or receiving (200) simulated or estimated integrated circuit activity for an operation thereof; and ii) controlling (204) one or more parameters of an operation of said integrated circuit based on said simulated or estimated activity; the method characterized by the steps of: iii) measuring (206) integrated circuit activity during operation thereof:; iv) comparing (210) said simulated or estimated activity with said measured activity, and, if a difference between (or a difference greater than or equal to a predetermined threshold value) is detected, adjusting (212) or replacing said simulated or estimated activity accordingly to produce an operation control activity signal; and v) controlling (202, 204) one or more parameters of an operation of said integrated circuit based on said operation control activity signal.

13. A method according to claim 12, including storing (110) said simulated or estimated activity.

14. A method according to claim 13, including the step (108) of encoding said simulated or estimated activity prior to storage thereof.

15. A method according to any one of claims 12 to 14, including the step of adjusting (202) said simulated or estimated activity if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between said measured activity and said simulated or estimated activity.

16. A method according to claim 15, wherein said simulated or estimated activity is adjusted (202) by an offset value which is equal or proportional to said difference.

17. A method according to any one of claims 12 to 14, including the step of replacing said simulated or estimated activity with said measured activity or a value proportional thereto to produce said operation control activity signal if there is determined to be a difference (or a difference greater than or equal to a predetermined threshold value) between said measured activity and said simulated or estimated activity.

18. A method according to any one of claims 12 to 14 wherein said operation control activity signal is selected or generated in accordance with an entry in a look-up table.

19. An operation control activity signal generated in accordance with the apparatus according to any one of claims 1 to 11 or a method according to any one of claims 12 to 18.

20. Electronic data storage means on which is stored an operation control activity signal according to claim 19.